Method of applying activation schemes to digitally controlled segmented RF power transmitters

Abstract

A method of applying an activation scheme to a digitally controlled segmented RF power transmitter having a plurality of adjacent segments (3), each segment (3) having an associated activation zone, the segments (3) being controlled by one or more code words (CWD). The method comprises controlling the segments (3) by activating a particular segment (3) using an activation scheme for activating the particular segment (3) in accordance with a code word (CWD), the activation scheme starting from a central segment of the plurality of segments (3) and proceeding towards an outer segment of the plurality of segments (3) with increasing code word (CWD) values. The method can be applied to any digitally controlled segmented RF power transmitter, whether in a polar implementation or in a Cartesian implementation, and whether in a single-ended output configuration or in a push-pull output configuration.

Description

Technical Field

[0001] This invention relates to optimal activation of unit cells in a digital transmitter (DTX) switch group or segmented output stage, or more specifically, to a method for applying an activation scheme to a digitally controlled segmented radio frequency (RF) power transmitter having multiple adjacent segments, each segment having an associated activation region, the segments being controlled by a codeword CWD. Background Technology

[0002] Transmitters used in wired and wireless systems are traditionally analog in nature for their RF front-end 105, such as... Figure 1 A general block diagram is shown. This transmitter includes a digital input processing section 101 for directly converting digital baseband information to the analog domain using a baseband digital-to-analog converter DAC 103 controlled by a clock 104. This digital baseband information is typically generated by an in-phase (I / Q) signal output from an I / Q baseband processing unit 102. BB ) and orthogonal (Q BB The transmitter also includes an RF front-end 105, which uses a low-pass filter 108 to process the analog signal output from the DAC 103 to remove sampled copies. Next, an analog quadrature mixer configuration is used for quadrature frequency up-conversion, thereby providing an amplitude- and phase-modulated RF signal (RF... mod The analog quadrature mixer configuration includes a local oscillator 107, a phase shifter 106, a multiplier 109, and an adder 110. The signal is amplified by a series of amplification stages (driver 111) and a power amplifier 112 to bring the RF output signal 7 to the desired level before it is transmitted by the antenna.

[0003] To meet the EVM and spectrum requirements of wireless standards (such as 3GPP), all electronic functions need to behave linearly and should not produce any distortion in the transmitted RF signal 7. Furthermore, the wireless transmitter also needs to be energy efficient. In analog design, these are often conflicting requirements, resulting in many trade-offs in the design of the wireless transmitter. Additionally, the RF front-end 105 is typically implemented using different semiconductor device technologies, such as CMOS for the digital baseband section, RF CMOS, SOI, or SiGe for the low-power analog section of the RF front-end 105, while GaAs, LDMOS, or GaN technologies are typically used to implement the power amplifier 112 (when targeting transmitter power greater than 1W). This results in low integration, high cost, and logistical issues. The inaccuracies inherent in analog circuitry are the cause of LO leakage, poor image suppression, and therefore the need for complex IQ calibration. Furthermore, the analog characteristics of the RF front-end 105 require (high) quiescent current to achieve sufficient linearity. This leads to significant power consumption under low traffic conditions or even in "off" mode operation. Typically, power amplifier 112 utilizes efficiency enhancement techniques, such as supply voltage modulation or Dougherty operation, to improve its efficiency in power back-off operation (PBO). However, the analog characteristics of the circuit here can also introduce defects and / or inaccuracies, which in practice limit the achievable peak efficiency as well as the efficiency of power back-off.

[0004] Recently, direct digital-to-RF upconversion techniques have been introduced to avoid the problems and limitations associated with analog transmitter implementations. These techniques are also referred to as RFDACs or RF hybrid DACs. When covering the entire digital transmitter (including the output power stage), they are called digital (dense) transmitters (DTX), or direct digital RF modulators (DDRM).

[0005] To date, prior art digital transmitter (DTX) implementations have been almost entirely limited to a few watts of RF output power. This allows them to use a very compact size for the switching groups in their output stage (power amplifier 112). Thus, these implementations can be considered electrically small and only affected to a limited extent by the current redistribution effects that generate irregularities in their digital baseband (e.g., due to codeword CWD) to their RF output signal transmission. Therefore, prior art DTX implementations are not very sensitive to their actual switching group layout implementation and the associated TX unit cell activation. This changes significantly when targeting higher power levels (i.e., greater than 10W). In such high-power implementations, the implemented switching groups are no longer electrically small compared to their operating frequency. Consequently, RF output current distribution effects occur due to the digitally controlled activation of their TX unit cells, severely degrading the quality of CWD-to-RF output transmission (i.e., CWD-AM and CWD-PM transmissions). These irregularities and disruptive behaviors in this transmission are difficult to correct through signal processing and / or DPD arrangement. Therefore, it significantly limits the achievable "noise floor" and the spectral purity of the output signal in contemporary power DTX implementations. Summary of the Invention

[0006] This invention seeks to provide a solution to problems related to (RF) current distribution effects that occur in the digital control segmented output stage of a transmitter.

[0007] According to the present invention, a method as defined above is provided, comprising: controlling the plurality of segments by activating the specific segment using an activation scheme that depends on the codeword CWD to activate the specific segment of the plurality of segments, the activation scheme proceeding from the center segment of the plurality of segments toward the outer segments of the plurality of segments to increase the codeword CWD value. Furthermore, these segments are activated such that current redistribution (e.g., as used in a Cartesian setup) resulting from using multiple activation moments to achieve the RF output waveform during an RF cycle is minimized.

[0008] These DTX segmented output stages can have a combination of thermometer encoding (potentially multi-stage) and / or binary encoding, and can include multiple switch groups with unit elements or segmented power output stages (e.g., in a Dougherty configuration). Digital predistortion (DPD) arrangements can be used to correct for (residual) linearity defects. Unlike earlier DAC, ADC, or DTX operations, the objective of this invention is not to reduce the absolute error (INL) of the CWD-RF output signal transmission due to the uncorrected segmented output stage / switch group performance. Instead, the objective of this invention is to overcome the interrupted and irregular characteristics that occur in the CWD-RF output signal transmission of prior art DTX implementations (even at the cost of a slight increase in the absolute error of the uncorrected switch group performance). The CWD-RF output function is made as smooth and monotonic as possible. This is achieved by applying an innovative activation scheme to the unit cells in the (electrically large) switch groups or segmented output stages of the DTX. That is, monotonic CWD-RF output signal transmission can be achieved by implementing strictly symmetrical activation. This monotonic behavior results in a smaller memory effect and allows for a significant reduction in the required predistorter complexity and its associated data interpolation algorithm, while it can still carefully correct for absolute transmission errors, thus providing significantly reduced TX “noise” and higher spectral purity. Attached Figure Description

[0009] The invention will now be discussed in more detail with reference to the accompanying drawings, in which: Figure 1 A block diagram of a prior art generic transmitter with an analog RF front end is shown; Figure 2 A schematic diagram of a generalized polar digital dense emitter (polar DTX) is shown; Figure 3 a) to Figure 3 e) shows the DTX signal representation for polarity, unsigned Cartesian, signed Cartesian, constellation mapping (interlaced) signed Cartesian, and (eight-phase) multi-phase / poly-phase implementations; Figure 4 A block diagram of the Cartesian Digital Dense Transmitter (Cartesian DTX) is shown. Figure 5 A block diagram of a multiphase digital dense transmitter (multiphase DTX) is shown; Figure 6 A block diagram of an interleaved (generalized multiphase) digital dense emitter (interleaved DTX) is shown; Figures 7A-7B A top view and a detailed top view of a switch assembly used in an embodiment of a first-generation digitally controlled segmented RF power transmitter are shown. Figure 8An example of a multiphase output waveform using a 25% duty cycle is shown, where A = 0.25 and B = 0.70; Figure 9 A logic circuit diagram of a decoder circuit applied in an embodiment of the present invention is shown; Figure 10 A logic circuit diagram of the second decoder circuit applied in an embodiment of the present invention is shown; Figure 11 A schematic diagram of a second decoder circuit array for controlling a segment array in a switch group is shown according to yet another embodiment of the present invention; Figure 12 A logic circuit diagram of the third decoder circuit applied in an embodiment of the present invention is shown; Figure 13 A schematic diagram of a third decoder circuit array for controlling a segment array in a switch group is shown according to yet another embodiment of the present invention; Figure 14 A schematic diagram of a DTX switch group according to an embodiment of the present invention is shown; Figure 15 A schematic diagram of a DTX switch group according to yet another embodiment of the present invention is shown; Figure 16 A schematic diagram of the switch assembly of DTX according to a push-pull embodiment of the present invention is shown; Figure 17 A schematic diagram of the switch group of DTX according to yet another possible push-pull embodiment of the present invention is shown; and Figure 18 A schematic diagram of a symmetrical push-pull switch assembly of DTX according to yet another possible push-pull embodiment of the present invention is shown. Detailed Implementation

[0010] Digital dense transmitters (or digital transmitters, DTX) are considered candidate building blocks for enabling new applications such as mMIMO 5G networks in a cost-effective and energy-efficient manner. An example of such a digital dense power transmitter is described in patent application NL-A-2024903 by the same applicant, which has not yet been published and is incorporated herein by reference. As described herein with reference to several exemplary embodiments, the objective of embodiments of the present invention is the optimal implementation of control of a segmented power amplifier stage to achieve monotonic and smooth CWD-AM (codeword-to-amplitude modulation) and CWD-PM (codeword-to-phase modulation) transmission. These embodiments can still be combined with digital predistortion (DPD) methods / algorithms, but since the transfer functions of CWD-AM and CWD-PM are monotonic and do not exhibit bulges or other irregularities, DPD can be avoided, or the relevant DPD model of the transmitter or the relevant data interpolation of the transmitter can be strongly simplified, while DPD can be applied more easily and efficiently.

[0011] To illustrate the advantages of the embodiments of the present invention, first consider as follows: Figure 7A and 7B The performance of the first-generation power LDMOS switch bank layout shown has been applied in higher power / electrically large polarity DTX architectures. While embodiments of the present invention can also be applied in principle to polarity operation, they are particularly advantageous in Cartesian and / or multiphase / multi-phase DTX implementations. Based on input baseband I... bb and Q bb In these signal concepts, the activation of unit cells / gated segments in the (interleaved) switch group configuration is controlled. This involves multiple unit cells / gated segments with different control clock phases (activation times), which can lead to large irregularities or, in more extreme cases, even non-monotonic behavior. Thus, it should be noted that embodiments of the invention can be applied to various DTX operating modes, such as, but not limited to, polarity, Cartesian, multiphase / multiphase operation in their single-ended or push-pull implementations, while operating as independent TX arrangements or embedded within Dougherty or out-of-phase arrangements, or as other efficiency-enhancing TX arrangement operations.

[0012] Figure 2 A schematic diagram of a generalized polar digital dense emitter (polar DTX) is shown. In this polar DTX architecture, depending on its exact properties (raw IQ data or data that has been slightly filtered and resampled), the raw IQ... BB and Q BB The data can be partially resampled and interpolated before predistortion in DPD unit 131, and then further upsampled and low-pass filtered in upsampling and interpolation unit 130 (the combination of upsampling and filtering is also called interpolation / resampling) to obtain I. c and Qc Data. Note that this sequence is typically constrained by the computational speed of the DPD unit. Next, the CORDIC unit 129 acquires the upsampled I... up and Q up The data is processed and transferred from a Cartesian signal representation to a polarity signal representation. Before recombining the components in the output "switch" group 121, the resulting amplitude (AM or envelope ((ρ)) and phase (PM or φ) digital signal representations are adjusted in their time alignment using delay alignment units 128 to compensate for delay differences in the AM and PM signal paths. The resulting AM signal is fed to a digital amplitude decoder 127, which controls the number of active output unit units 122 in the switch group 121. The output signals of the digitally controlled unit units 122 are combined in the analog domain using a power combination arrangement 120. The more unit units 122 are activated, the stronger the signal RF... out A higher output current / power is indicated by a 7. a The signal digitally controls phase modulator unit 126, which adjusts the phase of the local oscillator signal from local oscillator 107. The resulting phase-modulated signal is fed to buffer 125, which provides a "digital" phase-modulation clock that drives unit 122 in the output stage. Amplitude and phase information are (re)combined in the output stage to construct an amplitude and phase-modulated output signal (RF). out When not all unit cells 122 are activated, a clock signal gating can be applied to save clock tree power under PBO conditions. For good output signal quality, it is important that the RF signal obtained from switch group 121 is monotonic in nature and free from spurious signals or other interference, resulting in smooth behavior. However, achieving such smooth behavior is often a challenge in practical implementations. The power combination arrangement 120, combined with the output impedance it will provide to unit cells 122 and the control of unit cells 122, will set the operating class of the output stage. Assuming that the appropriate phase and drive conditions of these switch groups 121 are related to the nature of the Dougherty output power combiner used, multiple of these switch groups 121 can be used with an efficiency enhancement concept similar to Dougherty.

[0013] Polar transmitters offer advantages in terms of efficiency and output stage power utilization, and due to their fairly independent amplitude and phase behavior, they are relatively easy to correct for their defects. This allows for the use of 2×1-dimensional DPD correction schemes (AM-AM and AM-PM) in DPD unit 131 in many practical cases. Note that in the architecture shown, this “polarity” correction is accomplished using the IQ representation of the signal. In some architectures, these corrections are performed after CORDIC. A significant drawback of polar architectures is the bandwidth spread that occurs when transmitting the raw Cartesian baseband I and Q data to its amplitude (ρ) and phase (φ) representations (see Table 1 below). This requires nonlinear operations for phase and amplitude, which indeed causes this bandwidth spread. In practice, this means that the bandwidth (sampling rate) that the phase modulator 126 and amplitude decoder 127 need to provide is typically a factor (~5x) higher than the bandwidth of the raw baseband signal to be represented. This spread imposes severe constraints when operating with very large bandwidth signals (e.g., above 80 MHz). More importantly, the delay difference (multiple) between the envelope and phase path limits the use of signals with large modulation bandwidths because it significantly and linearly affects the in-band and near-spectral purity of the communication system. This is why polar architectures are considered less suitable for handling recently emerging communication standards such as fifth-generation (5G) wireless networks, which aim to use modulation bandwidths of up to 400 MHz in sub-6 GHz systems.

[0014] Figure 3 a) to Figure 3 e) shows the DTX signal representations for polarity, unsigned Cartesian, signed Cartesian, constellation-mapped Cartesian, and multiphase implementations, which will be referenced in the description below. For multiphase implementations, the following table provides examples for 8 phases: Figure 4 A block diagram of the Cartesian Digital Dense Transmitter (Cartesian DTX) is shown. To overcome the bandwidth limitations of the polarized DTX architecture, the Cartesian DTX architecture has recently attracted more attention for broadband applications (e.g., modulation bandwidth > 80 MHz).

[0015] Cartesian (I / Q) [Alavi, MTT 2012] and polyphase DTX are generally considered superior to their polar counterparts in terms of bandwidth because they are based on linear (vector) summation rather than using nonlinear equations, which (to some extent) avoids the bandwidth spread found in polar systems. Closer tests show that this is entirely true for unsigned Cartesian operations. However, for signed Cartesian and polyphase operations, switching between clock phases is used to select the appropriate quadrant / sector (i.e., signed I / Q TX requires clock phase modulation). This switching between clock phases can also be considered as broadband phase modulation, which also introduces bandwidth spread; however, unlike polarity, this is done in a synchronous clock state, which allows for a much simpler implementation of correlated phase mappers (very low-resolution phase modulators implemented using clock selection) than in the polarity case where continuously changing phases are required. The Cartesian concept will be explained first, and then generalized to the polyphase concept. Polyphase operations were first reported in [Matsuura, 2011] and [Wang, 2010].

[0016] In Descartes DTX (see Figure 4 ), I BB and Q BB The data can be pre-distorted by DPD unit 131, and then further upsampled and interpolated in upsampling and interpolation unit 130. The upsampled I... up and Q up Provided to digital codeword decoders 135-I and 135-Q, they transmit the original (binary) codeword (I1) in a (thermos-like) form suitable for controlling the activation of unit cells 122 in I1 switch group 121-I and Q1 switch group 121-Q. up and Q up Note that using thermometer encoding reduces spurious signals and mismatches in the electrical performance of unit cell 122. For higher efficiency, signed Cartesian operations are typically used, along with measures to avoid clock phase switching (see [link]). Figure 3 b) and Figure 3 Unlike the unsigned I / Q operation in c), in the signed Cartesian operation, unit cell 122 will not be activated when the expected output signal is zero. This is because such a signed Cartesian operation exhibits efficiency behavior similar to that of class B, which is the opposite of the unsigned Cartesian operation, which has efficiency behavior or is similar to that of class A operations.

[0017] In a signed I / Q DTX configuration, the local oscillator signal from local oscillator 107 is converted by phase generator 132 into four clock signals with a (constant) 90-degree phase shift relative to each other ([Alavi, ASSCC 2011]). Thus, these clocks are uniformly distributed over 360 degrees, or in other words, uniformly distributed over the RF cycle of the TX carrier frequency. These (phase-shifted) clocks require a sign-bit clock phase mapper 133 to address four quadrants. This quadrant selection is determined by the I and Q sign bits (I... sign and Q sign The phase-switching clock obtained from the sign bit clock phase mapper 133 provides the required activation time in the RF cycle to the unit cells 122 in the switch groups 121-I and 121-Q via the clock gating and buffer unit 134.

[0018] Unlike the CORDIC-controlled phase modulator 126, which provides a polarity system with a "continuously" (gradually) changing phase, the signed Cartesian operation is characterized by switching between four (constant-phase) clock signals at synchronized times. Another advantage is that the I and Q signal paths are identical in hardware nature, as this timing misalignment between them is smaller compared to polarity DTX. This, combined with its synchronized nature, allows for the retiming of the clock tree signals, as well as the retiming of the (upsampled) baseband information. This allows for reduction of the effects of delay mismatch and other timing inaccuracies in practical implementations.

[0019] However, I / Q and multiphase DTX (see Table 1 and Figure 3 a) to Figure 3 The units 122 in the switch group 121 (e) suffer from (signal) interactions between the activated units within their switch group. This is primarily caused by the simultaneous use of different clock phases (all "on") when activating the units 122 within an RF cycle. This interaction is typically most severe at higher power levels, where a large number of activated units 122 in the switch group 121 cause a decrease in the effective output impedance of the switch group 121. This results in the electrical behavior of the switch group beginning to deviate from that of the current source, making it susceptible to interactions between units 122 activated by different phases. This leads to poor I / Q picture suppression and other sources of signal distortion.

[0020] Using non-overlapping clocks in DTX switch group operation of Cartesian [Alavi MTT 2014] and multiphase transmitters can significantly reduce these interactions. This is achieved by using only one clock phase when activating unit cell 122. In Cartesian operation, this non-overlapping condition results in a duty cycle of 25% or less for the activation of unit cell 122 in switch group 121. For multiphase operation using non-overlapping clocks, the required duty cycle becomes even shorter (e.g., 12.5% ​​in an eight-phase DTX). The use of such a (very) short duty cycle clock presents implementation challenges at higher operating frequencies (e.g., above 3 GHz). Therefore, the use of overlapping activation clocks can still be beneficial for these multiphase DTX concepts.

[0021] Figure 5 A block diagram of a multiphase digital dense transmitter (multiphase DTX) is shown. In a Cartesian DTX, the multiphase system uses more than four phases to drive the unit cells 122 in their switch groups 121. In particular, using eight phases appears to be a suitable number (see [link to diagram]). Figure 3 Using more phases (e.g., 8 or 16 phases) allows for a smaller phase angle difference between the clocks driving the switch group 121. Therefore, the resulting analog “vector” summation is less perpendicular (e.g., 45 degrees) compared to the Cartesian case (90 degrees). This lower phase difference in the signal summation increases the efficiency of the off-axis constellation points (compared to Cartesian DTX) and approaches the efficiency of a polarized system when using many phases (e.g., 16 or more). Furthermore, because the summed “vectors” are more “aligned” in their directions, less severe undesirable interactions occur between the outputs of the activated unit cells 122 operating on different phases compared to the Cartesian case, resulting in a more perfect summation of the output signals they produce. Therefore, some overlap in the active clocks of the unit cells 122 driving the switch group 121 is still acceptable if the phase difference is limited (e.g., 45 degrees or less). Thus, in a practical multiphase concept, a tradeoff can be found between lower interactions (higher linearity and efficiency) and output power. This also allows for a balance between technical constraints on switching speed and output power. However, in Cartesian and multiphase DTX implementations, the duty cycle used when timing unit cells is preferably kept below 50%. In particular, a 25% clock duty cycle is considered a good trade-off in terms of efficiency and output power capability. It can be shown that a 33% duty cycle also offers specific advantages in providing low third harmonic content output.

[0022] Regarding the organization and activation of switch group 121 and unit cell 122 in a polarity DTX, the following observations can be made. In a single-ended polarity DTX, all unit cells 122 share the same phase-modulated “digital” clock to control their activation time and the duration of that activation. This duration is typically set by the duty cycle of this phase-modulated clock. When using operations like Class B or Class C, using a shorter duty cycle is advantageous for achieving higher peak efficiency (e.g., for a square wave with a 50% duty cycle, the theoretical peak efficiency is 63.6% when all harmonics of the output stage are short-circuited, while for a 25% duty cycle, this increases to 90% [W. Gaber ESSCIRC 2011 and W. Gaber TMTT 2017]). Since all unit cells 122 use the same clock signal, only one switch group 121 is needed, as... Figure 2 As shown, and the clock tree is relatively simple, however, practical implementations may suffer from spurious signals and non-monotonic behavior (e.g., device matching and / or current redistribution effects) in their CWD-AM and CWD-PM transmissions due to defects in the implemented thermometer and / or binary bits. This introduces errors in both the amplitude and phase of the resulting overall output signal. Note that the CWD-RF output (whose integral nonlinearity (INL)) is preferably monotonic.

[0023] To improve the spectral purity of the DTX configuration, push-pull single-ended operation is generally considered preferable. This is due to the inherent suppression of even-order harmonic products and the suppression of substrate and noise supply in the push-pull architecture. In this configuration, the clock tree is typically implemented in a complementary or (pseudo)differential configuration. Therefore, in a push-pull polarized DTX structure, typically two phase-modulated "digital" clocks, not one, are used to activate the unit cell 122. To implement the push-pull output stage, two separate switch groups 121 or a push-pull oriented switch group 121 can be used, connected to a differential power combiner 120 or a balun. Note that in the polarized system, the sum of the total output current / output power of the unit cell 122 also sets the peak output current / power capability of the polarized DTX. Since all unit cells 122 are driven by the same phase (or by two 180-degree phase shifts in the push-pull configuration), the current / power utilization of the unit cell 122 in the polarized architecture is the highest among all DTX configurations. Therefore, the associated (summed) output capacitance and losses of unit cell 122 in this configuration are the lowest for a given output current / power for all DTX configurations.

[0024] To reduce the DC power required by the clock tree and its associated buffers, dynamic clock tree activation can be used. In this approach, the clock signals to these unit cells 122 can also be activated or omitted based on the amplitude codeword activated by the control unit cell 122 [Alavi TMTT 2014]. This output power-based clock tree activation (hereinafter referred to as clock gating) helps improve the overall efficiency of DTX under output power back-off (PBO) conditions.

[0025] Regarding the organization and activation of the switch group 121 and unit cell 122 in Cartesian DTX and multiphase DTX, the following observations can be made. First-generation Cartesian DTXs often use one interdigitated or two separate push-pull switch groups 121 (…). Figure 4 In these designs, the unit cells 122 of these groups 121 always perform... Operation is restricted and cannot be dynamically changed to another clock phase [Morteza, 2014]. In this configuration, when operating on the I or Q axis (see...), Figure 3 In c), for example, assuming the maximum operation along the "I-axis", all / The unit is "connected", while all The unit is "disconnected". Therefore, when comparing a Cartesian DTX using separate I and Q units to a polarized DTX case, twice the number of unit units 122 are needed to provide the same peak output capability along the I and Q axes (assuming the unit units in the two DTX concepts are equal in terms of output current / power). For a Cartesian DTX using this concept, this results in twice the output capacitance and output loss, improving the efficiency and bandwidth limitations of practical implementations compared to similar polarized architectures.

[0026] In multiphase DTX, a separate set of unit cells 122 is also used to operate on the active phases (A and B) to produce a consideration equivalent to the Cartesian DTX described above.

[0027] To overcome the poor output stage current / power utilization in the Cartesian and multiphase methods, two separate switch groups 121 (interleaved switch group 121-i) are introduced [Jin ISSCC 2015, Mehrpoo RFIC2017]. Figure 6 A block diagram of an interleaved (generalized multiphase) digital dense emitter (interleaved DTX) is shown, wherein it has... Figure 5 Components / units with similar functions in the block diagram have the same reference numerals.

[0028] In the interleaved configuration, only one (push-pull) switch group 121-i is used, where its unit cell 122 can be activated by "any" of the provided clock phases to represent I, Q (Cartesian) signals, I', Q' (mapped Cartesian) signals, or to represent A or B signals (multiphase). This allows all unit cells 122 to be used for I or Q (or, similarly, for I' or Q', or for A or B) if desired. This configuration better approximates the polarity case in terms of efficiency or output power when the maximum power output conditions of the constellation diagram are arranged such that they occur along the I and Q axes or in the phases used to drive groups A and B.

[0029] In Cartesian operations, this can be achieved by using constellation mappings (see Table 1 and...). Figure 3 This is achieved by using d) in the example. For instance, it can be achieved by using a mapping representation of I and Q. and This effectively achieves a 45-degree rotation of the original IQ diagram [Shen, RFIC 2020]. The advantage of this mapping is that, for the maximum amplitude (outer corner of the constellation diagram), all unit cells 122 are activated only by either the I' or Q' clock. Compared to a comparable "conventional" Cartesian DTX configuration, this allows for a factorial reduction in the required output stage current (or the number of unit cells). The peak output power level is reduced to the same level. Furthermore, since the unit cells 122 share the same drive phase for the highest output power, the IQ interaction is also slightly reduced. Note that the multiphase DTX concept using interleaved operation for their unit cells 122 also benefits from comparable considerations, although rotating the original IQ constellation diagram is not necessary here. That is, they also show the interaction along their activation axes ( Figure 3 a) to Figure 3 The highest output current / power of e).

[0030] Note that when using proximity or Under certain conditions, the Cartesian and multiphase DTX implementations are still worse than the polarized implementations due to the phase difference between the associated clock signals and the overall increase in effective duty cycle resulting from the combined output signals, which reduces efficiency. However, compared to the conventional Cartesian implementation using separate I and Q groups, the output loss and output capacitance of the switch group 121 used in the interleaved Cartesian implementation are reduced by a factor of [missing information]. Therefore, it is closer to the output loss and output capacitance of a polarized DTX solution implemented in the same technology.

[0031] The operation of the interleaved switch group 121 / unit cell 122 is often implicitly associated in the literature with the use of a non-overlapping activation clock [Wentzloff, 2019]. As previously mentioned, when correctly implemented, a non-overlapping clock is expected to provide lower IQ interactions between the activated unit cells 122. For a Cartesian system, this would require a 25% duty cycle clock to obtain the activation signal for the unit cell 122. When considering a multiphase system, even smaller clock duty cycles are required to guarantee the non-overlapping condition in the activation of the unit cell 122. That is, when using 8 phases, a 12.5% ​​duty cycle (or less) is required. However, using such a low duty cycle (although beneficial for theoretical efficiency) also limits the output power capability of the interleaved group (by a factor of ~2.5 compared to 50% square wave duty cycle operation). Furthermore, clock tree and unit activation using short duty cycle operation become increasingly challenging at higher operating frequencies (e.g., 3 GHz).

[0032] For these reasons, using a slightly higher duty cycle clock (e.g., 25%) in the case of multiphase DTX may still be beneficial. Although there is overlapping clocking again in this case, the reduced phase angle between the activated unit cells 122 tends to reduce their interaction, and the combined duty cycle (phase angle difference + applied duty cycle) can still be low enough (well below 50%) to achieve good efficiency with good output power.

[0033] Note that it is still possible to use overlapping clocks within an interleaved switch group 121. Since all unit cells 122 will use the same active phase on the axis between segments, when in the intermediate case on the outer contour of a multi-segment structure, the switch group unit cells 122 are driven by one or the other active driving phase, their ratio gradually changing as they travel between segment axes. Unit cells 122 are driven on either the I / A clock or the Q / B clock (Cartesian / multiphase case). Because when driven by multiple phases within an RF cycle, the RF output contribution of unit cell 122 will not be proportionally perfected, as unit cell 122 itself still requires non-zero time to turn on or off. Thus, even with non-overlapping clocks, using one unit cell 122 (e.g., in a Cartesian DTX of a constellation map) to first represent I' and then the next Q' within an RF cycle will give different results than having one unit cell 122 representing I' and another unit cell 122 representing Q' in the same RF cycle. In summary, the available unit cells 122 in the interleaved switch group 121-1 can be assigned to I' or Q' (constellation mapping Cartesian) or to phase A or B (multi-phase), or they can be inactive. In a push-pull implementation, a unit cell can be considered as a push element and a pull element with shared activation logic. Logically, their clock assignment can be changed in the next RF cycle.

[0034] Furthermore, note that single-ended interleaving uses two clock phases within one RF cycle, while push-pull interleaving uses four phases.

[0035] References: [Alavi RFIT 2011]Morteza S. Alavi, Robert B. Staszewski, Leo CN deVreede;, John R. Long, Orthogonal summing and power combining network in a65-nm all-digital RF I / Q modulator, 2011 IEEE International Symposium onRadio-Frequency Integration Technology, year 2011 [Gaber, ESSCIRC 2011]W. Gaber, et al., “A CMOS IQ Direct digital RFmodulator with embedded RF FIR-based quantization noise filter” ESSCIRC 2011,pp. 139-142. [Alavi, ASSCC 2011]Morteza S. Alavi, Akshay Visweswaran, Robert B.Staszewski, Leo C.N de Vreede, John R. Long, Atef Akhnoukh, A 2-GHz digitalI / Q modulator in 65-nm CMOS, IEEE Asian Solid-State Circuits Conference 2011,2011 [Alavi, MTT 2012]Morteza Alavi, Robert Bogdan Staszewski, L.C.N. deVreede, Akshay Vissweswaran,and John Long, “All Digital RF I / Q Modulator,”IEEE MTT, vol. 60 issue 11, pp. 3513-3526, 2012. [Lu ISSCC 2013]Chao Lu, et al. “A 24.7dBm All-Digital RF Transmitterfor Multimode Broadband Application in 40nm CMOS”, in Proc. of IEEE ISCCC ,pp. 332–333, Feb. 2013. [Alavi RFIC 2013]Morteza S. Alavi;George Voicu;Robert B. Staszewski;Leo C. N. de Vreede;John R. Long, A 2×13-bit all-digital I / Q RF-DAC in 65-nmCMOS, 2013 IEEE Radio Frequency Integrated Circuits Symposium(RFIC), 2013 [Alavi MTT 2014]M.S. Alavi, R.G. Staszewski, L.C.N. de Vreede, J. R.Long, A Wideband 2x 13-bit All-Digital I / Q RF-DAC, IEEE Transactions onMicrowave Theory and Techniques, Volume: 62, Issue: 4, Part: 1, 2014 , Page(s): 732 – 752. [Deng ISSCC 2016]Z. Deng et al., “A dual-band digital-WiFi 802.11a / b / g / n transmitter SoC with digital I / Q combining and diamond profile mappingfor compact die area and improved efficiency in 40nm CMOS,” in IEEE ISSCCDig. Tech. Papers, Feb. 2016, pp. 172–173. [Jin 2015]H. Jin et al., “Efficient digital quadrature transmitterbased on IQ cell sharing,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp.168–169. [Mehrpoo RFIC 2017]M. Mehrpoo, et al., “ A wideband linear direct digital RF modulator using harmonic rejection and I / Q-interleaving RF DACs ”,RFIC2017, pp. 188-191. [W. Gaber TMTT 2017] W. Gaber, et al., “A 21-dBm I / Q DigitalTransmitter Using Stacked Output Stage in 28-nm Bulk CMOS Technology,”, TMTT2017, pp. 4744- 4757. [Shen CICC 2020]Yiyu Shen, Rob Bootsman, Morteza S. Alavi, Leonardusde Vreede, A 0.5–3 GHz I / Q Interleaved Direct-Digital RF Modulator with up to320 MHz Modulation Bandwidth in 40 nm CMOS, 2020 IEEE Custom IntegratedCircuits Conference(CICC), 22-25 March 2020 [Shen, RFIC 2020]Yiyu Shen, Rob Bootsman, Morteza S. Alavi, Leo C.N.De Vreede, A 1-3 GHz I / Q Interleaved Direct-Digital RF Modulator As A Driverfor A Common-Gate PA in 40 nm CMOS, RFIC 2020 - 2020 IEEE Radio FrequencyIntegrated Circuits Symposium. [Gaber, TMTT 2017]W. M. Gaber, et al."A 21-dBm I / Q DigitalTransmitter Using Stacked Output Stage in 28-nm Bulk CMOS Technology,"TMTT,pp. 4744-4757, 2017. [Xiong, ISSCC 2019]L. Xiong, et al., “A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off EfficiencyEnhancement,” ISSCC, pp. 76-77, 2019. [Wang, 2010]Hua Wang, Toru Matsuura, Gregoire le Grand de Mercey, SanJose, Paul Cheng-Po Liang, Koji Takinami, Richard W. D. Booth, Patent No.: US8,385.469 B2Date of Patent: Feb. 26, 2013, Filed Jan. 20, 2010, AssigneePanasonic Corporation. https: / / patents.google.com / patent / US8385469 [Matsuura, 2011]Toru Matsuura, Wayne S. Lee, Tomoya Urushihara,Toshifumi Nakatani, Patent High Efficiency Transmitter, Pub. No.: US 2013 / 0058435 A1, Pub. Date: Mar. 7, 2013. Filed: Sep. 7, 2011. https: / / patents.google.com / patent / US20130058435A1 / en [Wentzloff et. al., 2019]United States Patent No.: US 10,200,232 B1,Feb. 5. 2019 [Bootsman, IMS 2020] RJ Bootsman, DPN Mul, Y. Shen, RM Heeres, F. van Rijs, MS Alavi, LCN de Vreede, “An 18.5 W Fully-DigitalTransmitter with 60.4 % Peak System Efficiency,” accepted for publication at the IMS 2020 conference, June 2020. Figure 7A A top view of an embodiment of a first-generation digitally controlled segmented RF power transmitter is shown. A particular example has two groups (one indicated by D) of gate segment 3a / power output stage elements 3, implemented, for example, using LDMOS semiconductor technology. The fact that it has two groups allows it to be used for both polarity operation (e.g., by operating the groups in parallel) and Cartesian or multiphase operation (one group for processing I, A data and one group for processing Q, B data). The configuration shown here uses only one control connection 34 for each drain finger 31, which drives the left and right gate fingers 32 as a single gate element. In this example, each group has fifteen thermometer bits and seven binary weighting bits, the latter... Figure 7B The diagram is shown in more detail below. The gate fingers 32 to the left and right of the drain finger 31 share the same driver connection 34 that is connected to the input terminal 9a. The plurality of drain fingers 31 are connected to an associated drain junction bar 33.

[0036] exist Figure 7A In the gate-segmented power output stage 2 shown, two different encoding techniques are used: binary encoding and thermometer encoding. Thermometer encoding is used for the most significant bit (MSB), while binary encoding is used for the least significant bit (LSB). More specifically, in Figure 7A In the embodiment, the total LDMOS gate width (W) has been reduced to 41.5 mm. gtot The thermometer is divided into two groups, each with 15 most significant bits (MSBs) of the thermometer code (one represented by A, and combinations of MSBs represented by 100) and 7 binary weighted least significant bits (LSBs) (one represented by B, and combinations of LSBs represented by 101). In this implementation, the least significant LSB (in the middle and represented by 102) has been implemented twice to create some redundancy.

[0037] The power ideally output by a set of gate segmented power output stages 2 can be used Wm×P1+ Wn×2 -n ×P1The sum is used to calculate, where Wm (m=1……15) represents the weighting factor of the m-th power output stage element 3 / gate element 3a corresponding to the thermometer code, Wn (n=1……7) represents the weighting factor of the n-th power output stage element 3 / gate element 3a corresponding to the binary code, and P1 is the power output by the power output stage element 3 / gate element 3a corresponding to the thermometer code. Factor 2 -n This describes how the gate finger width of the power output stage element 3 / gate element 3a corresponding to the binary encoding should be selected relative to the gate finger width of the power output stage element 3 / gate element 3a corresponding to the thermometer encoding. Furthermore, the weighting factors Wm and Wn can typically be 0 corresponding to the off mode or 1 corresponding to the on mode.

[0038] The fifteen power output stage elements 3 / gate elements 3a corresponding to the thermometer encoding allow for the generation of 16 distinct values, while the seven power output stage elements 3 / gate elements 3a corresponding to the binary encoding allow for the generation of 128 distinct values. Therefore, ideally, a total of 128 × 16 = 2048 distinct values ​​can be generated, corresponding to an 11-bit binary codeword.

[0039] For the binary weighted bits, the drain is divided into two isolated sections. The first section, indicated by L1-L4, indicates the portion of the drain pointer that cooperates with the gate pointer 32 to generate the signal. The other section, aligned with the first section, is grounded, for example, using via 103. The use of these shorted drain lines balances the input (gate) capacitance across all segments. Other balancing techniques, such as buffer scaling or the use of virtual capacitors, can also be considered.

[0040] For the nth LSB, the effective LDMOS gate width is twice the width of the thermometer MSB. -n Times. For example, in Figure 7B In this context, L4 defines the effective gate width corresponding to the gate finger encoded by the thermometer. Furthermore, L4 = 2 × L3 = 4 × L2 = 8 × L1.

[0041] In terms of linearity, thermometer encoding is preferred because binary encoding schemes account for the large number of variations between sequence numbers, resulting in considerable switching events in the RF current. For example, a change between binary codes 0111 and 1000 involves a 4-bit change. However, thermometer encoding requires a large number of power output stage components compared to binary encoding. Combining thermometer encoding for the MSB and binary encoding for the LSB can provide good results while still limiting the number of inputs required to drive the gate components. Hybrid approaches, such as using two levels of thermometer encoding from multiple levels, are also possible. These approaches are frequently used in DTX. However, at RF frequencies and higher power levels, using this method in practical implementations without any improvement results in the desired transfer function (e.g., ...). Figure 7A The polarity amplitude codeword to RF transmission (CWD-RF) output signal transmission performance of the group layout shown exhibits large irregularities and non-monotonic behavior.

[0042] Embodiments of the present invention can be applied to various digital transmitters (DTXs) ​​having a segmented power output stage 2, also referred to as an (interleaved) power switch group 121, which has multiple unit cells 122 / gate segments 3. The desired effect is that the digital transmitter (DTX) has an (interleaved) power switch group 121 in which the (interleaved) power switch group 121 is dynamically selected for its unit cells 121 / power output stage elements 3 (or segments 3), thereby providing monotonic CWD to AM and CWD to PM behavior.

[0043] like Figure 7A As illustrated in the example, the RF power switch groups 121 can have a considerably large electrical size, considering the wavelengths involved. Therefore, their direct implementation and the activation of their segment 3 will cause a redistribution effect of their RF output current, resulting in non-monotonic DNL or CWD-AM and CWD-PM behavior [Bootsman, IMS 2020]. Large current redistribution can occur as a result of other situations, such as if one group 121 is activated first and then the other group 121 is activated in a Cartesian or multiphase DTX implementation using two groups 121 in one RF cycle. Or when using interleaved switch groups 121-i or dynamic phase allocation of output stage unit cells 122 / segments, if these unit cells 122 / segments switch from one phasor to another in a larger group (e.g., non-monotonic activation of a thermometer bit), or when binary elements are present, by applying binary switches. Currently, these large current redistribution effects require very complex correction measures in practical DTX systems, at the cost of high complexity and / or power consumption. It also increases the noise floor of the output signal, far exceeding the theoretical quantization noise of the considered switch group 121. The nonlinearity not only leads to large (non-monotonic) steps, but also demonstrates the difficulty in compensating for nonlinear memory effects.

[0044] One further possible cause of the current redistribution effect is the physical location of activated segment 3, which will see different load impedances depending on the location. This is due to the distributed characteristics of switch group 121 (e.g., drain finger 31, large drain junction bar 33, or junction line drain connection transmission line), which begin to become electrically large for the target frequency range (RF). This will create different matching conditions for different segments 3, thus affecting the overall CWD-AM and CWD-PM transfer functions. Furthermore, once one segment 3 is disabled and another segment 3 is activated in a physically different location, the current must be "repositioned," thus having a dynamically adverse effect on the resulting CWD-AM and CWD-PM transfer functions. This is particularly important for non-polar systems that utilize multiple phases within the RF cycle to construct their output signals.

[0045] This invention relates to a method for applying an activation scheme to a digitally controlled segmented RF power transmitter 2 having multiple adjacent segments 3, each segment 3 having an associated activation region (determining the power output contribution of that segment 3, e.g., the gate width in a FET implementation of a thermometer-coded and / or binary-coded scheme), the segment 3 being controlled by a codeword (CWD), e.g., using bits to provide on / off control for each segment 3. The method includes controlling the segments 3 (e.g., on-off) by activating a specific segment 3 using an activation scheme (e.g., using bits) that depends on the codeword CWD to activate a specific segment within the segment 3. The activation scheme proceeds from the center segment of the multiple segments 3 toward the outer segments of the multiple segments 3 to increase the codeword CWD value. Note that embodiments of the method of this invention may be referenced above. Figure 2 , Figure 4 , Figure 5 or Figure 6 Implemented in any of the aforementioned Digital Dense Transmitter (DTX) types, as logic circuitry, software control, or a combination of both.

[0046] This embodiment of the invention minimizes current redistribution by maximizing the symmetry in the activation of segment 3 (as described below). In another embodiment, control of segment 3 is applied dynamically. An activation scheme is applied to dynamically track interpolated baseband data in order to maintain current redistribution within the boundary as much as possible in time. In a further embodiment, at an operating frequency f RF Operate the digitally controlled segmented RF power transmitter and apply control of segment 3 in RF cycle synchronization.

[0047] To illustrate the potential problems addressed by the embodiments of the present invention, current redistribution in multiphase / multiphase operation will now be discussed. Similar conclusions are maintained for Cartesian operation. Current redistribution can occur within a single RF cycle, caused by the continuous switching on and off of different phasors (A and B), for example, when using multiphase operation, in this example using a 25% RF duty cycle. Figure 8 The curves in the figure show an example output waveform, where A = 0.25 and B = 0.70. In one RF cycle, three “states” can be distinguished: B only, both phasors, and A only. The table below shows each successive state if a conventional (and currently implemented) two-group architecture is used for a digitally controlled segmented RF power transmitter, i.e., as shown in group A and group B. During the RF cycle, the current is redistributed from right to left.

[0048] In one embodiment of the invention, the codeword CWD includes two phasor codewords CWD-A and CWD-B, wherein adjacent segments 3 are assigned to different phasors A and B depending on the associated one of the two phasor codewords CWD-A and CWD-B. In this way, by alternating columns A and B, the “center of gravity” of the output current waveform is maintained in the central portion of the digitally controlled segmented RF power transmitter, resulting in the most monotonic CWD-PM transmission. In other words, each segment 3 can be dynamically assigned to a different phase, thus eliminating dedicated groups A and B (see also the staggered DTX implementation described above). The following diagram illustrates each successive state of alternating columns A and B in the left and right groups of the digitally controlled segmented RF power transmitter (see the table above), clearly demonstrating the effect of maintaining the center of gravity of the current in the middle, thereby providing reduced current redistribution and minimizing position-dependent load differences between units A and B.

[0049] In another set of embodiments, if the values ​​of the two phasor codewords CWD-A and CWD-B are not equal and enough segments 3 have been activated to reach the minimum value of the two phasor codewords, then further adjacent available segments 3 are assigned to the other associated phasor A and B of the two phasor codewords CWD-A and CWD-B. This further minimizes the current distribution (also on the y-axis in the example above) while still maintaining a symmetrical current distribution. Furthermore, the current density is more uniformly distributed across the drain fingers.

[0050] Note that in the examples above and discussed below, multiple adjacent segments 3 comprise an array of segments 3(i, j) having n rows and m columns. Therefore, a digitally controlled segmented RF power transmitter can be implemented as a rectangular region where each segment 3 is oriented in an array pattern.

[0051] It is now also possible to minimize the current redistribution along the x-axis (in the table above). After alternating columns A and B as explained with reference to the previous group of embodiments, all the remaining segments 3 can be filled using either A or B. Activation examples are shown in the table below. Light gray cells represent A (in this example, 50 active segments 3), while dark gray cells represent (in this example, 20 active segments 3). In this example, A > B, and therefore, after alternating A and B, the last portion is filled using A. This approach minimizes the current redistribution along the y-axis. Furthermore, when A is activated, the distance between different active unit cells is minimized.

[0052] Using this activation scheme embodiment, activation from the center to the sides provides the most uniform current distribution across the device width, while concentrating closed activation on maintaining a low-loss drain connection (note column C). <0> ...C <15> (In a specific order). Alternating columns A and B minimizes the current redistribution between the A and B phasors. After the alternation, all segments 3 are filled from top with the remaining phasors (in consecutive rows R). <0> …R <7> This results in a minimized current redistribution along the y-axis and the lowest possible loss on the drain finger. This keeps the “center of gravity” of the output waveform centered in the segmented output stage (switch group 121) at all times (and within one RF cycle), and the total area of ​​the active segment 3 is kept as compact as possible to minimize the distance between the two active segments 3. Note that after alternating A and B, when A>B or B>A, the last portion is filled with A or B accordingly, thus minimizing the total area of ​​the active segment 3.

[0053] In practical implementations, two or more bits are required for the correct activation of segment 3, and these bits are derived from the codeword CWD. Activation bits can be used to indicate whether segment 3 should be activated, and phasor bits can be used, including information on which phasor to use for activation, i.e., activation at phasor A or phasor B.

[0054] As a first step, the activation order that will result in symmetric activation of segment 3 is provided. In the table below, for segments with eight columns C... and eight rows of R <j>The array of segment 3 illustrates an exemplary activation sort: Row and column encoding and decoding are used for the activation bits of each segment 3. Note that in the table above, each column C... The connection order is suitable for achieving fill from the center to the sides, rather than from left to right or in a serpentine activation scheme [Alavi, MTT 2014]. Therefore, in the left group of a digitally controlled segmented RF power transmitter, the column order is C. <6> C <5> C <2> ;C <1> And in the right group, the column order is C. <0> C <3> C <4> C <7> .exist Figure 9 The diagram illustrates the associated decoder logic implemented in each segment 3. Figure 9 The decoder circuit 20 is shown, which includes an AND gate 21, an OR gate 22, and an optional flip-flop gate 23 that receives a clock signal 24 as an input.

[0055] In embodiments of the present invention, using Figure 4 The decoder logic shown uses a decoder to obtain the activation of a specific segment 3(i, j) in the i-th row and j-th column of the array. The decoder implementation logic formula is: (R AND C <j>OR line<i+1> .

[0056] For codeword CWD with a total value of 70 (A+B or I+Q) (CWD-A=50 and CWD-B=20), the following table then shows the activation of the corresponding segment 3, for an example of group 3 with two groups, each group of segment 3 having eight columns C and eight rows R: Then phasor selection is applied, and the activation scheme also includes applying phasor selector C during activation segment 3. A , R A C B R B The phasor selector C selects either the first phasor A or the second phasor B. A , R A C B R B The value of CWD-B is high "1" (or selected value) as long as the number of activated A or B segments 3 is less than or equal to the associated codeword CWD-A; and low "0" (or non-selected value) when the number of activated segments 3 is greater than the associated codeword CWD-A; The value of CWD-B is low "0" (or non-selected value). Note that the selected and non-selected values ​​can also be inverted logic values.

[0057] Initially, the total number of activation segments 3 is known (from codeword CWD, or the sum of codewords CWD-A and CWD-B), rather than activating segments at phasors A or B. As described above, the following diagram represents the expected final output: Note the even-numbered sequence C. <0> C <2> C <4> C <6> C <8> C <10> C <12> C <14> Starting with phasor A and the odd sequence C <1> C <3> C <5> C <7> C <9> C <11> C <13> C <15> It begins with vector B. Initially, these are represented as columns A and B, respectively, although both can switch to another phasor as mentioned above. A phasor selector bit is introduced to know when segment 3 should switch to another phasor. This phasor selector bit needs to indicate when the phasor of segment 3 needs to switch from the initial phasor (based on whether the segment is in column A or column B) to another phasor. In the example above, when 20 segments 3 are activated using the phasor of B, the phasor selector bit needs to switch in column B'.

[0058] Figure 14 A schematic diagram of a switch group 121 of a DTX according to an embodiment of the present invention is shown, having a drain junction strip 33 connecting a plurality of drain fingers 31 and a plurality of gate contact pads. As described above, the gate contact pads are assigned to corresponding rows R(1)...R(n) and columns C(0)...C(15), thereby allowing implementation of the method embodiments of the present invention.

[0059] In this set of embodiments, the value of codeword CWD-A is sent to column A, and the value of CWD-B is sent to column B for appropriate and desired activation, further explained using the following steps.

[0060] For the phase selector bits, column C is arranged (columns A and B are separated, indicated by the corresponding indices in the columns), as shown in the table below. The two values ​​of CWD-A and CWD-B are again sent to the corresponding columns using the row and column decoders. When enough segments of the relevant phasor are activated, the phasor selector now switches from 1 to 0. The column arrangement and numbering in the two top rows are shown below. The output of the phase selector is shown for CWD-A=50 and CWD-B=20. Note that in this example, only the B phasor selector affects the last activated segment. The A phasor selector only toggles the inactive segment 3 (the boundary of the active segment is indicated by a black line in the table).

[0061] The output of the phasor activator (note that all segments above the black line are activated by the activation bit): The final activation, after combining the activation bits and phasor selections, is then provided in the following table: In the first two lines R <0> and R <1> In this configuration, both phasor activators A and B are "1", and phasors A and B alternate for all columns C. Once all 20 segments 3 in column B are activated using phasors B, column B switches to phasor A. Note that the maximum value of one of the phasors (CWD-A; CWD-B) is equal to the total number of segments; however, the maximum value that can be used in phasor selection is half the number of segments. When CWD-A or CWD-B is greater than half the total number of segments, the phasor selection needs to include the selection value for all segments (i.e., all segments in the column initially assigned to the associated CWD (A or B) should remain active at the initial phase).

[0062] This method embodiment can be implemented, for example, using a single row and column decoder for activation, and two row and column decoders for phasor selection (each having half the number of columns). Each segment 3 is then connected to only one of the two row and column decoders depending on which column it is assigned to. In an example with a total of four rows and eight columns, this would result in the following steps: Figure 15 A schematic diagram of a DTX switch group according to another embodiment of the present invention is shown, allowing for the implementation of this embodiment. The structure is similar to... Figure 14 The structure shown, however, now assigns the gate pad to row R. A , R B and column C A <j> , C B <j>.

[0063] Note that these embodiments can also be applied to push-pull embodiments of the DTX variants as described above, such as... Figure 16 and 17 As shown in the schematic diagram. In an embodiment of switch group 121, this means that adjacent drain fingers 31 are alternately assigned as push-drain fingers (diagonally shaded) or pull-drain fingers (horizontally shaded). Push-drain fingers are interconnected in push-drain (connection) strips (not shown), while pull-drain fingers are interconnected in pull-drain (connection) strips (not shown). More generally, in another embodiment, a plurality of adjacent segments 3 comprise staggered drain fingers in a push-pull configuration of a digitally controlled segmented RF power transmitter. Note that in the case of a push-pull configuration, a single unit cell can be used to control both the push-gate and pull-gate segments, or two separate unit cells can be used to independently control the push and pull fingers.

[0064] In another set of embodiments, a second decoder is used to select either a first phasor A or a second phasor B for a specific segment 3(i, j) in the i-th row and j-th column of the array. This second decoder implements the logic formula: (R A AND C A <j>ORR A <i+1> And (R) B AND C B <j>OR R B <i+1> This is, for example, using... Figure 10 The decoder circuit shown in the exemplary embodiment is used for implementation. A second decoder circuit 40 is provided, which includes, as shown in the exemplary embodiment... Figure 9 The decoder circuit 20 shown in the embodiment, the second decoder circuit 40 now uses R <x>R<x+1> and C <y>As input. The second decoder circuit 40 also includes a second AND gate 41 (where R A and C A <j>As input), the second OR gate 42 (where the output of the second AND gate 41 and R are inputs ... A <i+1> As input, a second flip-flop gate 43 (using the same clock signal 24 as the first decoder circuit), a multiplexer 44 for selecting either the first phasor A or the second phasor B depending on the output of the second flip-flop gate 43, and an output AND gate 45 for combining the outputs from the first decoder circuit 20 and the second decoder circuit 40. The first decoder circuit 20 controls activation, and the second decoder circuit 40 controls phasor selection.

[0065] Figure 11 A schematic diagram of the array of second decoder circuits 40 for controlling the array of segments 3, arranged in corresponding columns A and B, is shown. For each segment 3, the indicated parameter R... <x> , C <y>Used for activation, and parameter R A , C A <j> ,R B , C B <j>Used for phasor selection.

[0066] In another set of embodiments, a second decoder is used to select either a first phasor A or a second phasor B for a specific segment 3(i,j) in the i-th row and j-th column of the array. This second decoder implements the logic formula: ((R phasor <x>AND C phasor’ <y phasor >) OR R phasor <x+1> OR PhSel, where PhSel indicates which of the associated codewords (CWD-A; CWD-B) is the highest-order bit to add. This is used, for example, as shown in... Figure 12 The decoder circuit shown in the exemplary embodiment is used for implementation. A third decoder circuit 50 is provided, which includes, as shown in the exemplary embodiment... Figure 9 The decoder circuit 20 shown in the embodiment, but the third decoder circuit 50 now uses R <x>R<x+1> and C <y>As input. The third decoder circuit 50 also includes a third AND gate 51 (where R phasor <x>With C phasor <y phasor >As input), the third OR gate 42 (where the output of the third AND gate 51 and R are inputs ... phasor <x+1> As input, a third flip-flop gate 53 (using the same clock signal 24 as the first decoder circuit 20) and an additional OR gate 56 receive the output of the third flip-flop gate 53 and the PhSel signal as input. A multiplexer 54 is provided to select either the first phasor A or the second phasor B depending on the output of the additional OR gate 56. An output AND gate 55 combines the outputs from the first decoder circuit 20 and the third decoder circuit 50. The first decoder circuit 20 controls activation, and the third decoder circuit 50 controls phasor selection.

[0067] Figure 13 A schematic diagram of the array of third decoder circuits 50 for controlling the array of segments 3, arranged in corresponding columns A and B, is shown. For each segment 3, the indicated parameter R... <x> , C <y>Used for activation, and parameter R phasor <x>C phasor <y phasor > and PhSel are used for phasor selection. Therefore, this embodiment uses only one row and column detector parameter for phasor selection, connected to columns A and B, as shown. Figure 13 As shown above, a separate bit (PHSEL) is added to determine whether column A or column B is sensitive to the phasor selector. The output of the phasor row and column detector combined with an additional OR gate 56 and the PhSEL bit result in the phasor selection bit. Based on this bit, column A will change to active at phasor B, or column B will change to active at phasor A.

[0068] Note that in this case, the column inputs of the third decoder circuit 50 are shared between columns A and adjacent column B. Whether the decoder changes the inputs of the multiplexer 54 depends on the PhSel bit. Therefore, with... Figure 10 Compared to the illustrated embodiment, an additional OR gate 56 is added. Its advantage is that only one row and column detector is needed to implement phasor selection. As a result, there is one control line that does not traverse all rows (and one additional line that traverses all columns). Note that the PhSel bit contains information about which codeword CWD-A or CWD-B has a larger value. In some embodiments, this information is readily available; in further exemplary embodiments, this comparison needs to be added to the logic circuitry. Also note that for each segment 3, the third decoder circuit 50 has an additional input compared to the second decoder circuit 40.

[0069] The above embodiments all relate to a digitally controlled segmented RF power transmitter with thermometer-type control of associated segment 3. That is, the active regions of multiple segments 3 in a predetermined group are equal. If the predetermined group includes all segments 3, single-level thermometer coding is available; however, multi-level thermometer coding can also be applied. In another set of embodiments, the active regions of a first subset of multiple adjacent segments 3 are equal and provide thermometer coding for output power contribution, and the active regions of adjacent segments of a second subset of multiple adjacent segments 3 provide additional binary coding for output power contribution. Again, note that the applied thermometer coding can be single-level or multi-level. It is located close to or at the center of the switching group where it is advantageous to achieve smaller thermometer bits (e.g., thermometer bits with smaller drain current contribution). Examples are described in the following paragraphs.

[0070] The binary encoding used for output power contribution can also have an effect on current (re)distribution. When the large-position switch is turned on or off, the (fully) binary implementation generates a large current redistribution, as shown in the table below.

[0071] Limiting the number of bits will reduce this problem; however, a few additional bits can significantly increase resolution with very few extra connections, which can be highly advantageous. In any case, other embodiments, as described below, can be envisioned that further reduce or mitigate potential current redistribution effects when using bits. Even with a small number of bits, non-monotonic behavior can occur in digitally controlled segmented RF power transmitters because the contribution to the output waveform depends on the location of the specific active segment. It is desirable to make binary control segment 3 as close as possible to the nearest thermometer-style active segment 3. Note that even if only one set of binary segments 3 is added for each phasor A, B, the position of the bits can be far from the switching thermometer bit, as shown in the table below: In another embodiment using binary bits, a first subset of multiple adjacent segments 3 includes an array of segments 3(i,j) having n rows and m columns, and also includes m sets of a second subset of multiple adjacent segments (3), which are provided as the top row adjacent to the n rows. This allows one set of the second subset to always be close to the most recently activated thermometer-patterned segment 3. In a further embodiment, for each phasor A, B, a set of the m sets activating the second subset corresponds to the highest column number activated in the first subset of multiple adjacent segments 3.

[0072] These embodiments can be explained using the following table: In this example, several binary control segments 3 that are close to the active thermometer-style segment 3 are added by adding multiple sets of binary control segments 3 in the additional top row (denoted as "binary"). By copying this set of binary bits at the top of each column, you can dynamically select which specific set of binary control segments 3 to use, for example, by selecting the set closest to the next thermometer-style segment 3 to be activated. In the example above, the active binary segment is shown in shaded lines, similar to the active thermometer-style segment.

[0073] In an optional group embodiment, a first subset of multiple adjacent segments 3 includes an array of segments 3(i,j) having n rows and m columns, and also includes n sets of multiple second subsets of adjacent segments 3, which are provided here as middle columns in the array. This allows for the addition of several binary control segments close to the thermometer-style active segment by adding multiple sets of binary control segments as additional columns in the middle of the array.

[0074] Furthermore, for each phasor A, B, a set is selected from the n sets of the second subset that corresponds to the highest row number activated in the first subset of multiple adjacent segments 3. This allows for the dynamic selection of which set of binary segments to use, choosing the set closest to the highest activated thermometer segment.

[0075] These embodiments can be explained using the following table, where the added column is marked "binary": In the foregoing embodiments, the use of combinations of thermometer bits complementary to binary bits has been discussed. Alternatively, two (or even more) levels of thermometer bits can be used, for example, the two levels described above. 7 The (128) thermometer bit switch group uses binary bits in its center column to increase its effective resolution. However, these binary bits can also be replaced by a second level of 2. n Instead, each thermometer bit is smaller than the thermometer bit used to implement the first level in terms of its contribution to the output current by a factor of 2. n Note that this concept is easier to implement while still significantly improving the resolution of the switch group. While various flavors are possible, here, symmetrically activating these smaller thermometer bits is advantageous in achieving a higher resolution with smooth CWD-to-RF transmission. Note that when considering the push-pull version, the internal drain finger (close to the axis of symmetry of the gate segmented switch group) is preferably used to implement the smaller thermometer bits. An example of such an embodiment of a push-pull switch group implementation using two levels of thermometer bits is given, where a smaller second-level thermometer centered on the axis of symmetry... Figure 18 In the middle, the drain finger is shared by the gate segments on both sides of the drain finger. The alternating push-pull drain finger organization now also allows the use of push-pull drivers / unit cells, except for the external drain finger which is not used (unconnected) in this example. Note that by using this even number of alternating push-pull fingers in combination with the push-pull (dual) drain bar at the top of the switch group (not shown), a fully symmetrical push-pull switch group can be achieved, which allows for truly symmetrical activation of its segments while providing high resolution due to the two-stage thermometer segment implementation. Thus, this embodiment will support very smooth and monotonous CWD to RF signal transmission, making the digital predistorter arrangement easier and more efficient to correct than conventional DTX switch group implementations with correlated activation.

[0076] In all the exemplary embodiments described above, the activation scheme activates multiple adjacent segments 3 row by row. In an implementation of an array-type digitally controlled segmented RF power transmitter, where the top row is close to the drain bar, this results in the activation of segment 3 starting from the row closest to the drain bar, thereby allowing a symmetrical current distribution with as little current distribution effect as possible.

[0077] In another set of embodiments, the activation scheme activates multiple adjacent segments 3 column by column. In many embodiments of a digitally controlled segmented RF power transmitter with drain junction bars 33 connected to all segments 3, drain fingers 31 extending from the drain junction bars 33 are used to reach all active areas of all segments 3. By using this set of embodiments, the total area with activated segments 3 can be kept as compact as possible to minimize the distance between two activated segments 3, further enhancing the advantage described above of keeping the total area with activated segments 3 as compact as possible to minimize the distance between two activated segments 3. For example, starting from the middle column / drain finger, all rows are filled first, then the next column is selected, working from the center drain finger to the outer drain fingers.

[0078] Similar to the example above, the drain junction bar 33 of the corresponding digitally controlled segmented RF power transmitter is still positioned at the top of the table, and the associated drain fingers 31 are oriented from top to bottom. In the above embodiment, the activation scheme first activates the segment 3 closest to the drain junction bar 33 (lower numbered rows), and further away from the drain junction bar 33 (higher numbered rows). In this set of embodiments, the activation scheme changes again by activating the drain fingers 31 from the middle to the sides (i.e., column-by-column). Therefore, this activation scheme is again designed to keep the center of the waveform in the middle of the associated digitally controlled segmented RF power transmitter's drain junction bar 33. All the other embodiments(s) described above can also be applied to this column-by-column activation scheme, which will be illustrated using several examples.

[0079] The table below illustrates a pattern implementing this embodiment for an example where CWD-A=50 and CWD-B=20. In one example, to balance the center of gravity of the waveform, alternating phasors are used to activate the two column / drain fingers as the number of active segments 3 is increased. In this example, the highest active segment 3 is in both columns C1. <4> and C2 <4> The top is divided into the right and left sides.

[0080] To activate each segment 3 in the array and determine the phase using the same method as before, the first step is to determine and apply the activation bits, and the second step is to determine and apply the phasor selection bits. The activation order is swapped for rows and columns compared to the previously described embodiment. However, the activation scheme is again designed to keep the center of the waveform in the middle of the drain bar of the associated digitally controlled segmented RF power transmitter.

[0081] To achieve this pattern, two row and column decoders (similar to...) are provided. Figure 10 and 12 The decoder circuit shown, however, has the entries for C and R interchanged (see, for example, see...). Figure 10 and 12 ), to provide a new (90-degree rotation activation scheme), one for the left side and one for the right side. Instructions are used for rows, and The indicator is used for columns. Both row and column decoders are half the size of the entire array surface. In this case, the input to both decoders needs to be half the original active bits (i.e., One row and column decoder input is rounded up, and the other is rounded down. Similarly, the phase selection bit that determines whether a cell is A or B needs to be processed in the same way as described for the activation bit. The process is then split into two row and column decoders, and the C and R entries are swapped.

[0082] Note that by activating a full column / drain finger, the combined power within that drain finger is maximized, while the other fingers are completely off. High current flow can (locally) reduce the drain voltage, which may result in a small bulge in the CWD-AM and CWD-PM characteristics.

[0083] The invention has been described above with reference to several exemplary embodiments shown in the accompanying drawings. Modifications and substitutions to some components or elements are possible and are included within the scope of protection defined by the appended claims.< / x> < / y> < / x> < / x> < / y> < / x> < / x> < / j> < / j> < / y> < / x> < / j> < / y> < / x> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A method for applying an activation scheme to a digital dense emitter (DTX) including a switch group (121), the switch group having a plurality of adjacent unit cells (122), the plurality of adjacent unit cells comprising an array of unit cells having n rows and m columns, each unit cell (122) having an associated field-effect transistor gate width, the unit cells (122) being controlled by a codeword CWD, the method comprising: The specific unit (122) is activated by using an activation scheme for activating a specific unit among the plurality of unit units (122) according to the codeword CWD, thereby controlling the plurality of unit units (122). The activation scheme starts from the central unit in the plurality of unit units (122) and proceeds toward the outer unit units in the plurality of unit units (122) to increase the codeword CWD value.

2. The method according to claim 1, wherein, The codeword CWD includes two phasor codewords (CWD-A; CWD-B), and wherein, according to the associated phasor codeword in the two phasor codewords (CWD-A; CWD-B), the adjacent unit cell (122) is assigned to different phasors (A, B).

3. The method according to claim 2, wherein, If the values ​​of the two phasor codewords (CWD-A; CWD-B) are not equal, and sufficient unit cells (122) have been activated to reach the minimum value of the two phasor codewords, then additional adjacent available unit cells (122) are assigned to the two phasor codewords (CWD-A; CWD-B). The phasor (A; B) associated with another phasor codeword in CWD-B.

4. The method according to claim 3, wherein, The array includes a unit cell (122) at position (i, j).

5. The method according to claim 4, wherein, The activation of a specific unit cell at position (i, j) in the i-th row and j-th column of the array is obtained using a decoder that implements the logic formula: (R AND C <j> OR R<i+1> ;< / j> Where R represents the row selector signal of the i-th row, C represents the column selector signal of the j-th column, and R<i+1> This indicates the row selector signal for the next row.

6. The method according to any one of claims 2-5, wherein, The activation scheme further includes applying a phasor selector (C) when activating the unit cell (122). A , R A C B , R B The phasor selector (C) selects either the first phasor (A) or the second phasor (B) as long as the number of activated unit cells (122) is less than the value of the associated codeword (CWD-A; CWD-B). A , R A C B , R B The phasor selector (C) has a selection value, and when the number of activated unit cells (122) is equal to or greater than the value of the associated codeword (CWD-A; CWD-B), the phasor selector (C) has a selection value. A , R A C B , R B It has non-selective values.

7. The method according to claim 5, wherein, The codeword (CWD) includes two phasor codewords (CWD-A; CWD-B), wherein, based on the associated phasor codewords in the two phasor codewords (CWD-A; CWD-B), the adjacent unit cell (122) is assigned to different phasors (A, B), and wherein the activation scheme further includes applying a phasor selector (C) when activating the unit cell (122). A , R A C B , R B The phasor selector (C) selects either the first phasor (A) or the second phasor (B) as long as the number of activated unit cells (122) is less than the value of the associated codeword (CWD-A; CWD-B). A , R A ;C B , R B The phasor selector (C) has a selection value, and when the number of activated unit cells (122) is equal to or greater than the value of the associated codeword (CWD-A; CWD-B), the phasor selector (C) has a selection value. A , R A C B , R B It has non-selectable values. The selection of a first phasor (A) or a second phasor (B) for a specific unit cell at position (i, j) in the i-th row and j-th column of the array is obtained using a second decoder, which implements the logic formula: (R A AND C A <j>) OR R A <i+1> and (R B AND C B <j>)OR R B <i+1>;< / j> < / j> Among them, R A C represents the row selector signal for the i-th row phasor A. A R represents the column selector signal for the j-th column phasor A. A <i+1> This represents the row selector signal for phasor A in the next row, while R... B C B R B <i+1> These represent the corresponding signals of phasor B.

8. The method according to claim 5, wherein, The codeword (CWD) includes two phasor codewords (CWD-A; CWD-B), wherein, based on the associated phasor codewords in the two phasor codewords (CWD-A; CWD-B), the adjacent unit cell (122) is assigned to different phasors (A, B), and wherein the activation scheme further includes applying a phasor selector (C) when activating the unit cell (122). A , R A C B , R B The phasor selector (C) selects either the first phasor (A) or the second phasor (B) as long as the number of activated unit cells (122) is less than the value of the associated codeword (CWD-A; CWD-B). A , R A ;C B , R B The phasor selector (C) has a selection value, and when the number of activated unit cells (122) is equal to or greater than the value of the associated codeword (CWD-A; CWD-B), the phasor selector (C) has a selection value. A , R A C B , R B It has non-selectable values. The selection of a first phasor (A) or a second phasor (B) for a specific unit cell (i, j) at position (i, j) in the i-th row and j-th column of the array is obtained using a second decoder, which implements the following logic formula: ((R phasor <x>AND C phasor <y phasor >)OR R phasor <x+1>)OR PhSel,< / x> Where Rphasor represents the row selector signal for the x-th row, Cphasor represents the column selector signal for the yphasor-th column, Rphasor<x+1> represents the row selector signal for the next row, and PhSel is an added bit indicating which of the two associated codewords (CWD-A; CWD-B) has the highest value.

9. The method according to any one of claims 1-5 or 7-8, wherein, The plurality of unit cells (122) includes at least one set of unit cells, wherein the gate width of the field-effect transistor in each set of unit cells is equal.

10. The method according to any one of claims 1-5 or 7-8, wherein, The field-effect transistor gate widths of the first subset of the plurality of adjacent unit cells (122) are equal and provide a thermometer code for the output power contribution, and the field-effect transistor gate widths of the adjacent unit cells in the second subset of the plurality of adjacent unit cells (122) provide a binary code for the output power contribution.

11. The method according to claim 10, wherein, The first subset of the plurality of adjacent unit cells (122) includes an array of unit cells (122) having n rows and m columns, and also includes m sets in the second subset of the plurality of adjacent unit cells (122), wherein each of the m sets is located in an additional row adjacent to and above the n rows of the first subset.

12. The method of claim 11, wherein, For each phasor (A, B), activate one set in the m sets of the second subset that corresponds to the highest column number activated in the first subset of the plurality of adjacent unit cells (122).

13. The method of claim 10, wherein, The first subset of the plurality of adjacent unit cells (122) includes an array of unit cells (122) at position (i, j) having n rows and m columns, and also includes n sets in the second subset of the plurality of adjacent unit cells (122), the n sets being provided as middle columns in the array.

14. The method of claim 13, wherein, For each phasor (A, B), activate one set in the n sets of the second subset that corresponds to the highest row number activated in the first subset of the plurality of adjacent unit cells (122).

15. The method according to any one of claims 4-5, 7-8, or 11-14, wherein, The activation scheme activates the multiple adjacent unit cells (122) row by row.

16. The method according to any one of claims 4-5, 7-8, or 11-14, wherein, The activation scheme activates the multiple adjacent unit cells (122) column by column.

17. The method according to any one of claims 1, 4-5, 7-8 or 11-14, wherein, The control of the unit cell (122) is updated based on the change in the codeword (CWD) value of the interpolated baseband data over time.

18. The method according to any one of claims 1, 4-5, 7-8 or 11-14, wherein, The digital dense transmitter operates at a frequency f RF The operating frequency f RF It has a period that defines an RF cycle, and wherein control of the plurality of unit cells (122) is applied synchronously with the plurality of said RF cycles, wherein synchronization means that the control is synchronized to occur at a predetermined time within each RF cycle.

19. The method according to any one of claims 1, 4-5, 7-8 or 11-14, wherein, The plurality of adjacent unit cells (122) include staggered drain pairs in the push-pull configuration of the digital dense transmitter.

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