A pilot-scale lithography defect detection method based on regression model

Abstract

This invention discloses a regression model-based method for detecting defective pixels in pilot-scale lithography. The invention uses a layout generator to create a virtual layout, identifies lithographic defects through lithography simulation, and slices the surface. The slice is then expanded, and its label is calculated again through lithography simulation. A frequency domain transformation is performed on the slice, and the coefficients in the frequency domain and the slice's label are used as training data to train a regression model. For the design department, this model can be used to determine the possible defects in the layout and their probabilities, applying different local constraints to different areas. For the manufacturing department, this model can be used for rapid defect detection, and the dataset can be updated using actual simulation results. This method can quickly establish a defect detection model in the development of pilot-scale processes, reducing the difficulty of design and manufacturing.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and in particular relates to a method for detecting defective pixels in lead process photolithography based on a regression model. Background Technology

[0002] As the feature size of integrated circuits continues to shrink, the manufacturing process of integrated circuits becomes increasingly difficult, requiring closer communication between design and manufacturing departments to establish more precise constraints. This has led to the emergence of Design for Manufacturing (DFM) and Design Technology Co-optimization (DTCO), which provide a two-way communication channel between the manufacturing and design departments.

[0003] Due to diffraction limitations in optical systems, many process defects can occur in integrated circuit manufacturing, resulting in photolithographic defects such as pinching and bridging, which can lead to device failure. Tightening design rules to avoid these defects would significantly increase design complexity. Efficient and accurate defect detection technology can accelerate layout development cycles and reduce process development costs.

[0004] Currently, commonly used defect detection methods mainly include model simulation and pattern matching. Model simulation can detect all defective pixels on the layout, but since full-layout OPC simulation is very time-consuming, this technique is usually used in combination with other defect detection techniques. Pattern matching-based defect detection technology is based on a defective pixel pattern library. As feature sizes shrink, the defective pixel pattern library becomes increasingly large, and defect detection time becomes increasingly long. Before a new process (i.e., a pilot process) is established, the defective pixel pattern library is incomplete, thus introducing a large number of defective pixels during the design phase. As the process matures, the defective pixel pattern library can be gradually improved, increasing the ratio of matching areas on the layout.

[0005] Therefore, improving the accuracy and flexibility of defect detection in pilot-scale photolithography has become an urgent problem to be solved. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing photolithography defect detection technologies by providing a regression model-based method for detecting defective pixels in a pilot process. This method enables the establishment of a defect detection model before the process is established, eliminating the need for a lengthy accumulation process of defective pixel patterns and improving design flexibility while ensuring the accuracy of defect detection.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] In a first aspect, the present invention provides a pilot process photolithography defect detection model, the training method of which includes the following steps:

[0009] (1) Construct a classic graphics library and standard cell library for pilot process layout; wherein the pilot process refers to an immature process;

[0010] (2) Using a layout generator, elements from classic graphics libraries and standard cell libraries are used to design and combine virtual layouts for pilot processes.

[0011] (3) Based on the required pilot process information, the virtual layout is retargeted and then optical proximity correction (OPC) is performed to obtain the pattern on the photomask; the pattern on the photomask is simulated using a photolithography simulation model to mark the location of photolithography defects; the virtual layout is sliced ​​according to the location of the photolithography defects obtained from the simulation to obtain the first slice.

[0012] The pilot process information includes etching deviation and photolithography selectivity deviation;

[0013] The optical proximity effect correction employs at least one of the following methods: inserting a scattering bar, adding auxiliary graphics, adjusting the line length of the line graphic, and adjusting the line width of the line graphic.

[0014] (4) Use the layout generator to expand the first slice in multiple ways to obtain multiple second slices, wherein the second slices include the first slice area and the expanded area; use the layout generator to expand the multiple second slices in multiple ways to obtain multiple third slices, wherein the third slices include the second slice area and the expanded area; perform target reset and optical proximity effect correction on the third slices.

[0015] The optical proximity effect correction process for the third slice includes the following:

[0016] (1) Within the first slice area, adjust the line width and line length of the line graphics, and add auxiliary graphics and scattering bars;

[0017] (2) Add auxiliary graphics and scattering bars to the non-first slice portion within the second slice area;

[0018] (3) No adjustments are made to the portion of the third slice area that is not the second slice area;

[0019] Photolithography simulation was performed on the processed third slice, and the proportion of photolithographic defects in the third slice was used as the probability that the first slice would become a defective slice, i.e., the label of the first slice.

[0020] (5) Downsample the first slice with the label and then perform frequency domain transformation to enhance its frequency domain information; use the low-frequency coefficients in the frequency domain of the first slice and its label to train the regression model.

[0021] (6) Use the trained regression model to detect defective pixels in the pilot process photolithography.

[0022] Furthermore, the frequency domain transformation in step (5) is either Discrete Cosine Transform (DCT) or Fast Fourier Transform (FFT).

[0023] Furthermore, the regression model in step (5) is a linear regression model, a random forest regression model, or a gradient boosting regression model.

[0024] Secondly, the present invention provides a pilot process photolithography defect detection device, comprising:

[0025] The data acquisition module is responsible for acquiring map samples;

[0026] The data preprocessing module is responsible for resetting the target of the layout sample, then performing optical proximity effect correction to obtain the pattern on the photomask; using a sliding window to cut slices on the photomask pattern, downsampling and frequency domain transformation of the slices to obtain the low-frequency coefficients in the frequency domain of the slices;

[0027] The defect detection module is responsible for inputting the low-frequency coefficients in the frequency domain of the slice into the trained regression model to predict lithographic defects.

[0028] Thirdly, the present invention provides a method for designing and verifying a pilot process layout, comprising the following steps:

[0029] (1) The design department conducts physical verification of the pilot process layout of the design to obtain the actual layout;

[0030] (2) The actual map is re-targeted and optical proximity correction is performed to obtain the pattern on the photomask;

[0031] (3) Use a sliding window to cut slices on the photomask pattern, downsample and transform the slices in the frequency domain to obtain the low-frequency coefficients in the frequency domain of the slices; use a regression model to predict the probability that each slice on the layout will become a bad pixel.

[0032] (4) If the prediction results meet the manufacturing requirements, the actual layout will be delivered to the manufacturing department for chip manufacturing; otherwise, the actual layout will be modified and physical verification will be carried out again.

[0033] Furthermore, in step (4), the manufacturing requirements can impose different levels of constraints on critical and redundant designs. The probability of lithographic defects in different regions is accumulated, imposing strict constraints on critical designs and setting a lower local threshold; while imposing lenient constraints on redundant designs and setting a higher local threshold.

[0034] Fourthly, the present invention provides a method for correcting a pilot process layout, comprising the following steps:

[0035] (1) The manufacturing department resets the target and corrects for optical proximity effect on the actual layout to obtain the pattern on the photomask;

[0036] (2) Use a sliding window to cut slices on the photomask pattern, downsample and frequency domain transform the slices to obtain the low-frequency coefficients in the frequency domain of the slices; use a regression model to predict the probability that each slice on the layout will become a bad pixel.

[0037] (3) Sort the probability of becoming a bad pixel in descending order, and take the first n slices for individual optical proximity effect correction;

[0038] (4) Perform photolithography simulation on the corrected layout to find the actual photolithography hotspots;

[0039] (5) Based on the actual simulation results, determine whether the current layout meets the publishing requirements. If it meets the publishing requirements, deliver the photomask to the photomask factory for production. Otherwise, further modify the hot spots and return to step (4).

[0040] Furthermore, the actual lithography hotspots in step (4) can be used to slice the layout according to their positions, update the dataset of lithography defects, and improve the dataset of lithography defects.

[0041] Fifthly, the present invention provides a computer device including a memory, a modifier, and a computer program stored in the memory and executable on the modifier, wherein the modifier performs the steps of the above-described method when executing the computer program.

[0042] In a sixth aspect, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a modifier, implements the steps of the above-described method.

[0043] In traditional defect detection, detectors classify slices into two categories: defective and non-defective. However, whether a slice is defective depends not only on the slice itself but also on its surrounding environment. For example, if the probability of a first slice being defective is calculated to be 0.7, a traditional defect detector would classify it as defective, prohibiting the designer from using it in the layout. Compared to existing technologies, the advantages of this invention are: the method can flexibly treat slices according to actual conditions. Using the first slice can save design area and reduce process deviations. Under the premise of ensuring manufacturability, the designer can include the first slice in redundant design areas. In addition, the regression model used in this invention can improve the prediction accuracy and the model's generalization ability. For manufacturers, optical proximity correction requires iterative rounds until the layout's manufacturability meets requirements. The most time-consuming step in the optical proximity correction process is photolithography simulation. By using the regression model trained by this invention to detect and process defective pixels separately, the number of photolithography simulations can be reduced, shortening the mask production cycle. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a pilot-scale lithography defect detection method based on a regression model, including the data set creation process, the model training method, and the usage process of the model by the design and manufacturing departments.

[0045] Figure 2 (a) is a schematic diagram of the virtual design generated by the virtual layout generator; (b) is a schematic diagram of the mask pattern after target reset and optical proximity effect correction; (c) is a schematic diagram of the photoresist pattern on the wafer and the identified photolithographic defects after photolithography simulation; (d) is a schematic diagram of the virtual design sliced ​​according to the location of the photolithographic defects in the simulation results.

[0046] Figure 3 Expanding the results of the slices;

[0047] Figure 4 (a) is the first slice with tagged photolithographic defects; (b) is the density map obtained after downsampling; (c) is a schematic diagram of the frequency domain information after frequency domain transformation.

[0048] Figure 5 For optical proximity effect correction procedures;

[0049] Figure 6 This describes the process for slice expansion and label calculation. Detailed Implementation

[0050] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0051] When a semiconductor manufacturer wants to further reduce feature size—for example, if a manufacturer already has mass-produced products using a 55nm process technology node and wants to establish a new 28nm process—then the 28nm process is considered a pilot process for that manufacturer. In the process of establishing a new process, to ensure the manufacturability of the final design layout and to guarantee manufacturing yield, a globally optimal design rule should be applied to both the design and the process. Designers should consider manufacturing processes before starting the design phase, and the manufacturer should also adopt a layout similar to the actual design during the pilot process development.

[0052] like Figure 1 As shown. Before process establishment, the design department provides classic graphics libraries and standard cell libraries, while the manufacturing department generates a virtual layout using a layout generator and identifies defective pixels through simulation. Slices are created centered on the defective pixels, their environments are changed, and the probability of each slice becoming a defective pixel is calculated. After downsampling and frequency domain transformation, this data is used to train a regression model. During process establishment, simulation results can be fully utilized to update the dataset.

[0053] The regression model-based defect detection method for pilot-scale lithography uses a layout generator to create a virtual design. This allows for the establishment of a defect detection model even when a real design is lacking at the pilot-scale node, and the dataset can be continuously improved during subsequent R&D, providing dynamic design rules. Secondly, this detection method calculates the probability of a defect becoming a defect by changing the environment surrounding the defect slice, which is more accurate than the traditional binary judgment of whether it is a defect. Furthermore, the design department can apply different local constraints to different areas, such as SRAM cells, standard cell libraries, and analog circuits, improving design flexibility and reducing design difficulty. Meanwhile, the manufacturing department can identify and process hotspots independently without simulation, reducing the number of optical proximity effect correction cycles and accelerating mask production.

[0054] This invention provides a method for detecting defective pixels in lead-edge photolithography based on a regression model, comprising:

[0055] (1) Construct a classic graphics library and standard cell library for pilot process layout; wherein the pilot process refers to an immature process;

[0056] (2) Using a layout generator, the Monte Carlo method is used to design and combine elements from the classic graphics library and standard cell library to form a virtual layout for the pilot process.

[0057] The rules generated by the map generator can be random combinations or user-defined rules, such as... Figure 2 As shown in (a), a virtual layout of the polysilicon gate layer was generated using a classic graphic combination.

[0058] (3) Based on the Etch Bias Table and the Selected Bias Algorithm Table, the virtual layout is retargeted, and then scattering bars are inserted using a rule-based method. Figure 5 Optical Proximity Correction (OPC) is used to obtain the pattern on the photomask; a photolithography simulation model is used to simulate the pattern on the photomask and mark the location of photolithographic defects; based on the location of the photolithographic defects obtained from the simulation, the virtual pattern is sliced ​​to obtain the first slice;

[0059] The reset target is determined based on process information from photolithography and etching processes. Optical proximity correction can be based on the optical proximity correction recipe from the previous process node, such as... Figure 2 As shown in (b), the virtual map becomes a mask pattern after the target is reset and the optical proximity effect is corrected.

[0060] The photolithography simulation model includes an optical model and a photoresist model, such as Figure 2 As shown in (c), after the photomask pattern is simulated by photolithography, the location of photolithographic defects can be marked, and the photolithographic defects are marked with a darker color in the figure.

[0061] Defect slices are sub-patterns extracted from a virtual layout based on the locations of defective pixels obtained from photolithography simulation, such as... Figure 2 As shown in (d), the slice size is 1μm*1μm.

[0062] (4) Figure 6 The first slice is expanded using a layout generator to obtain multiple second slices of 3μm*3μm in size, where the second slice includes the first slice region and the expanded region; the multiple second slices are expanded using a layout generator to obtain multiple third slices of 9μm*9μm in size, where the third slice includes the second slice region and the expanded region; the third slice is then subjected to target reset and optical proximity effect correction.

[0063] As shown in Figure (3), the center points of different slices overlap. A is the first slice, which is derived from the slice of the virtual layout. The line width of the line graphic can be adjusted, the line of the line graphic can be extended, and graphics can be added. B is the second slice, which is formed by randomly generating graphics around the first slice. Auxiliary graphics or scattering bars can be added. C is the third slice, which is formed by randomly generating graphics around the second slice and participates in the photolithography simulation.

[0064] The optical proximity effect correction process for the third slice includes the following:

[0065] (1) Within the first slice area, adjust the line width and line length of the line graphics, and add auxiliary graphics and scattering bars;

[0066] (2) Add auxiliary graphics and scattering bars to the non-first slice portion within the second slice area;

[0067] (3) No adjustments are made to the portion of the third slice area that is not the second slice area;

[0068] Photolithography simulation was performed on the processed third slice, and the proportion of photolithographic defects in the third slice was used as the probability that the first slice would become a defective slice, i.e., the label of the first slice.

[0069] The aforementioned diversification is similar to generating a virtual map, which involves adding auxiliary graphics to the original slices;

[0070] (5) Downsample the first slice with labels, and enrich the dataset by data augmentation. Then perform frequency domain transformation to enhance its frequency domain information. Use the low-frequency coefficients and labels of the first slice in the frequency domain to train the regression model.

[0071] The downsampling method is density-based sampling. The image size after downsampling is 128 pixels * 128 pixels, as shown in Figure (4) (b). The image after downsampling becomes a 128-pixel * 128-pixel grayscale image. The dataset can be augmented by operations such as rotation and mirroring on the density map.

[0072] The frequency domain transformation method is the discrete cosine transform, such as... Figure 4 As shown in (c), the frequency domain information of the image is effectively enhanced after frequency domain transformation, which is more consistent with the imaging process of the optical system.

[0073] The regression model is a random forest regression model. The dataset is divided into training and validation sets in a 4:1 ratio. Grid search is used to determine parameters such as the number of subtrees, the maximum growth depth of the tree, the minimum number of samples per leaf, the minimum number of samples per branch node, and the maximum number of selected features.

[0074] (6) Use the trained regression model to detect defective pixels in the pilot process photolithography.

[0075] Example 2: A method for designing and verifying a pilot process layout, comprising the following steps:

[0076] (1) The design department conducts physical verification of the pilot process layout of the design to obtain the actual layout;

[0077] (2) The actual map is re-targeted and optical proximity correction is performed to obtain the pattern on the photomask;

[0078] (3) Use a sliding window to cut slices on the photomask pattern. The window size is 1μm*1μm and the step size is 0.1μm*0.1μm. Perform downsampling and frequency domain transformation on the slices to obtain the low-frequency coefficients in the frequency domain of the slices. Use a regression model to predict the probability that each slice on the layout will become a bad pixel.

[0079] (4) If the prediction results meet the manufacturing requirements, the actual layout will be delivered to the manufacturing department for chip manufacturing; otherwise, the actual layout will be modified and physical verification will be carried out again.

[0080] Furthermore, in step (4), the manufacturing requirements can impose different levels of constraints on critical and redundant designs. The probability of lithographic defects in different regions is accumulated, imposing strict constraints on critical designs and setting a lower local threshold; while imposing lenient constraints on redundant designs and setting a higher local threshold.

[0081] Example 3: A method for correcting a pilot process layout, comprising the following steps:

[0082] (1) The manufacturing department resets the target and corrects for optical proximity effect on the actual layout to obtain the pattern on the photomask;

[0083] (2) Use a sliding window to cut slices on the photomask pattern. The window size is 1μm*1μm and the step size is 0.1μm*0.1μm. Perform downsampling and frequency domain transformation on the slices to obtain the low-frequency coefficients in the frequency domain of the slices. Use a regression model to predict the probability that each slice on the layout will become a bad pixel.

[0084] (3) Sort the probability of becoming a bad point in descending order, and take the first n slices for individual optical proximity correction, such as inverse lithography (ILT).

[0085] (4) Perform photolithography simulation on the corrected layout to find the actual photolithography hotspots;

[0086] (5) Based on the actual simulation results, determine whether the current layout meets the publishing requirements. If it meets the publishing requirements, deliver the photomask to the photomask factory for production. Otherwise, further modify the hot spots and return to step (4).

[0087] Furthermore, the actual lithography hotspots in step (4) can be used to slice the layout according to their positions, update the dataset of lithography defects, and improve the dataset of lithography defects.

[0088] The above description is merely a preferred embodiment of one or more embodiments of this specification and is not intended to limit the scope of one or more embodiments of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A method for detecting defective pixels in lead-ahead lithography based on a regression model, characterized in that... The method is specifically as follows: Classic graphics libraries and standard cell libraries for constructing pilot process layouts; Using a layout generator, virtual layouts for pilot processes are designed and combined using elements from classic graphics libraries and standard cell libraries. Based on the required pilot process information, the virtual layout is reset to target, and then optical proximity correction is performed to obtain the pattern on the photomask; The pattern on the photomask was simulated using a photolithography simulation model, and the location of the photolithography defects was marked. Based on the location of the lithographic defects obtained from the simulation, the virtual layout is sliced ​​to obtain the first slice; The first slice is expanded in multiple ways using a layout generator to obtain various second slices; The second slice includes the first slice area and the extended area; The layout generator is used to diversify and expand various second slices to obtain various third slices; The third slice includes the second slice region and the extended region; The third slice is subjected to target resetting and optical proximity effect correction; Photolithographic simulation was performed on the third slice after resetting the target and correcting the optical proximity effect. The proportion of photolithographic defects in the third slice was used as the probability that the first slice would become a defect, i.e., the label of the first slice. The first slice with the current label is downsampled and frequency domain transformed to obtain the low-frequency coefficients in the frequency domain of the first slice; the low-frequency coefficients in the frequency domain of the first slice and its label are used to train the regression model. A trained regression model is used to detect defective pixels in the lead process photolithography.

2. The method according to claim 1, characterized in that, The optical proximity effect correction process for the third slice includes the following: Adjust the line width and length of the lines in the first slice area, and add auxiliary graphics and scattering bars; Add auxiliary graphics and scattering bars to the non-first slice portion within the second slice area.

3. The method according to claim 1, characterized in that, The pilot process information includes etching deviation and photolithography selectivity deviation; The optical proximity effect correction employs at least one of the following methods: inserting scattering bars, adding auxiliary graphics, adjusting the line length of the line graphics, and adjusting the line width of the line graphics.

4. The method according to claim 1, characterized in that, The frequency domain transformation is either a discrete cosine transform or a fast Fourier transform.

5. The method according to claim 1, characterized in that, The regression model is a linear regression model, a random forest regression model, or a gradient boosting regression model.

6. A pilot-process photolithography defect detection device for implementing the method of any one of claims 1-5, characterized in that, include: The data acquisition module is responsible for acquiring map samples; The data preprocessing module is responsible for resetting the target of the layout sample, then performing optical proximity effect correction to obtain the pattern on the photomask; using a sliding window to cut slices on the photomask pattern, downsampling and frequency domain transformation of the slices to obtain the low-frequency coefficients in the frequency domain of the slices; The defect detection module is responsible for inputting the low-frequency coefficients in the frequency domain of the slice into the trained regression model to predict lithographic defects.

7. A method for designing and verifying a pilot process layout, characterized in that... Includes the following steps: (1) The design department conducts physical verification of the pilot process layout of the design to obtain the actual layout; (2) The actual map is re-targeted and optical proximity correction is performed to obtain the pattern on the photomask; (3) Use a sliding window to cut slices on the photomask pattern, downsample and frequency domain transform the slices to obtain the low-frequency coefficients in the frequency domain of the slices; use the regression model trained by any one of claims 1-5 to make predictions to obtain the probability that each slice on the layout becomes a bad point; (4) If the prediction results meet the manufacturing requirements, the actual layout is delivered to the manufacturing department for chip manufacturing; otherwise, the actual layout is modified and the process returns to step (1).

8. A method for modifying a pilot process layout, characterized in that... Includes the following steps: (1) The manufacturing department resets the target and corrects for optical proximity effect on the actual layout to obtain the pattern on the photomask; (2) Use a sliding window to cut slices on the photomask pattern, perform downsampling and frequency domain transformation on the slices to obtain the low-frequency coefficients in the frequency domain of the slices; use the regression model trained by any one of claims 1-5 to make predictions to obtain the probability that each slice on the layout becomes a bad pixel. (3) Sort the probability of becoming a bad pixel in descending order, and take the first n slices for individual optical proximity effect correction; (4) Perform photolithography simulation on the corrected layout to find the actual photolithography hotspots; (5) Based on the actual simulation results, determine whether the current layout meets the publishing requirements. If it meets the publishing requirements, deliver the photomask to the photomask factory for production. Otherwise, further modify the hot spots and return to step (4).

9. A computer device comprising a memory, a modifier, and a computer program stored in the memory and executable on the modifier, characterized in that, When the corrector executes the computer program, it implements the steps of the method as claimed in any one of claims 1-5.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the corrector, it implements the steps of the method as described in any one of claims 1-5.

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