Adaptive dynamic digital circuit-based multiply-accumulate system and design method thereof

Abstract

The application provides a multiply-accumulate system based on an adaptive dynamic digital circuit and a design method thereof, and comprises the following steps: designing a multiply-accumulate controller; designing input signals of an adder; organically connecting the multiply-accumulate controller with the adder and a multiplier to obtain a multiply-accumulate system; and designing an indication signal, which is used for indicating a final output value of the multiply-accumulate system. The multiply-accumulate system is obtained by organically connecting the multiplier, the adder and the multiply-accumulate controller, so that the design of the multiply-accumulate system is simplified and the structure of the multiply-accumulate system is simple. Through the design of the input signals and the indication signal, the multiply-accumulate system can be compatible with the scenes of continuous data and non-continuous data without changing the structure of the multiply-accumulate system, and the compatibility of the multiply-accumulate system is improved. In addition, the multiply-accumulate system provided by the application has simple judgment logic and can effectively save hardware resources, and solves the problems of large hardware resource occupation and complex design process of the existing multiply-accumulate method.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a multiply-accumulate system based on adaptive dynamic digital circuits and its design method. Background Technology

[0002] With the development of artificial intelligence technology, convolutional neural network technology has also developed rapidly. Convolutional neural networks can process large amounts of data through convolution calculations to obtain corresponding results. Currently, the multiplication-accumulation method is commonly used to implement large-scale convolution calculations. For example, application number 202211193323.8, entitled "In-memory computing chip capable of realizing multi-mode multiplication-accumulation calculations," achieves multi-mode multiplication-accumulation of the overall data by designing a computing unit array and using configurable inter-column connectors and intra-column connectors. Another example is application number 202310216702.2, entitled "A 7T in-memory computing circuit and multiplication-accumulation operation circuit based on low-voltage technology," which effectively solves the problems of power consumption and computing performance of the functional circuit through careful design of the basic components of the circuit implementation.

[0003] However, most existing multiply-accumulate methods use fixed-point and floating-point numbers as the main data calculation modes. For high-precision scientific computing, the data bit width is several times that of ordinary numerical operations. Addition operations have a large delay due to carry propagation, while floating-point operations have a high degree of complexity due to their data structure.

[0004] When designing floating-point multiply-accumulate functionality, most current designs tend to decompose and reassemble the floating-point multiplier and accumulator to form an independent, complete multiply-accumulate module. While this approach reduces the normalization and decomposition / reconstruction processes for the multiplier and adder, it comes at the cost of using significant hardware resources to build an independent floating-point multiply-accumulate function, resulting in high hardware resource consumption and a complex design process. Summary of the Invention

[0005] The purpose of this invention is to provide a multiply-accumulate system based on adaptive dynamic digital circuits and its design method, so as to at least solve the problems of large hardware resource consumption and complex design process of existing multiply-accumulate methods.

[0006] To address the aforementioned technical problems, this invention provides a design method for a multiply-accumulate system based on adaptive dynamic digital circuits, comprising:

[0007] Design a multiply-accumulate controller;

[0008] Design the input signal for the adder;

[0009] The multiply-accumulate controller is organically connected to the adder and the multiplier to obtain a multiply-accumulate system;

[0010] The design includes an indicator signal used to indicate the final output value of the multiply-accumulate system.

[0011] Optionally, in the design method of the multiply-accumulate system based on adaptive dynamic digital circuits, the method for designing the multiply-accumulate controller includes:

[0012] Design the operating status register of the multiply-accumulate controller;

[0013] Design the counter and temporary data register of the multiply-accumulate controller;

[0014] The working status register, the counter, and the temporary data register are organically connected to obtain a multiply-accumulate controller.

[0015] Optionally, in the design method of the multiply-accumulate system based on adaptive dynamic digital circuits, the method for designing the operating state register of the multiply-accumulate controller includes:

[0016] Initialize the working status register so that the state of the working status register is 0;

[0017] The function of the configuration status register is to indicate the current multiplication-accumulation status;

[0018] Configure the status of the working status register: 0 indicates that the external data for this multiplication-accumulation operation is being input after multiplication by the multiplier; 1 indicates that the multiplication input of the external data for this multiplication-accumulation operation has been completed, and the multiplication of the last data has ended, and the multiplier has completed sending the last multiplication result to the multiplication-accumulation controller.

[0019] Optionally, in the design method of the multiply-accumulate system based on adaptive dynamic digital circuits, the method for designing the operating state register of the multiply-accumulate controller further includes:

[0020] Configure the working logic of the working status register: When the state of the working status register is 0, the multiplier outputs the multiplication result to the multiply-accumulate controller; when the state of the working status register is 1, the multiplier stops outputting the multiplication result to the multiply-accumulate controller.

[0021] Optionally, in the design method of the multiply-accumulate system based on adaptive dynamic digital circuits, the method for designing the counter and temporary data register of the multiply-accumulate controller includes:

[0022] Initialize the counter and the temporary data register so that the state of the counter is 0 and the state of the temporary data register is empty;

[0023] The function of the configuration counter is to count the number of valid buffers in the multi-cycle adder;

[0024] The function of configuring the temporary data register is as follows: The temporary data register is used to buffer the output result of the current adder cycle when the state of the working status register is 1, and to perform addition operation on the output result of the next adder cycle.

[0025] Optionally, in the design method of the multiply-accumulate system based on adaptive dynamic digital circuits, the method for designing the counter and temporary data register of the multiply-accumulate controller further includes:

[0026] Configure the working logic of the counter and temporary data register:

[0027] When the status register is 0, the counter increments by 1 when the multiplier has an output but the adder has no output; otherwise, the counter remains unchanged.

[0028] When the status register is 1, the counter remains unchanged when the adder has no output; when the adder has an output and the temporary data register is empty, the data in the adder is stored in the temporary data register and the temporary data register is set to full; when the adder has an output and the temporary data register is full, the temporary data register is set to empty and the counter is decremented by 1.

[0029] Optionally, in the design method of the multiply-accumulate system based on adaptive dynamic digital circuits, the method for designing the input signal of the adder includes:

[0030] Set the first adder signal, the second adder signal, and the enable adder signal;

[0031] Configure the working logic of the adder:

[0032] When the status register is 0, if the adder has an output, the adder output value is sent to the first adder signal; otherwise, 0 is sent to the first adder signal. If the multiplier has an output, the multiplier output value is sent to the second adder signal; otherwise, 0 is sent to the second adder signal. If either the adder or the multiplier has an output, 1 is sent to the enable adder signal; otherwise, 0 is sent to the enable adder signal.

[0033] When the status register is 1, if the adder has an output and the temporary data register is full, the adder output value is sent to the first adder signal, the temporary data register value is sent to the second adder signal, and 1 is sent to the enable adder signal; otherwise, the first adder signal, the second adder signal, and the enable adder signal are all sent to 0.

[0034] Optionally, in the design method of the multiply-accumulate system based on adaptive dynamic digital circuits, the method for providing the design indication signal includes:

[0035] The function of the configuration indicator signal is to indicate the final output value of the multiply-accumulate system;

[0036] Configure the status of the indicator signal: a value of 1 indicates the end of a complete multiplication-accumulation process;

[0037] Configure the logic for generating the indicator signal:

[0038] When the status of the working status register is 0, the indicator signal is set to 0;

[0039] When the status register is 1, if the counter is 1 when the adder has an output, the indicator signal will be set to 1; otherwise, the indicator signal will be set to 0.

[0040] When the indicator signal is 1, the working status register, counter, first adder signal, second adder signal and enable adder signal are all set to 0, and the temporary data register is set to empty.

[0041] To address the aforementioned technical problems, this invention also provides a multiply-accumulate system based on adaptive dynamic digital circuits, designed using the design method for a multiply-accumulate system based on adaptive dynamic digital circuits as described in any of the preceding claims. The multiply-accumulate system includes a multiplier, an adder, and a multiply-accumulate controller. The multiplier and the adder are communicatively connected to the multiply-accumulate controller. The multiply-accumulate controller controls the multiplier and the adder, performs multiply-accumulate operations using the output values ​​of the multiplier and the adder, and outputs the final output value.

[0042] Optionally, in the multiply-accumulate system based on adaptive dynamic digital circuits, the multiply-accumulate controller includes a working state register, a counter, and a temporary data register; the working state register is used to indicate the current multiply-accumulate state; the counter is used to count the number of valid buffers in the multi-cycle adder; the temporary data register is used to buffer the output result of the current adder when the working state register is 1, and to perform addition operations on the output result of the next adder.

[0043] This invention provides a multiply-accumulate system and its design method based on adaptive dynamic digital circuits, comprising: designing a multiply-accumulate controller; designing the input signal of the adder; organically connecting the multiply-accumulate controller with the adder and multiplier to obtain the multiply-accumulate system; and designing an indicator signal for indicating the final output value of the multiply-accumulate system. By organically connecting the multiplier, adder, and multiply-accumulate controller to obtain the multiply-accumulate system, the design of the multiply-accumulate system is greatly simplified, resulting in a simple structure. Through the design of the input and indicator signals, the system can be compatible with both continuous and non-continuous data scenarios without altering its structure, improving its compatibility. Furthermore, the multiply-accumulate system provided by this invention has simple judgment logic and can still operate independently without changing the functionality of the existing multiplier and adder, maintaining the modular design performance of the overall circuit and the reusability of logic resources. This effectively saves hardware resources and solves the problems of large hardware resource consumption and complex design processes in existing multiply-accumulate methods. Attached Figure Description

[0044] Figure 1 A flowchart illustrating the design method of the multiply-accumulate system based on adaptive dynamic digital circuits provided in this embodiment;

[0045] Figure 2 This is a block diagram of the conventional design structure of the multiply-accumulate system provided in this embodiment;

[0046] Figure 3 This is a module design diagram of the multiply-accumulate system provided in this embodiment;

[0047] Figure 4 This is a flowchart of the design algorithm for the multiply-accumulate system provided in this embodiment;

[0048] Figure 5 This is a schematic diagram of the structure of the multiply-accumulate system based on adaptive dynamic digital circuits provided in this embodiment. Detailed Implementation

[0049] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more comprehensive overview of the multiply-accumulate system based on adaptive dynamic digital circuits and its design method proposed in this invention. It should be noted that the drawings are all in a very simplified form and use non-precise scales, intended only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and thus may use different scales.

[0050] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0051] This embodiment provides a design method for a multiply-accumulate system based on adaptive dynamic digital circuits, such as... Figure 1 As shown, the design method of the multiply-accumulate system based on adaptive dynamic digital circuits includes:

[0052] S1, Design a multiply-accumulate controller;

[0053] S2, Design the input signal of the adder;

[0054] S3, the multiply-accumulate controller is organically connected to the adder and the multiplier to obtain the multiply-accumulate system;

[0055] S4, Design indicator signal, the indicator signal is used to indicate the final output value of the multiply-accumulate system.

[0056] The design method for a multiply-accumulate system based on adaptive dynamic digital circuits provided in this embodiment simplifies the design of the system by organically connecting the multiplier, adder, and multiply-accumulate controller, resulting in a simple system structure. Through the design of the input and indication signals, the system can be compatible with both continuous and non-continuous data scenarios without altering its structure, thus improving its compatibility. Furthermore, the multiply-accumulate system provided by this invention has simple judgment logic and can operate independently without changing the functionality of the existing multipliers and adders, maintaining the modular design performance and reusability of logic resources. This effectively saves hardware resources and solves the problems of large hardware resource consumption and complex design processes in existing multiply-accumulate methods.

[0057] It should be noted that, in practical applications, the order of the steps in the design method of the multiply-accumulate system based on adaptive dynamic digital circuits provided in this embodiment can be adjusted according to actual needs. For example, the input signal of the adder can be designed first, followed by the design of the multiply-accumulate controller. Furthermore, in some specific embodiments, additional steps can be added between the steps to optimize or enhance the corresponding functions. Any adjustments or additions to the design method steps without departing from the spirit of this invention should fall within the scope of protection of this application.

[0058] Since multipliers and adders are mature and universal modules, they generally do not require separate design. Therefore, in this embodiment, existing multiplier and adder modules can be directly used, and only the differences between them and the prior art will be described in detail.

[0059] See Figure 2 It can be concluded that the input and output of a multiplier are independent. Therefore, as a sequential logic circuit, the delay cycle number (the delay period from multiplication input to output) of the multiplier does not need to be considered during the multiplication-accumulation process. Only the synchronous output of the input `last` signal and the corresponding multiplication result to the multiplication-accumulation controller is required. In contrast, the input and output of an adder are directly related during the multiplication-accumulation process. For ordinary addition calculations, which can generally be completed within one cycle, the output of the multiplier can be directly connected to the input of the adder. However, for high-precision scientific calculations of fixed-point numbers or large-scale data calculations, the data is often composed of multiple bytes, and the calculation process is also decomposed into multiple cycles. Floating-point calculations, due to the multiple steps involved in factoring, exponent alignment, calculation, and exponent restoration, require even more cycles. In both cases, a multiplication-accumulation controller must be designed to control the input and output of the adder, gradually eliminating the scattering of the multiplication-accumulation sum caused by the multiple delay cycles of the adder, and finally merging the multiplication-accumulation sum into a single value as the final output value.

[0060] Based on this, this application designs a multiply-accumulate controller with a counter and a numerical register. The counter counts the internal components and quantities of the adder, and simultaneously controls the input of the adder; the numerical register buffers the data. By properly connecting this multiply-accumulate controller to external multipliers and adders, the multiply-accumulate function can be realized.

[0061] The following is for reference Figure 3 and Figure 4 The design method of the multiply-accumulate system provided in this embodiment will be described in detail.

[0062] Specifically, in this embodiment, step S1, the method for designing a multiply-accumulate controller, includes:

[0063] S11, Design the working state register of the multiply-accumulate controller. Specifically, in this embodiment, the working state register is named last_state, and the method for designing the working state register of the multiply-accumulate controller includes:

[0064] Initialize the working state register last_state so that the state of the working state register last_state is 0;

[0065] Configure the function of the working status register last_state: The working status register last_state is used to indicate the current multiplication and accumulation status;

[0066] Configure the state of the working status register last_state: 0 indicates that the multiplier is receiving external data to perform multiplication and outputting the multiplication result to the multiplier-accumulator controller; 1 indicates that the input of external data for the current multiplication-accumulation operation has been completed and the multiplication of the last data has ended, and the multiplier has completed sending the last multiplication result to the multiplier-accumulator controller.

[0067] In addition, the working logic of the working status register last_state is configured as follows: when the state of the working status register last_state is 0, the multiplier outputs the multiplication result to the multiply-accumulate controller; when the last signal reaches the multiply-accumulate controller after passing through the multiplier, the state of the working status register last_state is 1, and the multiplier stops outputting the multiplication result to the multiply-accumulate controller.

[0068] S12, Design the counter and temporary data register of the multiply-accumulate controller. Specifically, in this embodiment, the counter is named adder_stage, and the temporary data register is named temp_result. The method for designing the counter and temporary data register of the multiply-accumulate controller includes:

[0069] Initialize the counter adder_stage and the temporary data register temp_result so that the state of the counter adder_stage is 0 and the state of the temporary data register temp_result is empty;

[0070] Configure the function of counter adder_stage: The counter adder_stage is used to count the number of valid caches in the multi-cycle adder;

[0071] Configure the function of the temporary data register temp_result: The temporary data register temp_result is used to buffer the output result of the current adder cycle when the state of the working state register last_state is 1, and to perform addition operation on the output result of the next adder cycle;

[0072] And, the working logic for configuring the counter adder_stage and the temporary data register temp_result:

[0073] When the state of the working status register last_state is 0, the counter adder_stage increments by 1 when the multiplier has an output (multi_result_valid is 1) and the adder (adder_result_valid is 0) has no output; otherwise, the counter adder_stage remains unchanged.

[0074] When the state register last_state is 1, the counter adder_stage remains unchanged when the adder has no output; when the adder has an output and the temporary data register temp_result is empty, the data adder_result in the adder is stored in the temporary data register temp_result, and the state of the temporary data register temp_result is set to full; when the adder has an output and the state of the temporary data register temp_result is full, the temporary data register temp_result is set to empty, and the counter adder_stage is decremented by 1.

[0075] S13, the working status register, the counter, and the temporary data register are organically connected to obtain a multiply-accumulate controller. The connection method of the working status register, the counter, and the temporary data register can be referred to by those skilled in the art. Figure 3 and Figure 4 Based on what is known from existing technology, it will not be elaborated here.

[0076] Furthermore, in this embodiment, step S2, the method for designing the input signal of the adder, includes:

[0077] Set the first adder signal adder_a, the second adder signal adder_b, and the adder enable signal adder_en;

[0078] Configure the working logic of the adder:

[0079] When the state of the working status register last_state is 0, if the adder has an output, the adder output value is sent to the first adder signal adder_a; otherwise, 0 is sent to the first adder signal adder_a. If the multiplier has an output, the multiplier output value is sent to the second adder signal adder_b; otherwise, 0 is sent to the second adder signal adder_b. If either the adder or the multiplier has an output, 1 is sent to the enable adder signal adder_en; otherwise, 0 is sent to the enable adder signal adder_en.

[0080] When the state of the working status register last_state is 1, if the adder has an output and the temporary data register is full, the adder output value is sent to the first adder signal adder_a, the temporary data register value is sent to the second adder signal adder_b, and 1 is sent to the enable adder signal adder_en; otherwise, the first adder signal adder_a, the second adder signal adder_b, and the enable adder signal adder_en are all sent to 0.

[0081] By controlling the input signal logic of the adder in different states of the working state register last_state, it can be ensured that the period of the adder matches the period of the multiplier. In this way, the efficiency and accuracy of operation can be guaranteed without increasing the complexity of the multiply-accumulate system through signal logic control.

[0082] Step S3 involves organically connecting the multiply-accumulate controller with the adder and multiplier to obtain a multiply-accumulate system. The specific implementation is well-known to those skilled in the art; for details, please refer to [link to relevant documentation]. Figure 3 and Figure 4 Having learned the specific construction method of the multiplication-accumulation system, this application will not elaborate on it.

[0083] Furthermore, in this embodiment, step S4, the method for designing the indication signal, includes:

[0084] Define the indicator signal as mac_valid;

[0085] The function of the configuration indicator signal mac_valid is: the indicator signal mac_valid is used to indicate the final output value of the multiply-accumulate system;

[0086] Configure the status of the mac_valid indicator signal: a value of 1 indicates the end of a complete multiply-accumulate process;

[0087] Configure the logic for generating the mac_valid indicator signal:

[0088] When the state of the last_state register is 0, the indicator signal mac_valid is set to 0;

[0089] When the state of the working status register last_state is 1, if the counter adder_stage is 1 when the adder has an output, the indicator signal mac_valid will be set to 1; under other conditions, the indicator signal mac_valid will be set to 0.

[0090] When the indicator signal mac_valid is 1, it indicates the end of a complete multiply-accumulate process. At this time, the working status register last_state, the counter adder_stage, the first adder signal adder_a, the second adder signal adder_b, and the enable adder signal adder_en are all set to 0, and the temporary data register temp_result is set to empty, in preparation for the next multiply-accumulate process.

[0091] This embodiment also provides a multiply-accumulate system based on adaptive dynamic digital circuits, designed using the above-described design method for a multiply-accumulate system based on adaptive dynamic digital circuits. Figure 5 As shown, the multiply-accumulate system includes a multiplier, an adder, and a multiply-accumulate controller; the multiplier and the adder are respectively communicatively connected to the multiply-accumulate controller; the multiply-accumulate controller is used to control the multiplier and the adder, and to perform multiply-accumulate operations using the output values ​​of the multiplier and the adder and output the final output value.

[0092] The multiply-accumulate system based on adaptive dynamic digital circuits provided in this embodiment simplifies the design of the system by organically connecting the multiplier, adder, and multiply-accumulate controller, resulting in a simple system structure. Through the design of the input and indication signals, the system can be compatible with both continuous and non-continuous data scenarios without altering its structure, thus improving its compatibility. Furthermore, the multiply-accumulate system provided by this invention has simple judgment logic and can operate independently without changing the functionality of the existing multipliers and adders, maintaining the modular design performance and reusability of logic resources. This effectively saves hardware resources and solves the problems of large hardware resource consumption and complex design processes in existing multiply-accumulate methods.

[0093] Preferably, in this embodiment, the multiply-accumulate controller includes a working status register, a counter, and a temporary data register; the working status register is used to indicate the current multiply-accumulate state; the counter is used to count the number of valid buffers in the multi-cycle adder; the temporary data register is used to buffer the output result of the current adder cycle when the working status register is 1, and to perform addition operations on the output result of the next adder cycle.

[0094] It should be noted that the technical solution of this application focuses on the logic model of digital circuits. In the specific implementation process, it can be implemented on FPGA, hardware programmable SOC, or ASIC chip design. The implementation of the logic model by choosing different chips is known to those skilled in the art and will not be elaborated here.

[0095] The following specific example illustrates the effectiveness of the multiply-accumulate system and its design method based on adaptive dynamic digital circuits provided in this application.

[0096] In this embodiment, an external 16-bit fixed-point multiplier and a fixed-point adder are selected, with the adder having a delay of 7.

[0097] Design a multiply-accumulate controller. The input interface includes the multiplier's output, valid signal, and synchronization last signal; the adder's output and valid signal; the output interface includes addend 1 and addend 2, and the addition enable signal. Internally, design a working state register last_state, a counter adder_stage with its empty / full flag adder_stage_flag, and a temporary data register temp_result.

[0098] The table below shows the performance of this design when multiplying and accumulating 10 sets of data (0-9) continuously with add_dly (adder delay) of 7. The output multiply-accumulate result is valid in the 27th cycle after mul_last (where zero represents zero data, X represents invalid data, and ab represents the sum of the multiplication result of the a-th set and the multiplication result of the b-th set).

[0099]

[0100]

[0101] As shown in the table above, when 10 sets of continuous data are multiplied and accumulated, with an adder delay of 7 cycles, the total accumulated sum is output in the 36th cycle, along with a mac_valid indicator signal. This multiply-accumulate process is consistent with the control process of the static configuration method, demonstrating its functional correctness. Furthermore, this method uses 40% less logic resources compared to the static configuration multiply-accumulate with a 7-cycle delay, effectively reducing hardware resource consumption. From a design perspective, this multiply-accumulate controller does not require knowledge of the adder's delay cycle or pre-calculation of parameters, significantly simplifying the design process.

[0102] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0103] This embodiment provides a multiply-accumulate system and its design method based on adaptive dynamic digital circuits, including: designing a multiply-accumulate controller; designing the input signal of the adder; organically connecting the multiply-accumulate controller with the adder and multiplier to obtain the multiply-accumulate system; and designing an indicator signal to indicate the final output value of the multiply-accumulate system. By organically connecting the multiplier, adder, and multiply-accumulate controller to obtain the multiply-accumulate system, the design of the multiply-accumulate system is greatly simplified, resulting in a simple structure. Through the design of the input and indicator signals, the system can be compatible with both continuous and non-continuous data scenarios without changing its structure, improving its compatibility. Furthermore, the multiply-accumulate system provided by this invention has simple judgment logic and can still operate independently without changing the functionality of the existing multiplier and adder, maintaining the modular design performance of the overall circuit and the reusability of logic resources. This effectively saves hardware resources and solves the problems of large hardware resource consumption and complex design processes in existing multiply-accumulate methods.

[0104] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A design method for a multiply-accumulate system based on adaptive dynamic digital circuits, characterized in that, include: The design of a multiply-accumulate controller includes: designing a working status register for the multiply-accumulate controller; designing a counter and a temporary data register for the multiply-accumulate controller; and organically connecting the working status register, the counter, and the temporary data register to obtain the multiply-accumulate controller. Design the input signal for the adder; The multiply-accumulate controller is organically connected to the adder and the multiplier to obtain a multiply-accumulate system; The design includes an indicator signal used to indicate the final output value of the multiply-accumulate system.

2. The design method of the multiply-accumulate system based on adaptive dynamic digital circuits according to claim 1, characterized in that, The method for designing the operating status register of the multiply-accumulate controller includes: Initialize the working status register so that the state of the working status register is 0; The function of the configuration status register is to indicate the current multiplication-accumulation status; Configure the status of the working status register: 0 indicates that the external data for this multiplication-accumulation operation is being input after multiplication by the multiplier; 1 indicates that the multiplication input of the external data for this multiplication-accumulation operation has been completed, and the multiplication of the last data has ended, and the multiplier has completed sending the last multiplication result to the multiplication-accumulation controller.

3. The design method for a multiply-accumulate system based on adaptive dynamic digital circuits according to claim 2, characterized in that, The method for designing the operating status register of the multiply-accumulate controller further includes: Configure the working logic of the working status register: When the state of the working status register is 0, the multiplier outputs the multiplication result to the multiply-accumulate controller; when the state of the working status register is 1, the multiplier stops outputting the multiplication result to the multiply-accumulate controller.

4. The design method of the multiply-accumulate system based on adaptive dynamic digital circuits according to claim 1, characterized in that, The method for designing the counter and temporary data register of the multiply-accumulate controller includes: Initialize the counter and the temporary data register so that the state of the counter is 0 and the state of the temporary data register is empty; The function of the configuration counter is to count the number of valid buffers in the multi-cycle adder; The function of configuring the temporary data register is as follows: The temporary data register is used to buffer the output result of the current adder cycle when the state of the working status register is 1, and to perform addition operation on the output result of the next adder cycle.

5. The design method of the multiply-accumulate system based on adaptive dynamic digital circuits according to claim 4, characterized in that, The method for designing the counter and temporary data register of the multiply-accumulate controller also includes: Configure the working logic of the counter and temporary data register: When the status register is 0, the counter increments by 1 when the multiplier has an output but the adder has no output; otherwise, the counter remains unchanged. When the status register is 1, the counter remains unchanged when the adder has no output; when the adder has an output and the temporary data register is empty, the data in the adder is stored in the temporary data register and the temporary data register is set to full; when the adder has an output and the temporary data register is full, the temporary data register is set to empty and the counter is decremented by 1.

6. The design method of the multiply-accumulate system based on adaptive dynamic digital circuits according to claim 1, characterized in that, The method for designing the input signal of the adder includes: Set the first adder signal, the second adder signal, and the enable adder signal; Configure the working logic of the adder: When the status register is 0, if the adder has an output, the adder output value is sent to the first adder signal; otherwise, 0 is sent to the first adder signal. If the multiplier has an output, the multiplier output value is sent to the second adder signal; otherwise, 0 is sent to the second adder signal. If either the adder or the multiplier has an output, 1 is sent to the enable adder signal; otherwise, 0 is sent to the enable adder signal. When the status register is 1, if the adder has an output and the temporary data register is full, the adder output value is sent to the first adder signal, the temporary data register value is sent to the second adder signal, and 1 is sent to the enable adder signal; otherwise, the first adder signal, the second adder signal, and the enable adder signal are all sent to 0.

7. The design method of the multiply-accumulate system based on adaptive dynamic digital circuits according to claim 6, characterized in that, The method for providing the design indication signal includes: The function of the configuration indicator signal is to indicate the final output value of the multiply-accumulate system; Configure the status of the indicator signal: a value of 1 indicates the end of a complete multiplication-accumulation process; Configure the logic for generating the indicator signal: When the status of the working status register is 0, the indicator signal is set to 0; When the status register is 1, if the counter is 1 when the adder has an output, the indicator signal will be set to 1; otherwise, the indicator signal will be set to 0. When the indicator signal is 1, the working status register, counter, first adder signal, second adder signal and enable adder signal are all set to 0, and the temporary data register is set to empty.

8. A multiply-accumulate system based on adaptive dynamic digital circuits, designed using the design method for a multiply-accumulate system based on adaptive dynamic digital circuits as described in any one of claims 1 to 7, characterized in that, The multiply-accumulate system includes a multiplier, an adder, and a multiply-accumulate controller. The multiplier and the adder are communicatively connected to the multiply-accumulate controller. The multiply-accumulate controller controls the multiplier and the adder, performs multiply-accumulate operations using the output values ​​of the multiplier and the adder, and outputs the final output value. The multiply-accumulate controller includes a working status register, a counter, and a temporary data register. The working status register indicates the current state of the multiply-accumulate operation. The counter counts the number of valid buffers in the multi-cycle adder. The temporary data register buffers the output of the current adder when the working status register is 1, and performs addition operations on the output of the next adder.

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