FPGA-based high-speed compact pipeline matrix transposition implementation method

Abstract

The application provides a high-speed compact pipeline matrix transposition implementation method based on FPGA, which transposes an M-parallel pipeline input N-row by N-column matrix X in FPGA to obtain an M-parallel pipeline output matrix X T (M≤N), and the method comprises the following steps: shaping the M-parallel data into K-parallel data (K is a minimum value not less than M and divisible by N, N=αK, and α is a positive integer); opening K RAM spaces, and the depth of each space is L=N / K; writing the input K-parallel data into the K RAM spaces according to the configured address after sorting the K-parallel data, simultaneously reading out the data in the address and outputting the data after sorting, and finally shaping the K-parallel data into M-parallel data to obtain the transposed M-parallel output N-row by N-column matrix X 2 T The application satisfies the cache-free transposition under the condition of multi-parallel data pipeline input, and the occupied space is only 50% of the traditional space.​

Description

Technical Field

[0001] This invention relates to the field of communications, and more particularly to a high-speed, compact, pipelined matrix transpose method based on FPGA. Background Technology

[0002] In on-chip systems such as ultra-high-speed communication, high-performance computing, and real-time image processing, a large number of matrix transpose operations are required. Since communication data is transmitted and processed in a pipelined manner and cannot be cached, matrix transpose needs to be processed in real time.

[0003] Existing matrix transposition methods typically utilize registers, DDR, or RAM. Register-based transposition involves storing input data in a register, and retrieving the value from the transpose register after all data for the matrix has been stored. This approach is only suitable for small-scale matrix transpositions; for larger matrices, it strains FPGA resources and increases routing complexity. DDR-based transpositions require external DDR memory and an additional DDR controller, resulting in complex control, low read / write efficiency, and significant processing latency, making them unsuitable for real-time systems. RAM-based transposition involves storing input data in RAM at configured addresses, and retrieving the value from the RAM at the configured transpose address after all data for the matrix has been stored. This approach offers low latency and requires fewer registers, but under parallel pipelined input conditions, a RAM-based transposition module requires at least twice the size of the matrix in RAM. In baseband communication algorithm implementations, multiple transposition modules are needed, further straining the FPGA's internal RAM resources. Therefore, existing matrix transposition methods need improvement to achieve transposition with fewer resources. Summary of the Invention

[0004] To address the problems in the prior art, this invention proposes a high-speed, compact, pipelined matrix transpose implementation method based on FPGA.

[0005] The purpose of this invention is to fully utilize the feature of dual-port RAM in FPGA that can be read and written simultaneously, thereby simplifying the complexity of RAM resources required for matrix transpose.

[0006] A high-speed, compact, pipelined matrix transpose method based on FPGA includes the following steps:

[0007] For an N-row × N-column matrix X input to an M-channel parallel pipeline, where M ≤ N, first, input the M-channel parallel data... 1t’ 、in 2t’ …、in Mt’ Reshape into K-way parallel data x 1t x 2t …、x KtK is the minimum value that is not less than M and can divide N, and N = αK, where α is a positive integer, and t' is the number of clocks for M parallel data inputs, where t' = 1, 2, ...;

[0008] After shaping, the number of clock cycles input to an N x N matrix is ​​T = N. 2 / K; counts the number of input clock cycles, with a count value of t, where t = 1, 2, ..., T. The physical meaning of t is that the current input is the Kth data point under the t-th clock cycle of the current matrix.

[0009] Based on t, K-way parallel data is input in an ordered manner to obtain new K-way parallel data x'. 1t 、x' 2t …、x' Kt ;

[0010] Write control writes new K parallel data streams into K RAM spaces of depth L, where L = N. 2 / K; Simultaneously, read from K RAM spaces via read control; output K parallel data streams y' 1t y' 2t …、y' Kt ;

[0011] Based on t, the K-way parallel data is sorted and output to obtain the sorted K-way parallel data y. 1t y 2t …、y Kt ;

[0012] The K-way parallel data after sorting is then shaped to finally obtain the transposed M-way parallel data out. 1t” out 2t” …、out Mt” t” represents the number of clock cycles for M-channel parallel data output, where t” = 1, 2, ...

[0013] As a preferred embodiment of the present invention, the step of reordering the K-channel parallel data according to t specifically refers to: for the K-channel parallel data x input at the current time of the t-th clock cycle... 1t x 2t …、x kt …、x Kt For k = 1, 2, ..., K, first determine if the data before reordering input at this clock is in the j-th column of the matrix. This indicates rounding down; then determine the number of positions to move, 'a', where 'a = mod(j-1, K)', where 'mod()' represents the modulo operation; then... kt Move from a to x rt The position, r = mod(k + a - 1, K) + 1, yields the new K-way parallel data x'.1t 、x' 2t …、x' kt …、x' Kt .

[0014] In a preferred embodiment of the present invention, the K RAM spaces of depth L are K-way parallel storage spaces, respectively denoted as RAM1, RAM2, ... RAM K It can be written simultaneously in one clock cycle. The depth of the K-way parallel memory space is L, with ADDR1 being the low address and ADDR... L It is a high address.

[0015] As a preferred embodiment of the present invention, the step of writing new K-channel parallel data into K RAM spaces of depth L via write control specifically involves: determining whether the K-channel parallel data input at the current time of the t-th clock cycle belongs to an odd matrix or an even matrix; counting the number of matrices, incrementing the count by 1 each time an N-row × N-column matrix X is input; when the current number of matrices is odd, it is called an odd matrix; when the current number of matrices is even, it is called an even matrix.

[0016] If the K-channel parallel data input at the current time (clock t) belongs to an odd matrix, when k < a, it is written into RAM. k ADDR cN+bK+K+(k-a) When k≥a, write it into RAM. k ADDR cN+bK+(k-a) Simultaneously with writing, data at the same address is read out.

[0017] If the K-channel parallel data input at the current clock moment (the t-th clock cycle) belongs to an even matrix, write it into RAM. k ADDR cK+bN+a+1 Simultaneously with writing, data at the same address is read out.

[0018] Where b is the remainder of (t-1) / α, and c is the quotient of (j-1) / K.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0020] The high-speed, compact, pipelined matrix transpose implementation method based on FPGA proposed in this invention can meet the requirements of real-time transpose without buffering under multi-channel parallel data pipeline input conditions. For an N row × N column matrix, compared with the 2*N*N RAM space required by the traditional transpose method, this invention only requires N*N RAM space, occupying only 50% of the space of the traditional method. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the transposition method of the present invention;

[0022] Figure 2 There are K RAM spaces of depth L;

[0023] Figure 3 This is a diagram illustrating the input sequence.

[0024] Figure 4 This is a diagram illustrating read / write control.

[0025] Figure 5 This is a schematic diagram of the ordered output;

[0026] Figure 6 This is a diagram illustrating the transpose when the first matrix is ​​input.

[0027] Figure 7 This is a diagram illustrating the transpose when the second matrix is ​​input in the implementation column;

[0028] Figure 8 This is a diagram illustrating the transpose when the third matrix is ​​input. Detailed Implementation

[0029] The present invention will be further described and illustrated below with reference to specific embodiments. The embodiments described are merely examples of the content of this disclosure and do not limit the scope of the invention. The technical features of each embodiment in the present invention can be combined accordingly, provided that there is no mutual conflict.

[0030] The purpose of this invention is to fully utilize the feature of dual-port RAM in FPGA that can be read and written simultaneously, thereby simplifying the complexity of RAM resources required for matrix transpose.

[0031] The implementation method of this invention is as follows Figure 1 As shown. For an N-row × N-column matrix X (M≤N) with M-channel parallel pipeline input, the input is column-wise. That is, the M-channel data input in the first clock cycle is rows 1 to M of column 1 of X, the M-channel data input in the second clock cycle is rows M+1 to N of column 1 of X, rows 1 to 2M-N of column 2 of X, and so on. First, the M-channel parallel data is input... 1t '、in 2t '...、in Mt 'Shaping into K-way parallel data x' 1t x 2t …、x Kt (K is the minimum value that is not less than M and divisible by N, denoted as N = αK, where α is a positive integer), t' is the number of clocks for M parallel data inputs, t' = 1, 2, ... . The number of clocks for an N row × N column matrix input after shaping is T = N 2 / K; Counts the number of input clock cycles, with a count value of t, t = 1, 2, ..., T. The physical meaning of t is: it indicates that the current input is the Kth data point under the t-th clock cycle of the current matrix; it is then ordered according to t to become a new K-way parallel data x'.1t 、x' 2t …、x' Kt The data is written to K RAM spaces of depth L, where L = N, via write control. 2 / K; simultaneously reads K RAM spaces via read control; outputs K parallel data streams y' 1t y' 2t …、y' Kt Based on t, the data is sorted and output to obtain the sorted K-way parallel data y. 1t y 2t …、y Kt After shaping, the transposed M-way parallel data output is finally obtained. 1t” out 2t” …、out Mt” t” represents the number of clock cycles for M-channel parallel data output, where t” = 1, 2, ...

[0032] K RAM spaces of depth L, such as Figure 2 As shown: RAM1, RAM2...RAM K This is a K-way parallel memory space, capable of being written to simultaneously within a single clock cycle. Its depth is L, with ADDR1 being the low address and ADDR... L For the higher addresses, they form a K×L matrix, RAM1 to RAM2. K For rows, ADDR1~ADDR L For example.

[0033] The working principle of sequential input is as follows: Figure 3 As shown: For the K-channel parallel data x input at the current time, the clock cycle x 1t x 2t …、x kt …、x Kt For k = 1, 2, ..., K, first determine if the data before reordering input at this clock is in the j-th column of matrix X. ( (This indicates rounding down); then determine the number of positions to move, a, where a = mod(j-1, K) (mod() represents the modulo operation); then x kt Move from a to x rt The position, r = mod(k + a - 1, K) + 1, yields the new K-way parallel data x'. 1t 、x' 2t …、x' kt …、x' Kt .

[0034] For the K-path parallel data x' output to RAM space after being ordered, at the t-th clock cycle... 1t 、x' 2t …、x'kt …、x' Kt Read and write control such as Figure 4 As shown, the K parallel data output to the RAM space at the t-th clock cycle after reordering are divided into two cases: odd matrices and even matrices. The number of matrices is counted; each time an N x N matrix X is input, the count is incremented by 1. When the current number of matrices is odd, it is called an odd matrix; when the current number of matrices is even, it is called an even matrix. Odd and even matrices represent the relative positions of two adjacent matrices. That is, when a matrix is ​​defined as odd, the subsequent input matrix is ​​an even matrix, and vice versa. Here, b is the remainder of (t-1) / α, and c is the quotient of (j-1) / K.

[0035] The current time step is an odd matrix. When k < a, write it into RAM. k ADDR cN+bK+K+(k-a) When k≥a, write it into RAM. k ADDR cN+bK+(k-a) Simultaneously with writing, data at the same address is read out.

[0036] The current time step is an even matrix; write it into RAM. k ADDR cK+bN+a+1 Simultaneously with writing, data at the same address is read out.

[0037] For odd and even matrices, their read and write controls can be interchanged; that is, odd matrices can use the read and write controls of even matrices, and even matrices can use the read and write controls of odd matrices.

[0038] The current time step is an even matrix; when k < a, it is written into RAM. k ADDR cN+bK+K+(k-a) When k≥a, write it into RAM. k ADDR cN+bK+(k-a) Simultaneously with writing, data at the same address is read out.

[0039] The current time step is an odd matrix; write it into RAM. k ADDR cK+bN+a+1 Simultaneously with writing, data at the same address is read out.

[0040] Controlling read and write addresses is complex in real time. As described above, the addresses that need to be read and written at each moment can be pre-stored in the ROM. When data is input, the ROM is addressed according to t to obtain the current write and read addresses, which greatly simplifies the control process.

[0041] When writing the first matrix, do not read it; when reading the last matrix, do not write it.

[0042] The working principle of ordered output is as follows: Figure 5 As shown: For the K-channel parallel data y' output at the current time t 1t y' 2t …、y' kt …、y' Kt , will y' kt Move from a to y r’t The position is r', which is the remainder of (K+ka) / K (when the remainder is 0, r'=K), to obtain the K-way parallel data y after reordering. 1t y 2t …、y kt …、y Kt .

[0043] Example:

[0044] because Figure 1 The shaping in this example is a simple conversion of the number of parallel paths. For ease of drawing, the shaping is ignored in the example. The process from K-path parallel data input to K-path parallel data output is explained in detail.

[0045] In the example, K=3, N=6, and M=3.

[0046] Z 6×6 matrices for 3-way parallel pipeline inputs, with the inputs represented by 3×12 matrices:

[0047]

[0048] z = 1, 2, ..., Z, indicating that the current input is the z-th matrix, where Z can be any positive integer. X (z) The first column is the first three rows of the first column of the input 6×6 matrix, X (z) The second column is rows 4 to 6 of the first column of the input 6×6 matrix, X (z) The third column represents rows 1-3 of the second column of the input 6×6 matrix, and so on. Based on the above sorting and read / write methods, when z=1, the data stored in the storage space when writing each column is as follows: Figure 6 As shown, no reading is performed at this time; when z=2, the data stored and read in the storage space during the writing and reading of each column of data is as follows: Figure 7 As shown; when z=3, the data stored and read from the storage space during the writing and reading of each column of data is as follows: Figure 8 As shown; similarly, the transposed 6×6 matrix is ​​obtained, which can also be represented using a 3×12 matrix:

[0049]

[0050] z = 1, 2, ..., Z, indicating that the current output is the z-th matrix, X T (z) The first column represents rows 1-3 of the first column of the output 6×6 matrix, XT (z) The second column represents rows 4 to 6 of the first column of the output 6×6 matrix, X T (z) The third column is the first to third rows of the second column of the output 6×6 matrix, and so on.

[0051] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. Those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A high-speed, compact, pipelined matrix transpose method based on FPGA, characterized in that, The method includes the following steps: For an N-row × N-column matrix X input to an M-channel parallel pipeline, where M ≤ N, first, input the M-channel parallel data... 1t’ 、in 2t’ …、 in Mt’ Reshape into K-way parallel data x 1t x 2t …、x Kt K is the minimum value that is not less than M and can divide N, and N = αK, where α is a positive integer, and t' is the number of clocks for M parallel data inputs, where t' = 1, 2, ...; After shaping, the number of clock cycles input to an N x N matrix is ​​T = N. 2 / K; Counts the number of input clock cycles, with a count value of t, where t = 1, 2...T; Based on t, K-way parallel data is input in an ordered manner to obtain new K-way parallel data x'. 1t 、x' 2t …、x' Kt The aforementioned reordering of K-channel parallel data based on t specifically refers to: for the K-channel parallel data x input at the current time t-th clock cycle... 1t x 2t …、x kt …、x Kt For k=1, 2…K, first determine if the input data under this clock is in the j-th column of matrix X, j= , This indicates rounding down; then determine the number of positions to be moved, 'a', where 'a' = mod(j-1, K). mod() represents the modulo operation; then x kt Move from a to x rt The position is given by r = mod(k + a - 1, K) + 1, which yields the new K-way parallel data x'. 1t 、x' 2t …、x' kt …、x' Kt ; Write control writes new K parallel data streams into K RAM spaces of depth L, where L = N. 2 / K; Simultaneously, read from K RAM spaces via read control; output K parallel data streams y' 1t y' 2t …、y' Kt The process of writing new K parallel data into K RAM spaces of depth L via write control specifically involves: determining whether the K parallel data input at the t-th clock moment is an odd or even matrix; counting the number of matrices, incrementing the count by 1 each time an N-row × N-column matrix X is input; when the current number of matrices is odd, it is called an odd matrix; when the current number of matrices is even, it is called an even matrix. If the K-channel parallel data input at the current time (clock t) belongs to an odd matrix, when k < a, it is written into RAM. k ADDR cN+bK+K+(k-a) When k≥a, write it into RAM. k ADDR cN+bK+ (k-a) Simultaneously with writing, data at the same address is read out. If the K-channel parallel data input at the current clock moment (the t-th clock cycle) belongs to an even matrix, write it into RAM. k ADDR cK+bN+a+1 Simultaneously with writing, data at the same address is read out. Where b is the remainder of (t-1) / α, and c is the quotient of (j-1) / K; Based on t, the K-way parallel data is sorted and output to obtain the sorted K-way parallel data y. 1t y 2t …、y Kt The aforementioned method of reordering the output of K-channel parallel data based on time t specifically involves: for the K-channel parallel data y' output at the current time t... 1t y' 2t …、y' kt …、y' Kt , will y' kt Move from a to y r’t The position is r', which is the remainder of (K+ka) / K. When the remainder is 0, r'=K, and the K-way parallel data y after sorting is obtained. 1t y 2t …、y kt …、y Kt ; The K-way parallel data after sorting is then shaped to finally obtain the transposed M-way parallel data out. 1t’’ out 2t’’ …、out Mt’’ t'' is the number of clock cycles for M-channel parallel data output, t'' = 1, 2, ...

2. The high-speed, compact pipelined matrix transpose method based on FPGA according to claim 1, characterized in that, The K RAM spaces of depth L are K-way parallel storage spaces, denoted as RAM1, RAM2, ..., RAM3. K It can be written simultaneously in one clock cycle. The depth of the K-way parallel memory space is L, with ADDR1 being the low address and ADDR... L It is a high address.

3. The high-speed, compact pipelined matrix transpose method based on FPGA according to claim 1, characterized in that, Odd and even matrices represent the relative positions of two adjacent matrices. That is, when a matrix is ​​defined as odd, the matrix input after it will be even, and vice versa.

4. The high-speed, compact pipelined matrix transpose method based on FPGA according to claim 1 or 3, characterized in that, For odd and even matrices, their read and write controls can be interchanged; that is, odd matrices can use the read and write controls of even matrices, and even matrices can use the read and write controls of odd matrices.

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