Cache checking method, checking system and cache checker

Abstract

The application discloses a cache verification method, a verification system and a cache checker. The cache verification method is used for verifying an execution result of a memory corresponding to a data access instruction in the cache checker. The cache verification method comprises the following steps: calling an executable file to execute hit logic corresponding to the data access instruction to obtain a prediction result; and comparing the execution result and the prediction result to verify the correctness of the memory. By pre-compiling the hit logic into the executable file, the checker does not need to bear the logical load in the data comparison process, the running load in the cache verification process is reduced, and the cache verification efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a cache verification method, a verification system, and a cache checker. Background Technology

[0002] As design complexity increases, verification has become a crucial factor influencing the chip design process. Cache (cache memory), as a vital component of the chip, can significantly reduce processor power consumption when accessing main memory, decrease the area of ​​chip storage units, and enhance chip competitiveness. Therefore, it also needs to be verified during the chip design process.

[0003] Existing cache verification methods typically employ simulation verification, comparing the data predicted by the checking device with the data read by the storage device to verify the cache's correctness. However, current cache verification processes suffer from low efficiency due to the high load. Therefore, a new cache verification method is urgently needed. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a cache verification method, verification system and cache checker, which directly calls the executable file to execute the hit logic to obtain the prediction result during the cache verification process, thereby reducing the operating load of the cache checker and improving the running speed.

[0005] According to one aspect of this application, a cache verification method is provided for verifying the execution result of a memory corresponding to a data access instruction in a cache checker. The cache verification method includes: executing hit logic corresponding to the data access instruction by calling an executable file to obtain a prediction result; and comparing the execution result and the prediction result to verify the correctness of the memory.

[0006] Optionally, before invoking the executable file, the method further includes: creating a storage space corresponding to the cache size in the memory; and compiling the hit logic of the cache checker into an executable file.

[0007] Optionally, the cache verification method further includes: synchronizing the storage space and the cache after the storage space is created.

[0008] Optionally, when the data access instruction is hit, the prediction result is returned from the storage space; when the data access instruction is not hit, the storage space is updated according to the execution result.

[0009] Optionally, the hit logic of the cache checker is defined using a programming language, and the hit logic is pre-compiled using an editor corresponding to the programming language to obtain the executable file.

[0010] Optionally, the execution results and the prediction results are compared using a hardware description and verification language compilation script.

[0011] Optionally, the cache verifier calls the executable file through a direct programming interface.

[0012] According to another aspect of this application, a cache checker is provided for verifying the execution result of a memory. The cache checker includes: a monitoring module for acquiring a data access instruction and the execution result corresponding to the data access instruction; a prediction module, communicatively connected to the monitoring module, for calling an executable file to execute hit logic corresponding to the data access instruction to obtain a prediction result; and a comparison module, communicatively connected to the monitoring module and the prediction module, for comparing the execution result and the prediction result to verify the correctness of the memory.

[0013] Optionally, the prediction module includes: an executable file for executing hit logic corresponding to the data access instruction; and a storage space communicatively connected to the executable file, the size of which corresponds to the memory cache, for returning the prediction result based on the calculation result of the executable file.

[0014] Optionally, the hit logic is defined using a programming language, and the hit logic is pre-compiled using an editor corresponding to the programming language to obtain the executable file.

[0015] Optionally, the monitoring module and the comparison module are compiled using a hardware description and verification language.

[0016] Optionally, the monitoring module calls the executable file through a direct programming interface.

[0017] According to a third aspect of this application, a cache verification system is provided, comprising: a controller for providing data access instructions; a memory connected to the controller and returning an execution result according to the data access instructions; and a cache checker as described in any of the preceding claims, the cache checker being communicatively connected to the controller and the memory.

[0018] According to the cache verification method, verification system and cache checker of this application, since the hit logic is defined by the underlying language and pre-compiled into an executable file, the structure of the executable file is compact, the compilation quality and running efficiency are higher. In the cache verification process, the prediction result is obtained by calling the executable file, which reduces the load brought by obtaining the prediction result in the cache verification process and improves the cache verification efficiency. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This diagram illustrates a schematic block diagram of a cache verification system according to an embodiment of this application. Figure 2 This diagram illustrates a schematic block diagram of a cache checker according to an embodiment of this application. Figure 3 This is a flowchart illustrating the cache verification method according to an embodiment of this application. Detailed Implementation

[0020] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0021] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0022] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0023] A cache typically consists of two parts: logical units and storage units. The logical unit parses the tag data from the received data access command and determines whether the target data is present in the storage unit based on the tag. If the target data is present in the storage unit, it's a tag hit; otherwise, it's a tag miss. When a tag hit occurs, the cache responds to the data access command and reads the data from its storage space. When a tag miss occurs, the main storage responds to the data access command, reads the data from its main storage, and updates the cache's logical units and storage units based on the access command and the data read from main storage.

[0024] During cache checking, the checker verifies the correctness of the memory by comparing the cache data predicted by the simulation software (hereinafter referred to as the prediction result) with the cache data actually read from the memory (hereinafter referred to as the execution result). In existing technologies, the comparison unit is usually compiled using SystemVerilog (hereinafter referred to as SV) to perform data comparison. In order to meet the accuracy requirements, a large amount of cache judgment logic needs to be defined in the interface, and a storage space of the same size as the cache needs to be created. However, this makes the interface bulky, increases the load in the prediction result acquisition process, slows down the prediction result acquisition speed, and results in low cache check rate.

[0025] Figure 1 A schematic block diagram of a cache verification system according to an embodiment of this application is shown. As shown, the cache verification system 1 includes a controller 300, a memory 200 communicatively connected to the controller 300, and a cache checker 100 communicatively connected to both the controller 300 and the memory 200. The controller 300 sends a data access instruction to the memory 200 to obtain the memory execution result corresponding to the data access instruction. Furthermore, the cache checker 100 also captures the data access instruction and obtains its corresponding prediction result, which is also captured by the cache checker. The correctness of the memory is determined by comparing the execution result and the prediction result.

[0026] like Figure 1 As shown, the memory 200 includes a logic verification module 210 and a cache module 220 and a main memory module 230 connected to it. The logic verification module 210 receives and parses data access instructions, and determines whether the cache module 220 caches the target data corresponding to the data access instruction based on the parsed tag data. If the cache module 220 contains the target data, it is a tag hit; if the cache module 220 does not contain the target data, it is a tag missing. When a tag hits, the logic verification module 210 sends a first access instruction to the cache module 220, and the cache module 220 returns a first access result based on the first access instruction. When a tag is missing, the logic verification module 210 sends a second access instruction to the main memory module 230, and the main memory module 230 returns a second access result based on the second access instruction. After obtaining the first or second access result, the logic verification module 210 processes it into an execution result. Furthermore, when a tag is missing, the logic verification module 210 updates its internal judgment logic according to the data access instruction and writes the second access result to the cache module 220 to update the cached data in the second cache unit. It should be noted that when the cache module 220 is full, when storing data into it, some stored content needs to be deleted based on the tag data before storing the new content.

[0027] like Figure 1 As shown, the cache checker 100 includes a monitoring module 110, a prediction module 120, and a comparison module 130. The monitoring module 110 is used to capture data access commands issued by the controller 300 and execution results returned by the memory 200, and sends the execution results to the comparison module 130. The prediction module 120 is invoked through the data access command. The prediction module 120 is communicatively connected to the monitoring module and is used to invoke the executable file to execute the hit logic corresponding to the data access command to obtain the prediction result. The comparison module 130 is communicatively connected to the monitoring module 110 and the prediction module 120 and is used to compare the execution result and the prediction result to verify the correctness of the memory 200.

[0028] Specifically, Figure 2 Show Figure 1 The schematic block diagram of the cache checker 100 is shown in the figure. The prediction module 120 includes an executable file 121 and a storage space 122. The executable file 121 is communicatively connected to the monitoring module 110 and the comparison module 130, respectively, and is used for the execution hit logic of the cache checker. The storage space 122 is communicatively connected to the executable file 121, and the size of the storage space 122 corresponds to that of the cache module 220 in the memory 200.

[0029] For example, in this embodiment, the monitoring module 110 and the comparison module 130 are compiled using the SV language, the storage space and the hit logic of the prediction module 120 are defined using the C / C++ language, and the hit logic is pre-compiled into an executable file using the GCC (GNU Compiler Collection) editor. The monitoring module 110 calls the prediction module 120 through the DPI (Direct Programming Interface). However, it should be understood that the compilation language of each module should not be limited to this. For example, the monitoring module 110 and the comparison module 130 can also be compiled using the Verilog language or other hardware description and verification languages, and the hit logic in the prediction module 120 can be defined using, for example, the Basic language or other programming languages ​​and pre-compiled into an executable file using an editor that matches the programming language.

[0030] The monitoring module 110 calls the prediction module 120 according to the data access instruction. The executable file 121 receives and parses the data access instruction, and determines whether the storage space 122 contains the target data corresponding to the data access instruction based on the parsed tag data. If the storage space 122 contains the target data, the tag is hit; if the storage space 122 does not contain the target data, the tag is missing. When the tag is hit, the executable file 121 sends a third access instruction to the storage space 122, and the storage space 122 returns the prediction result according to the three access instructions. The prediction result is processed by the executable file 121 and sent to the comparison unit 112 for comparison with the execution result. When the tag is missing, the executable file 121 updates the hit logic according to the data access instruction and writes the processed execution result back to the storage space 122 to update the cached data in the storage space 122. It should be noted that when the storage space 122 is full, when storing data in it, some stored content needs to be deleted according to the tag data before storing new content.

[0031] The comparison module 130 compares the execution result with the prediction result to verify the correctness of the memory 200. If the execution result and the prediction result are consistent, the memory is correct; if the execution result and the prediction result are inconsistent, it is necessary to find out if there is a problem with the memory.

[0032] According to the cache verification system and cache checker of this application, since the hit logic is defined by the underlying language and pre-compiled into an executable file, the structure of the executable file is compact, the compilation quality and running efficiency are higher. During the cache verification process, the prediction result is obtained by calling the executable file, which reduces the load brought by obtaining the prediction result during the cache verification process and improves the cache verification efficiency.

[0033] Figure 3 A schematic flowchart illustrating a cache verification method according to an embodiment of this application is shown. As shown, it includes the following steps: Step S01: Create a storage space corresponding to the cache size in memory; In this step, a storage space 122 corresponding to the size of the cache module 220 in the memory 200 is created. In some embodiments, the storage space 122 is defined using C / C++, while in some other embodiments, it is defined using Basic or other programming languages.

[0034] Step S02: Edit the hit logic into an executable file; In this step, the hit logic of the cache checker 100 is defined and pre-compiled into an executable file 121. In some embodiments, the hit logic is defined in C / C++ and pre-compiled into an executable file 121 using a GCC editor. In some other embodiments, the hit logic is defined in Basic or other programming languages ​​and pre-compiled into an executable file 121 using an editor corresponding to that programming language.

[0035] Step S03: Capture the data access instructions and the execution results of the memory; In this step, the monitoring module 110 captures the data access command issued by the controller 300 and the execution result returned by the memory 200 in response to the data access command.

[0036] In some embodiments, the logic verification module 210 receives and parses a data access instruction, and determines whether the cache module 220 caches the target data corresponding to the data access instruction based on the parsed tag data. If the cache module 220 contains the target data, the tag is hit; if the cache module 220 does not contain the target data, the tag is missing. When the tag is hit, the logic verification module 210 sends a first access instruction to the cache module 220, and the cache module 220 returns a first access result based on the first access instruction. When the tag is missing, the logic verification module 210 sends a second access instruction to the main storage module 230, and the main storage module 230 returns a second access result based on the second access instruction. After obtaining the first or second access result, the logic verification module 210 processes it into an execution result.

[0037] Step S04: Call the executable file to execute the hit logic; In this step, the monitoring module 110 calls the prediction module 120 according to the captured data access instruction. The executable file 121 receives and parses the data access instruction and executes the hit logic corresponding to the data access instruction.

[0038] Step S05: Determine if a hit has occurred; In this step, the executable file 121 determines whether the storage space 122 contains the target data corresponding to the data access instruction based on the parsed tag data. If the storage space 122 contains the target data, the tag is hit; if the storage space 122 does not contain the target data, the tag is missing.

[0039] When a tag is matched, execute steps S06 and S07; when a tag is missing, execute step S08.

[0040] Step S06: Return the prediction results from the storage space; In this step, the logic verification module 210 sends a first access instruction to the cache module 220, and the cache module 220 returns a first access result according to the first access instruction. Step S07: Compare the prediction results with the execution results; In this step, the comparison module 130 compares the execution result with the prediction result to verify the correctness of the memory 200. If the execution result and the prediction result are consistent, the memory is correct; if the execution result and the prediction result are inconsistent, it is necessary to find out if there is a problem with the memory.

[0041] Step S08: Update storage space.

[0042] In this step, the logic verification module 210 sends a second access instruction to the main storage module 230, and the main storage module 230 returns a second access result based on the second access instruction. The logic verification module 210 processes the first or second access result into an execution result after obtaining it. It should be noted that when the storage space 122 is full, when storing data into it, some stored content needs to be deleted based on the tag data before storing new content.

[0043] According to the cache verification method of this application, since the hit logic is defined in the underlying language and pre-compiled into an executable file, the structure of the executable file is compact, the compilation quality and running efficiency are higher. In the cache verification process, the prediction result is obtained by calling the executable file, which reduces the load brought by obtaining the prediction result in the cache verification process and improves the cache verification efficiency.

[0044] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A cache verification method for verifying the execution result of a memory corresponding to a data access instruction in a cache checker, the cache verification method comprising: Create a storage space corresponding to the cache size in the memory; Synchronize the storage space and the cache; Compile the cache checker's hit logic into an executable file; The prediction result is obtained by calling the executable file to execute the hit logic corresponding to the data access instruction; as well as The execution results and the prediction results are compared to verify the correctness of the memory.

2. The cache verification method according to claim 1, wherein, When the data access instruction is hit, the prediction result is returned from the storage space; when the data access instruction is not hit, the storage space is updated according to the execution result.

3. The cache verification method according to claim 1, wherein, The hit logic of the cache checker is defined using a programming language, and the hit logic is pre-compiled using an editor corresponding to the programming language to obtain the executable file.

4. The cache verification method according to claim 3, wherein, The execution results and the prediction results are compared using a hardware description and verification language compilation script.

5. The cache verification method according to claim 4, wherein, The cache verifier calls the executable file through a direct programming interface.

6. A cache checker for verifying the execution result of a memory, the cache checker comprising: The monitoring module is used to acquire data access instructions and the execution results corresponding to the data access instructions; The prediction module is communicatively connected to the monitoring module and is used to call the executable file to execute the hit logic corresponding to the data access instruction according to the data access instruction to obtain the prediction result. as well as The comparison module, communicatively connected to the monitoring module and the prediction module, is used to compare the execution result and the prediction result to verify the correctness of the memory. The prediction module includes: An executable file for executing the hit logic corresponding to the data access instruction; and The storage space is communicatively connected to the executable file, and the size of the storage space corresponds to the memory cache. It is used to return the prediction result based on the calculation result of the executable file.

7. The cache checker according to claim 6, wherein, The hit logic is defined using a programming language, and the hit logic is pre-compiled using an editor corresponding to the programming language to obtain the executable file.

8. The cache checker according to claim 7, wherein, The monitoring module and the comparison module are compiled using a hardware description and verification language.

9. The cache checker according to claim 8, wherein, The monitoring module calls the executable file through a direct programming interface.

10. A cache verification system, comprising: The controller is used to provide data access instructions; The memory, connected to the controller, returns the execution result according to the data access instruction; as well as The cache checker as described in claims 6-9, wherein the cache checker is communicatively connected to the controller and the memory.

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