A binary phase-locked loop time-domain noise modeling method based on MATLAB

Abstract

The application discloses a binary phase-locked loop time domain noise modeling method based on MATLAB, and the whole model is divided into two parts, first, the behavior of the binary phase-locked loop is described to abstract the time domain iterative equation, and second, the phase noise of the numerically controlled oscillator is analyzed, the phase noise is converted into power spectral density, and MATLAB functions are used to generate a random array with corresponding power spectral density in the time domain as a time domain noise source, namely jitter, to simulate the behavior of the numerically controlled oscillator. The binary phase-locked loop time domain noise modeling is completed. The phase noise of important circuit modules such as the numerically controlled oscillator is converted into time domain noise and added to the loop time domain iterative equation after fitting, and the method has the advantages of flexible parameters, accurate behavior and fast simulation speed. The method simulates the zero-order hold delay caused by the discrete work of the system, is more accurate for the stability analysis of the system, and realizes more flexible and simple phase noise addition.

Description

Technical Field

[0001] This invention relates to a time-domain noise modeling method for binary phase-locked loops based on MATLAB, belonging to the field of phase-locked loops. Background Technology

[0002] Wireless communication technology is widely used in smart home appliances, mobile phones, wearable medical devices, and other fields. Driven by broad market demand, wireless communication technology is developing towards lower power consumption, lower cost, and stronger interference resistance. The frequency synthesizer is the core module of the entire wireless communication system, and its phase-locked loop (PLL) circuit provides a high-quality clock for the system to achieve frequency synthesis and phase modulation. The noise performance of the PLL directly affects the system's communication accuracy and bit error rate. Compared to traditional analog PLLs, digital phase-locked loops (DPLLs) offer advantages such as shorter design cycles, automated layout implementation of some circuits, resistance to PVT variations, strong process portability, and flexible calibration, making them an important direction for PLL development.

[0003] Among the various types of DPLLs, binary phase-locked loops (PLLs) have become a key research focus due to their advantages of simple phase detector design, space-saving design, and large loop bandwidth. However, the strong nonlinearity of the phase detector output in binary PLLs makes loop gain analysis complex. Typically, it is necessary to first determine the time jitter of the phase detector input to approximate the loop gain, and the simulation process consumes a lot of time, leading to a longer design cycle and making binary PLL implementations less competitive in the market. Summary of the Invention

[0004] This invention proposes a MATLAB-based time-domain iterative equation model for binary phase-locked loops (PLLs). It transforms the phase noise of critical circuit modules, such as the numerically controlled oscillator (CNC), into time-domain noise, fits it, and adds it to the loop's time-domain iterative equation. This model offers advantages such as flexible parameters, accurate behavior, and fast simulation speed. The invention divides the overall model into two parts. First, the first part describes the behavior of the binary PLL, abstracting its time-domain iterative equation. Second, it analyzes the phase noise of the CNC oscillator, transforming it into power spectral density. MATLAB functions are then used to generate a random array with a corresponding power spectral density in the time domain as a time-domain noise source, i.e., jitter, mimicking the behavior of the CNC oscillator. This completes the time-domain noise modeling of the binary PLL.

[0005] The above objectives are achieved through the following technical solutions:

[0006] A MATLAB-based method for modeling time-domain noise in binary phase-locked loops (PLLs) is presented. The resulting binary PLL loop model, based on an iterative time-domain equation model, includes a binary phase detector, a second-order digital filter, a delay unit, a digitally controlled oscillator, and a frequency divider. Its operating state is as follows:

[0007] The binary phase detector detects the relationship between the rising edge of the reference clock and the rising edge of the feedback clock. When the reference clock leads the feedback clock, the binary phase detector outputs 1 to increase the loop frequency; conversely, it outputs -1 to decrease the loop frequency. A MATLAB function, `sgn`, is used to simulate this phase detection behavior.

[0008]

[0009] The second-order digital filter includes a proportional path and an integral path. The proportional path multiplies the output of the binary phase detector by the proportional gain and outputs it directly. The integral path accumulates the output of the binary phase detector with a reference clock period, and then multiplies it by the integral gain before outputting it.

[0010] The delay unit simulates the delay generated by the phase detector and digital filter during digital processing, making the model behavior closer to the actual binary phase-locked loop circuit.

[0011] The numerically controlled oscillator multiplies the control word by its time resolution and adds it to its initial oscillation period to obtain the adjusted oscillator output period. This period is multiplied by the frequency division ratio to obtain the period of the frequency divider feedback clock. Accumulating the periods of the frequency divider feedback clock yields the rise time of the feedback clock. Accumulating the feedback clock periods yields the rise time of the feedback clock, and accumulating the reference clock periods yields the rise time of the reference clock. These two parameters are sent back to the binary phase detector for the next round of frequency adjustment. Finally, the phase-locked loop is locked to a fixed phase.

[0012] Furthermore, the time-domain iterative equation model of the aforementioned binary phase-locked loop is established as follows:

[0013]

[0014] Where PD(i) is the output of the phase detector in this round, ACC(i) is the output of the accumulator in this round, DLF(i) is the frequency control word of the oscillator in this round, iD represents the oscillator frequency control word output by the digital filter after D cycles of data processing, and t ref (i) represents the time of the rising edge of the current reference clock output, t fbc (i) represents the rise time of the current frequency divider output, N is the phase-locked loop division ratio, and T is the time of the rise time of the current frequency divider output. out F is the output period after the phase-locked loop is locked. err KT is the ratio of the oscillator's output period under initial conditions to its output period after locking, DCO_NOISE(i) is the oscillator's time resolution, and T is the oscillator's cumulative jitter within the reference period equivalent to the input. err (i) is the time difference between the rising edge of the reference clock and the rising edge of the feedback clock generated in this round.

[0015] Furthermore, the oscillator phase noise is analyzed, and a random array is generated to simulate the time-domain behavior of the noise. The low-frequency component of the oscillator phase noise is caused by circuit flicker noise, exhibiting a frequency of 1 / f. 3 The high-frequency noise is caused by circuit thermal noise and is characterized by 1 / f 2 characteristic:

[0016]

[0017] Where, k flick k is the flicker noise coefficient. white The white noise figure is given. The oscillator phase noise power spectral density is:

[0018]

[0019] The phase difference between the oscillator output phase and the ideal output phase is Phase. err The difference between the output period and the ideal output period is T. err The transformation relationship between the two is as follows:

[0020] Phase err (i) / ω out =T err (i)(4)

[0021] Where, ω out For the ideal output phase, it is also equal to 2π / T. out Therefore, the power spectral density of the oscillator periodic noise is obtained as follows:

[0022]

[0023] Equivalent to the input of an oscillator:

[0024]

[0025] Therefore, the oscillator phase noise, when considered at the oscillator input, can be viewed as a superposition of white noise and noise with a 1 / f characteristic. Using the MATLAB function `wgn(m, n, power)`, a random number with an m x n power spectral density of `power` following a Gaussian distribution can be generated, which can represent the white noise component of the oscillator. Using the MATLAB function `filter(b, a, x)`, a sequence with a numerator coefficient of `b` and a denominator coefficient of `a` filtered by `x` can be generated. When `b` and `a` take appropriate values, a first-order low-pass filtering effect on the output sequence power spectrum can be achieved, representing noise with a 1 / f characteristic. 2 The noise power spectrum of the characteristics. Several first-order low-pass filters H with different corner frequencies. k(f) Superposition can shape the power spectral density of the input white noise into a noise power spectrum with 1 / f characteristics, such as... Figure 2 As shown. The white noise is superimposed with the noise with the 1 / f characteristic, i.e., DCO_NOISE(i) in equation (1).

[0026] The method specifically includes the following steps:

[0027] Step 1: Establishing the time-domain model of the binary phase detector;

[0028] The input to the binary phase detector is the time between the rising edge of the reference clock and the rising edge of the feedback clock. When the rising edge of the reference clock leads the rising edge of the feedback clock, the binary phase detector outputs PD(i) as 1; otherwise, it outputs -1. A MATLAB function, sgn, is used to simulate this phase detector behavior.

[0029]

[0030] Among them, t ref (i) represents the time of the rising edge of the current reference clock output, t fbc (i) represents the time of the rising edge of the frequency divider output in this round.

[0031] Step 2: Establishing the time-domain model of the second-order digital filter and delay unit;

[0032] The second-order digital filter includes a proportional path and an integral path. The proportional path directly outputs the binary phase detector output by multiplying it by the proportional gain. The integral path accumulates the binary phase detector output with a reference clock period, then multiplies it by the integral gain before outputting. The delay unit simulates the delay generated during the digital processing of the phase detector and digital filter, delaying the second-order digital filter output value by D cycles to obtain the control word DLF[i] of the numerically controlled oscillator.

[0033]

[0034] Where KI is the integral gain, KP is the proportional gain, and D is the delay generated during digital processing.

[0035] Step 3: Establishing the time-domain model of the numerically controlled oscillator and frequency divider;

[0036] The input of the numerically controlled oscillator is the output of a second-order digital filter, with its phase noise equivalently represented at the input. The output of the numerically controlled oscillator is proportional to the rise time of its input clock. The frequency divider divides the output of the numerically controlled oscillator by N, and the rise time of the output feedback clock is:

[0037] t fbc [i] = t fbc [i-1]+N×(T out ×Ferr +KT×(DLF[i]+DCO_NOISE[i]))

[0038] Where N is the division ratio of the frequency divider, and T out F is the output period after the phase-locked loop is locked. err KT is the ratio of the oscillator's output period under initial conditions to its output period after locking, used to simulate the frequency locking process of a phase-locked loop. KT is the oscillator's time resolution.

[0039] Step 4: Establishing the time-domain model of the binary phase-locked loop;

[0040] Rewrite the time-domain expressions of each module in steps one through three as a system of simultaneous equations to obtain the time-domain model of the binary phase-locked loop:

[0041]

[0042] Where i represents the number of simulations.

[0043] Step 5: Establishing a time-domain model of the noise at the input of the numerically controlled oscillator;

[0044] Equation (6) converts the output phase noise obtained from the simulation of the actual numerically controlled oscillator circuit into input time-domain noise. The time-domain noise is added to the time-domain model of the numerically controlled oscillator, and the rise time of the output clock of the numerically controlled oscillator is processed by FFT and other methods to obtain the phase noise output by the time-domain model of the noise at the input of the numerically controlled oscillator.

[0045] Step 6: Add the noise at the input of the numerically controlled oscillator to the time-domain model of the binary phase-locked loop. Perform FFT and other processing on the rising edge time of the output clock of the numerically controlled oscillator to obtain the output phase noise of the designed binary phase-locked loop. The result is consistent with the output phase noise obtained by simulation of the actual binary phase-locked loop circuit.

[0046] Compared with existing technologies, the binary phase-locked loop time-domain iterative equation model described in this invention accurately describes the sampling characteristics of its discrete system and can simulate the zero-order hold delay caused by the discrete operation of the system, resulting in more accurate system stability analysis. In the binary phase-locked loop time-domain iterative equation model, data processing between different modules uses integer operations to simulate quantization noise in digital circuits, ensuring the integrity of the model's noise sources. The oscillator phase noise described in this invention is converted into time-domain noise, and the power spectrum shaping method is used to simulate the oscillator phase noise, achieving more flexible and convenient phase noise addition. Attached Figure Description

[0047] Figure 1 This is a binary phase-locked loop model diagram of the present invention.

[0048] Figure 2This is the 1 / f noise frequency spectrum of the low-pass filter shaping of this invention.

[0049] Figure 3 This is a diagram showing the time-domain modeling results of phase noise in this invention.

[0050] Figure 4 This is a comparison chart of the binary phase-locked loop time-domain modeling results and the actual circuit simulation results of this invention. Detailed Implementation

[0051] The present invention will be described in detail with reference to specific embodiments. A method for modeling time-domain noise of a binary phase-locked loop based on MATLAB includes the following steps:

[0052] Step 1: Establishing the time-domain model of the binary phase detector;

[0053] The input to the binary phase detector is the time between the rising edge of the reference clock and the rising edge of the feedback clock. When the rising edge of the reference clock leads the rising edge of the feedback clock, the binary phase detector outputs PD(i) as 1; otherwise, it outputs -1. A MATLAB function, sgn, is used to simulate this phase detector behavior.

[0054]

[0055] Among them, t ref (i) represents the time of the rising edge of the current reference clock output, t fbc (i) represents the time of the rising edge of the frequency divider output in this round.

[0056] Step 2: Establishing the time-domain model of the second-order digital filter and delay unit;

[0057] The second-order digital filter includes a proportional path and an integral path. The proportional path directly outputs the binary phase detector output by multiplying it by the proportional gain. The integral path accumulates the binary phase detector output with a reference clock period, then multiplies it by the integral gain before outputting. The delay unit simulates the delay generated during the digital processing of the phase detector and digital filter, delaying the second-order digital filter output value by D cycles to obtain the control word DLF[i] of the numerically controlled oscillator.

[0058]

[0059] Where KI is the integral gain, which is taken as 2 in this example. -1 KP is the proportional gain, which is 10 in this example, and D is the delay generated by the digital processing, which is 1 in this example.

[0060] Step 3: Establishing the time-domain model of the numerically controlled oscillator and frequency divider;

[0061] The input of the numerically controlled oscillator is the output of a second-order digital filter, with its phase noise equivalently represented at the input. The output of the numerically controlled oscillator is proportional to the rise time of its input clock. The frequency divider divides the output of the numerically controlled oscillator by N, and the rise time of the output feedback clock is:

[0062] t fbc [i] = t fbc [i-1]+N×(T out ×F err +KT×(DLF[i]+DCO_NOISE[i]))

[0063] Where N is the division ratio of the frequency divider, which is 40 in this example, and T out The output period after the phase-locked loop is locked is 1 / (2.4×10). 9 ), F err This is the ratio of the oscillator's output period under initial conditions to its output period after locking, used to simulate the frequency locking process of a phase-locked loop. In this example, it is taken as 0.99. KT is the oscillator's time resolution, which is taken as 1.73 × 10⁻⁶ in this example. -15 .

[0064] Step 4: Establishing the time-domain model of the binary phase-locked loop;

[0065] The time-domain expressions of each module in steps one through three are rewritten as a system of simultaneous equations according to equation (1) to obtain the time-domain model of the binary phase-locked loop described in this example:

[0066]

[0067] Where i represents the number of simulations, which is 10 in this example. 6 This ensures a sufficient number of rising clock edges from the oscillator output, guaranteeing the accuracy of the loop phase noise obtained from its processing.

[0068] Step 5: Establishing a time-domain model of the noise at the input of the numerically controlled oscillator;

[0069] Equation (6) converts the output phase noise obtained from the simulation of the actual numerically controlled oscillator circuit into input time-domain noise. In this example, the flicker phase noise angular frequency of the numerically controlled oscillator is taken as 10°. 4 Phase noise -120dBc / Hz@1MHz. The time-domain noise is added to the time-domain model of the numerically controlled oscillator (CNC oscillator). FFT and other processing are performed on the rise time of the CNC oscillator output clock to obtain the phase noise output from the time-domain model of the CNC oscillator input noise, as shown below. Figure 3 As shown.

[0070] Step Six: Add the noise from the input of the numerically controlled oscillator to the time-domain model of the binary phase-locked loop. Perform FFT and other processing on the rise time of the output clock of the numerically controlled oscillator to obtain the output phase noise of the binary phase-locked loop designed in this example, as shown below. Figure 4 As shown, the results are basically consistent with the output phase noise obtained from the simulation of the actual binary phase-locked loop circuit.

[0071] Of course, the above description is not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A method for modeling time-domain noise in a binary phase-locked loop based on MATLAB, characterized in that, The binary phase-locked loop loop model established by this method based on the binary phase-locked loop time-domain iterative equation model includes a binary phase detector, a second-order digital filter, a delay unit, a digitally controlled oscillator, and a frequency divider; Its working status is as follows: The binary phase detector detects the relationship between the rising edge of the reference clock and the rising edge of the feedback clock. When the reference clock leads the feedback clock, the binary phase detector outputs 1 to increase the loop frequency; conversely, it outputs -1 to decrease the loop frequency. A MATLAB function, sgn, is used to simulate this phase detection behavior. The second-order digital filter includes a proportional path and an integral path. The proportional path multiplies the output of the binary phase detector by the proportional gain and outputs it directly. The integral path accumulates the output of the binary phase detector with a reference clock period, and then multiplies it by the integral gain before outputting it. The aforementioned delay unit simulates the delay generated by the phase detector and digital filter during digital processing, making the model behavior closer to the actual binary phase-locked loop circuit. The numerically controlled oscillator multiplies the control word by its time resolution and adds it to its initial oscillation period to obtain the adjusted oscillator output period. This period is multiplied by the frequency division ratio to obtain the period of the frequency divider feedback clock. The periods of the frequency divider feedback clock are accumulated to obtain the time of the rising edge of the feedback clock. The feedback clock cycle is accumulated to obtain the time of the rising edge of the feedback clock, and the reference clock cycle is accumulated to obtain the time of the rising edge of the reference clock. The two parameters are sent back to the binary phase detector for the next round of frequency adjustment operation, and finally the phase-locked loop will be locked to a fixed phase.

2. The binary phase-locked loop time-domain noise modeling method based on MATLAB according to claim 1, characterized in that, The time-domain iterative equation model of the aforementioned binary phase-locked loop is established as follows: Where PD(i) is the output of the phase detector in this round, ACC(i) is the output of the accumulator in this round, DLF(i) is the frequency control word of the oscillator in this round, iD represents the oscillator frequency control word output by the digital filter after D cycles of data processing, and t ref (i) represents the time of the rising edge of the current reference clock output, t fbc (i) represents the rise time of the current frequency divider output, N is the phase-locked loop division ratio, and T is the time of the rise time of the current frequency divider output. out F is the output period after the phase-locked loop is locked. err KT is the ratio of the oscillator's output period under initial conditions to its output period after locking, DCO_NOISE(i) is the oscillator's time resolution, and T is the oscillator's cumulative jitter within the reference period equivalent to the input. err (i) is the time difference between the rising edge of the reference clock and the rising edge of the feedback clock generated in this round.

3. The binary phase-locked loop time-domain noise modeling method based on MATLAB according to claim 1, characterized in that, The oscillator phase noise is analyzed, and a random array is generated to simulate the time-domain behavior of the noise. The low-frequency component of the oscillator phase noise is caused by circuit flicker noise, which is 1 / f 3 The high-frequency noise is caused by circuit thermal noise and is characterized by 1 / f 2 characteristic: Where, k flick k is the flicker noise coefficient. white The white noise figure is: The oscillator phase noise power spectral density is: The phase difference between the oscillator output phase and the ideal output phase is Phase. err The difference between the output period and the ideal output period is T. err The transformation relationship between the two is as follows: Phase err (i) / ω out =T err (i)(4) Where, ω out For the ideal output phase, it is also equal to 2π / T. out The power spectral density of the oscillator periodic noise is obtained as follows: Equivalent to the input of an oscillator: The oscillator phase noise, equivalent to the superposition of white noise and noise with 1 / f characteristics at the oscillator input, is represented by the MATLAB function wgn(m, n, power), which generates m rows and n columns of random numbers with a power spectral density of power that conforms to a Gaussian distribution, representing the white noise component of the oscillator. The MATLAB function filter(b, a, x) generates a sequence filtered by x, with numerator coefficient b and denominator coefficient a. When b and a take appropriate values, a first-order low-pass filtering effect is achieved on the power spectrum of the output sequence, representing noise with 1 / f characteristics. 2 The noise power spectrum of the characteristics; several first-order low-pass filters with different corner frequencies H k (f) Superposition, which shapes the power spectral density of the input white noise into a noise power spectrum with 1 / f characteristics; superimposing the white noise with the noise with 1 / f characteristics, i.e., DCO_NOISE(i) in equation (1).

4. The binary phase-locked loop time-domain noise modeling method based on MATLAB according to claim 1, characterized in that, The method specifically includes the following steps: Step 1: Establishing the time-domain model of the binary phase detector; The input to the binary phase detector is the time difference between the rising edge of the reference clock and the rising edge of the feedback clock. When the rising edge of the reference clock leads the rising edge of the feedback clock, the binary phase detector outputs PD(i) as 1; otherwise, it outputs -1. A MATLAB function, sgn, is used to simulate this phase detector behavior. Among them, t ref (i) represents the time of the rising edge of the current reference clock output, t fbc (i) represents the rising edge time of the frequency divider output in this round; Step 2: Establishing the time-domain model of the second-order digital filter and delay unit; The second-order digital filter includes a proportional path and an integral path. The proportional path multiplies the output of the binary phase detector by the proportional gain and outputs it directly. The integral path accumulates the output of the binary phase detector with a reference clock period, and then multiplies it by the integral gain before outputting it. The delay unit simulates the delay generated by the digital processing of the phase detector and the digital filter, and delays the output value of the second-order digital filter by D periods to obtain the control word DLF[i] of the numerically controlled oscillator. Where KI is the integral gain, KP is the proportional gain, and D is the delay generated during digital processing; Step 3: Establishing the time-domain model of the numerically controlled oscillator and frequency divider; The input of the numerically controlled oscillator is the output of a second-order digital filter, and its phase noise is equivalent to the input. The output of the numerically controlled oscillator is proportional to the rise time of its input clock. The frequency divider divides the output of the numerically controlled oscillator by N, and the output feedback clock rise time is: t fbc [i]=t fbc [i-1]+N×(T out ×F err +KT×(DLF[i]+DCO_NOISE[i])) Where N is the division ratio of the frequency divider, and T out F is the output period after the phase-locked loop is locked. err KT is the ratio of the oscillator's output period under initial conditions to its output period after locking, used to simulate the frequency locking process of a phase-locked loop. KT is the oscillator's time resolution. Step 4: Establishing the time-domain model of the binary phase-locked loop; Rewrite the time-domain expressions of each module in steps one through three as a system of simultaneous equations to obtain the time-domain model of the binary phase-locked loop: Where i represents the number of simulations; Step 5: Establishing a time-domain model of the noise at the input of the numerically controlled oscillator; Equation (6) converts the output phase noise obtained from the simulation of the actual numerically controlled oscillator circuit into the input time-domain noise. The time-domain noise is added to the time-domain model of the numerically controlled oscillator, and the rise time of the output clock of the numerically controlled oscillator is processed by FFT and other methods to obtain the phase noise output by the time-domain model of the noise at the input of the numerically controlled oscillator. Step 6: Add the noise at the input of the numerically controlled oscillator to the time-domain model of the binary phase-locked loop. Perform FFT processing on the rising edge time of the output clock of the numerically controlled oscillator to obtain the output phase noise of the designed binary phase-locked loop. The result is consistent with the output phase noise obtained from the simulation of the actual binary phase-locked loop circuit.

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