A circuit layout method based on welsh-powell algorithm

Abstract

The present disclosure discloses a circuit layout method based on Welsh-Powell algorithm, comprising the following steps: S100: performing module division on a circuit to be laid out to obtain circuit modules of the circuit to be laid out; S200: setting a module point object according to circuit modules having mutual exclusion relationship in the circuit modules; S300: establishing a connection relationship of the module point object and constructing a first mathematical model G1; S400: constructing a second mathematical model G2 based on the first mathematical model G1; S500: marking the second mathematical model G2 based on the Welsh-Powell algorithm to obtain a third mathematical model G3; and S600: laying out the circuit to be laid out based on the third mathematical model G3. The present disclosure can obtain a better PCB layout structure based on the Welsh-Powell algorithm, effectively improve the efficiency and correctness of the PCB design, and save the cost of IC testing.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor finished product testing technology, specifically relating to a circuit layout method and apparatus based on the Welsh-Powell algorithm. Background Technology

[0002] In recent years, with the rapid development of integrated circuit technology, SOC (System on Chip) chips have played an increasingly important role in the IC (Integrated Circuit) industry. Integrating digital circuits, analog circuits, memory circuits, and radio frequency circuits onto a single chip has become an inevitable trend in integrated circuit development. As the integration level of chip functions increases, higher requirements are placed on automatic test equipment (ATE) and test loadboards, and testing costs have become an indispensable factor in chip costs.

[0003] Currently, there are two main PCB layout methods: one is based on signal flow, i.e., PCB layout in a left-center-right order of signal input, signal processing, and signal output; the other is simply categorizing different functional modules and scattering them on the PCB in a star topology. These two PCB layout methods are fine for simple circuits, but with the development of IC technology, the integration of SOC chips is becoming increasingly higher, their functions are becoming more complex, and their corresponding intelligent computing power, core speeds are becoming faster, and the amount of data processed is increasing. The above PCB layout methods can lead to data transmission bottlenecks, thus failing to meet the rapid development of SOC systems. Furthermore, since there is no unified standard for PCB layout, engineers often need to rely on experience to simplify the design process. For novice PCB design engineers, this requires multiple PCB modifications, increasing PCB prototyping costs and reducing product development efficiency. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this disclosure is to provide a circuit layout method based on the Welsh-Powell algorithm. This method can obtain the optimal PCB layout structure based on the Welsh-Powell algorithm, which can effectively improve the efficiency and accuracy of PCB design on the one hand, and save IC testing costs on the other hand.

[0005] To achieve the above objectives, this disclosure provides the following technical solutions:

[0006] A circuit placement method based on the Welsh-Powell algorithm includes the following steps:

[0007] S100: Divide the circuit to be laid out into modules to obtain the circuit modules of the circuit to be laid out;

[0008] S200: Set module point objects according to the circuit modules that have mutual exclusion relationships in the circuit modules;

[0009] S300: Establish the connection relationship between module point objects and construct the first mathematical model G1;

[0010] S400: Construct a second mathematical model G2 based on the first mathematical model G1;

[0011] S500: The second mathematical model G2 is labeled based on the Welsh-Powell algorithm to construct the third mathematical model G3;

[0012] S600: Layouts the circuit to be laid out based on the third mathematical model G3.

[0013] Preferably, step S300 includes the following steps:

[0014] S301: Based on the mutual exclusion relationship between modules, the modules are arranged separately;

[0015] S302: Connect the module point objects corresponding to mutually exclusive modules to obtain the first mathematical model G1.

[0016] Preferably, step S400 includes the following steps:

[0017] S401: Calculate the degree d of each module point object in the first mathematical model G1;

[0018] S402: Sort the degree d of each module point object and redefine each module point object based on the sorting result. The redefined module point object is represented as V = {v1, v2, v3, ..., v...} i}, where i represents the number of module point objects;

[0019] S403: Construct a second mathematical model G2 based on the redefined point objects of each module.

[0020] Preferably, in step S500, the second mathematical model G2 is labeled using the following method:

[0021] S501: Define the labeling function π(x): x = {v1, v2, v3, ..., v...} i}, where i represents the number of module point objects;

[0022] S502: Mark each module point object according to the association between the redefined module point objects and based on the marking function π(x).

[0023] Preferably, in step S600, the layout of the circuit to be laid out based on the third mathematical model G3 includes: dividing the single-layer PCB board into regions according to the markings of the module point objects in the third mathematical model G3, prioritizing the divided regions, and placing modules with the same markings in G3 into the corresponding regions.

[0024] Preferably, in step S600, the layout of the circuit to be laid out based on the third mathematical model G3 further includes: dividing the PCB board into corresponding signal layers according to the markings of the module point objects in the third mathematical model G3, prioritizing the divided signal layers, and placing modules with the same markings in G3 into the corresponding signal layers.

[0025] This disclosure also provides a circuit layout apparatus based on the Welsh-Powell algorithm, comprising:

[0026] The module division is used to divide the circuit to be laid out into modules to obtain the circuit modules of the circuit to be laid out.

[0027] A setting module is used to set module point objects based on the mutually exclusive circuit modules in the circuit module;

[0028] The first building module is used to establish the connection relationship between module point objects and construct the first mathematical model G1;

[0029] The second building module is used to build the second mathematical model G2 based on the first mathematical model G1;

[0030] The third construction module labels the second mathematical model G2 based on the Welsh-Powell algorithm to construct the third mathematical model G3;

[0031] The layout module is used to lay out the circuit to be laid out based on the third mathematical model G3.

[0032] This disclosure also provides an electronic device, including:

[0033] Memory, processor, and computer programs stored in memory and executable on the processor, wherein,

[0034] When the processor executes the program, it implements the method described in any of the preceding methods.

[0035] This disclosure also provides a computer storage medium storing computer-executable instructions for performing any of the methods described above.

[0036] Compared with the prior art, the beneficial effects of this disclosure are as follows:

[0037] 1. The method described in this disclosure is based on the Welsh-Powell algorithm to obtain a better PCB layout structure, which can effectively improve the efficiency and accuracy of PCB design and save the cost of IC testing.

[0038] 2. The method described in this disclosure prioritizes each circuit module according to the amount of data transmitted, thereby ensuring that the transmission path of high-speed signals is as short as possible, avoiding signal distortion and crosstalk caused by excessively long lines, thus achieving the optimal data transmission effect of the circuit and avoiding data transmission bottleneck problems. Attached Figure Description

[0039] Figure 1 This is a flowchart of a circuit layout method based on the Welsh-Powell algorithm provided in one embodiment of this disclosure;

[0040] Figure 2 This is a schematic diagram of the first mathematical model G1;

[0041] Figure 3 This is a schematic diagram of the second mathematical model G2;

[0042] Figure 4 This is a schematic diagram of the third mathematical model, G3;

[0043] Figure 5 Based on Figure 1 The diagram shows a single-layer, region-based layout of the Loadboard circuit using the method shown.

[0044] Figure 6 Based on Figure 1 The diagram shows a layered layout of the Loadboard circuitry as described above.

[0045] Figure 7 This is a schematic diagram of the Loadboard circuit layout based on the signal flow layout method.

[0046] Figure 8 This is a schematic diagram showing the layout of the Loadboard circuit based on the star topology layout method;

[0047] Figure 9 This is a schematic diagram of the layered layout of the Loadboard circuit based on the signal flow layout method. Detailed Implementation

[0048] The following will refer to Figures 1 to 9Specific embodiments of this disclosure are described in detail. While specific embodiments of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0049] It should be noted that certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that different terms may be used to refer to the same component. This specification and claims do not distinguish components based on differences in terminology, but rather on differences in function. The terms "comprising" or "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." The following descriptions are preferred embodiments for carrying out this disclosure; however, these descriptions are for the purpose of understanding the general principles of the specification and are not intended to limit the scope of this disclosure. The scope of protection of this disclosure is determined by the appended claims.

[0050] To facilitate understanding of the embodiments of this disclosure, further explanations and descriptions will be provided below with reference to the accompanying drawings and specific embodiments. The accompanying drawings do not constitute a limitation on the embodiments of this disclosure.

[0051] In one embodiment, such as Figure 1 As shown, this disclosure provides a circuit placement method based on the Welsh-Powell algorithm, including the following steps:

[0052] S100: Divide the circuit to be laid out into modules according to its functions to obtain the circuit modules to be laid out.

[0053] In this step, taking the SOC chip test Loadboard circuit as an example, the Loadboard circuit is specifically divided into clock circuit module A, power amplifier circuit module B, analog circuit module C, digital circuit module D, low frequency circuit module E, high frequency circuit module F, filter circuit module G, power supply module H, logic circuit module I, SOC core chip J, memory chip K, and ADC / DAC circuit module L according to function.

[0054] It should be noted that the above module division is only for the Loadboard circuit and is intended to provide an illustrative example of this solution. For other more complex circuits, the module division is not limited to the above method and can be extended to include many other modules.

[0055] S200: Set module point objects according to the circuit to be laid out, from module A to module I;

[0056] In this step, since the Welsh-Powell algorithm subsequently used in this disclosure only applies to circuit modules with mutual exclusion relationships (i.e., only to modules A to I with mutual exclusion relationships), and there are no mutual exclusion relationships between the aforementioned SOC core chip J, memory chip K, and ADC / DAC circuit module L, or with other circuit modules, when using the Welsh-Powell algorithm to construct the mathematical model, it is not necessary to include the SOC core chip J, memory chip K, and ADC / DAC circuit module L in the calculation process (the division of the SOC core chip J, memory chip K, and ADC / DAC circuit module L is only to make the final circuit layout more complete).

[0057] Based on the above, this disclosure only lists the point objects from module A to module I, specifically represented as follows:

[0058] A→a, B→b, C→c, D→d, E→e, F→f, G→g, H→h, I→i, where A to I represent the partitioned modules, and a to i represent the module point objects corresponding to modules A to I respectively.

[0059] S300: Based on the module mutual exclusion rule, establish the connection relationship between module point objects a and i and construct the first mathematical model G1;

[0060] In this step, the digital circuit operates in a high-speed pulse state. Due to the large instantaneous surge current, it will generate high-frequency interference to the DC voltage, which will in turn affect the normal operation of the small-signal analog circuit. Therefore, it is generally necessary to separate the analog power supply and the digital power supply, and the digital ground and the analog ground only share a common ground at their respective busbars, so as to minimize the interference.

[0061] Taking the Loadboard circuit given above as an example, its divided clock circuit module A, power amplifier circuit module B, etc. are mostly interference circuits, while low frequency circuit module E, filter circuit module G, etc. are mostly sensitive circuits. In order to avoid interference from the interference circuits to the sensitive circuits, the interference circuits and sensitive circuits need to be laid out separately.

[0062] Regarding the aforementioned division of modules A to I, in establishing the connection relationships between module point objects a to i, modules with mutual exclusion relationships need to be placed separately. For example, if there is a mutual exclusion relationship between module A and module C (i.e., there is mutual interference between module A and module C, and similar for other modules), then module A and module C need to be placed separately. Furthermore, based on the rules set in this embodiment, when two modules have a mutual exclusion relationship, the corresponding point objects of the two modules are connected by edges. Therefore, since module A and module C are mutually exclusive, according to the rules, it is necessary to connect point object a corresponding to module A and point object c corresponding to module C, thereby indicating that module A and module C have a mutual exclusion relationship. Specifically, for the Loadboard circuit, the specific layout of the divided modules A to I is as follows:

[0063] Clock circuit module A and analog circuit module C are placed separately;

[0064] Clock circuit module A and low-frequency circuit module E are laid out separately;

[0065] Clock circuit module A and filter circuit module G are laid out separately;

[0066] The clock circuit module A and the power supply circuit module H are laid out separately.

[0067] The power amplifier circuit module B and the analog circuit module C are laid out separately;

[0068] The power amplifier circuit module B and the low-frequency circuit module E are laid out separately.

[0069] The power amplifier circuit module B and the filter circuit module G are laid out separately.

[0070] The power amplifier circuit module B and the power supply circuit module H are laid out separately.

[0071] Analog circuit module C and digital circuit module D are placed separately;

[0072] The analog circuit module C and the high-frequency circuit module F are laid out separately;

[0073] The analog circuit module C and the power supply circuit module H are laid out separately;

[0074] Analog circuit module C is placed separately from logic circuit module I;

[0075] Digital circuit module D and power supply circuit module H are laid out separately;

[0076] Digital circuit module D and logic circuit module I are laid out separately;

[0077] The low-frequency circuit module E and the high-frequency circuit module F are laid out separately.

[0078] The high-frequency circuit module F and the power supply circuit module H are laid out separately.

[0079] After completing the placement of modules A to I as shown above, the connection relationship between point objects a to i established according to the above rules (i.e., connecting the corresponding point objects between mutually exclusive modules) is as follows:

[0080] Connect edge a and c;

[0081] Connect edge a and e;

[0082] Connect edge a to g;

[0083] Connect edge a to h;

[0084] Connect edge b to edge c;

[0085] Connect edge b to edge e;

[0086] Connect b and g with an edge;

[0087] Connect b and h with an edge;

[0088] Connect c and d with an edge;

[0089] Connect c and f with an edge;

[0090] Connect c and h with an edge;

[0091] Connect c to i with an edge;

[0092] Connect d and h with an edge;

[0093] Connect d and i with an edge;

[0094] Connect e and f with an edge;

[0095] Connect f and h with an edge.

[0096] Once the connection relationship between point objects a and i is clarified, a structure like this can be constructed. Figure 2 The first mathematical model G1 is shown.

[0097] S400: Construct a second mathematical model G2 based on the first mathematical model G1;

[0098] In this step, after obtaining such Figure 2 After obtaining the first mathematical model G1, the second mathematical model G2 can be constructed by performing the following steps:

[0099] 1. Calculate the degree of module point objects a to i in G1, that is, the number of edges connecting each module point object a to i to the other module point objects, denoted as d. Then we have:

[0100] d(a) = 4;

[0101] d(b) = 4;

[0102] d(c) = 6;

[0103] d(d) = 3;

[0104] d(e) = 3;

[0105] d(f) = 3;

[0106] d(g) = 2;

[0107] d(h) = 5;

[0108] d(i) = 2.

[0109] 2. Sort the degree values ​​of module point objects a to i, then:

[0110] d(c)≥d(h)≥d(a)≥d(b)≥d(d)≥d(e)≥d(f)≥d(g)≥d(i).

[0111] 3. Redefine module point objects a to i according to the above sorting, that is:

[0112] v1 = c

[0113] v2 = h

[0114] v3 = a

[0115] v4=b

[0116] v5=d

[0117] v6 = e

[0118] v7=f

[0119] v8=g

[0120] v9=i

[0121] Among them, point object c has the most connected edges, and is numbered v1; point object i has the fewest connected edges, and is numbered v9.

[0122] 4. Construct the following based on the redefined point objects a to i: Figure 3 The second mathematical model G2 is shown.

[0123] S500: The second mathematical model G2 is labeled based on the Welsh-Powell algorithm to construct the third mathematical model G3;

[0124] In this step, this embodiment uses the Welsh-Powell algorithm to process, for example... Figure 3 The redefined point objects a to i in the second mathematical model G2 shown are labeled. Before the specific labeling, it is necessary to first set:

[0125] Number V = {v1, v2, v3, ..., v9};

[0126] The label set C = {1, 2, 3, ..., Δ(G)+1} = {①, ②, ③, ..., ⑦};

[0127] Label the function π(x): x = {v1, v2, v3, ..., v9};

[0128] The specific marking process is as follows:

[0129] 1. Let π(v1) = 1, i = 1 (mark v1 with ①);

[0130] v2 is associated with v1. v2 cannot be labeled with ①. C((v2)) = {①}. The set of labels that v2 can be labeled is: C\C(v2) = {②, ③, ..., ⑦}.

[0131] 2. Let π(v2) = 2, and mark v2 with symbol ②;

[0132] v3 is associated with v1 and v2, so the labels used by v1 and v2 cannot be used to label v3. C((v3)) = {①, ②}; the set of labels available for v3 is: C\C(v3) = {③, ..., ⑦};

[0133] 3. Let π(v3) = 3, and mark v3 with the symbol ③;

[0134] v4 is associated with v1 and v2, so the labels used by v1 and v2 cannot be used to label v4. C((v4)) = {①, ②}; the set of labels available for v4 is: C\C(v4) = {③, ..., ⑦};

[0135] 4. Let π(v4) = 3, and mark v4 with the symbol ③;

[0136] v5 is associated with v1 and v2, so the labels used by v1 and v2 cannot be used to label v5. C((v5)) = {①, ②}; the set of labels available for v5 is: C\C(v5) = {③, ..., ⑦};

[0137] 5. Let π(v5) = 3, and mark v5 with symbol ③;

[0138] v6 is associated with v3 and v4, so the labels used by v3 and v4 cannot be used to label v6. C((v6)) = {③}; the set of labels available for v6 is: C\C(v6) = {①, ②, ④, ..., ⑦};

[0139] 6. Let π(v6) = 1, and mark v6 with ①;

[0140] v7 is associated with v1, v2, and v6, so the labels used by v1, v2, and v6 cannot be used to label v7. C((v7)) = {①, ②}; the set of labels available for v7 is: C\C(v7) = {③, ..., ⑦};

[0141] 7. Let π(v7) = 3, and mark v7 with the symbol ③;

[0142] v8 is associated with v3 and v4, so the labels used by v3 and v4 cannot be used to label v8. C((v8)) = {③}; the set of labels available for v8 is: C\C(v8) = {①, ②, ④, ..., ⑦};

[0143] 8. Let π(v8) = 1, and mark v8 with ①;

[0144] v9 is associated with v1 and v5, so the labels used by v1 and v5 cannot be used to label v9. C((v9)) = {①, ③}; the set of labels available for v9 is: C\C(v8) = {②, ④, ..., ⑦};

[0145] 9. Let π(v9) = 2, and mark v9 with symbol ②.

[0146] It should be noted that the labeling process shown in 1-9 above is to simplify the programming difficulty of the algorithm and to simplify the constructed mathematical model, making the constructed mathematical model as concise and intuitive as possible, and avoiding errors made by developers when constructing the mathematical model. Therefore, this method labels the number corresponding to each point object according to the minimum label. For example, the set of available labels for v2 is: C\C(v2)={②,③,…,⑦}, where ② is the minimum label, so v2 is labeled as label ②.

[0147] After completing the above marking process, you can obtain the following: Figure 4 The third mathematical model G3 is shown after the labeling.

[0148] Step S600: Layout the circuit to be laid out based on the third mathematical model G3.

[0149] In this step, by Figure 4 It is known that to ensure that the two vertices of any edge in the third mathematical model G3 are labeled with different numbers, at least three different labels are needed. Mapped to the PCB layout, under the constraints given above, to ensure that each module is laid out separately and does not interfere with each other, the PCB board must be divided into at least three regions (region division is for single-layer layout of modules A to I). The specific layout process is as follows:

[0150] The PCB substrate is divided into three regions based on the labels (v1 to v9 are labeled 1, 2, and 3), denoted as Region 1, Region 2, and Region 3 respectively. The region priority is set as: Region 1 > Region 2 > Region 3. It should be noted that the closer a module is to the SOC core chip J, the higher its corresponding region's priority. For details on the priority, please refer to Table 1.

[0151] Table 1

[0152]

[0153] After determining the area priorities as shown in Table 1, circuit modules with the same labels are placed into their corresponding areas according to G3 (for example, in G3, if v1 is labeled ①, then the analog circuit module C corresponding to v1 is placed in area ①). This initially achieves the goal of ensuring that each circuit module does not interfere with the others with minimal partitioning conditions. Furthermore, in each of the partitioned areas, the modules can also be prioritized (the larger the amount of data a module transmits, the higher its priority). For example, in area ①, the memory chip K has the highest priority and is defined as the first priority; the ADC / DAC circuit module L and the logic circuit module I are defined as the second priority, and the power supply module H is defined as the third priority. Prioritizing based on the amount of data transmitted ensures that high-priority circuit modules are allocated to the best layout positions, thereby achieving optimal data transmission performance. The final PCB layout result obtained based on the above layout process is as follows: Figure 5 As shown.

[0154] Furthermore, this disclosure employs existing signal flow-based layout methods to lay out the aforementioned Loadboard circuit, and the layout result is as follows: Figure 7 As shown. By comparison Figure 5 and Figure 7 It is known that when dealing with complex circuits with many circuit modules, the signal flow layout method cannot guarantee that all critical signal traces are the shortest possible in order to avoid the interleaving and interference between the circuit modules, thus greatly reducing the actual data transmission rate of the overall circuit.

[0155] This disclosure also employs an existing star topology layout method to lay out the aforementioned Loadboard circuit, and the layout result is as follows: Figure 8 As shown, by comparison Figure 5 and Figure 8 As can be seen, the star topology layout revolves around the SOC core chip J, with the circuit modules positioned relatively dispersed, resulting in complex PCB routing. Shielding measures are necessary for critical signal lines to prevent signal distortion and crosstalk. Furthermore, circuit impedance is difficult to control, requiring signal matching design at the receiving end to eliminate terminal reflections.

[0156] Furthermore, this embodiment can also implement a layered layout for modules A to I. Under the constraints given by the single-layer layout above, in order to ensure that each module is laid out separately and does not interfere with each other, the PCB board signal layer must be divided into at least 3 layers. The specific layout process is as follows:

[0157] The PCB substrate is divided into 3 layers according to the labels (v1 to v9 are labeled with 3 labels, namely label ①, label ② and label ③), which are respectively labeled as signal layer ①, signal layer ② and signal layer ③. The priority of the signal layers is set as: signal layer ① > signal layer ② > signal layer ③ (the closer to the SOC core chip, the higher the priority of the corresponding layer). Then, according to G3, the circuit modules with the same label are placed into the corresponding layer (for example, in G3, v1 is labeled ①, so the analog circuit module C corresponding to v1 is placed in signal layer ①). In this way, the initial goal of ensuring that the circuit modules do not interfere with each other with the fewest partition conditions is achieved. Furthermore, within each layer after partitioning, modules can also be prioritized (the larger the amount of data a module transmits, the higher its priority). For example, in signal layer ①, the memory chip K has the highest priority and is defined as the first priority; the ADC / DAC circuit module L and the logic circuit module I are defined as the second priority, and the power supply module H is defined as the third priority. Prioritizing modules based on the amount of data transmitted ensures that high-priority circuit modules are allocated to the best layout positions, thereby achieving optimal data transmission performance. The final PCB layout result obtained based on the above layout process is as follows: Figure 6 As shown.

[0158] Figure 9 This is a schematic diagram illustrating the layered layout of the Loadboard circuit described above, based on a signal flow-oriented layout method. Figure 9 As shown, this layout maximizes the separation of circuit modules and minimizes inter-module interference, enabling the handling of more complex functions and providing greater power, operational capability, and speed. However, compared to... Figure 6 compared to, Figure 9 The number of signal layers in the circuit increases several times, which makes production more complex, increases design costs and production cycles, and makes subsequent maintenance of the circuit board more complicated.

[0159] It should be noted that, Figure 6 and Figure 9The PCB layout diagram of the corresponding Loadboard circuit only shows the layout of the signal layer. In actual multilayer board circuit PCB design, it is also necessary to consider the internal power layer, silkscreen layer, mechanical layer, solder mask layer and keep-away layer, etc. However, most of the circuit modules involved in this disclosure are set on the signal layer of the multilayer board PCB structure. Therefore, this disclosure only describes the layout of the signal layer. The layout of other layers is not included in the scope of this disclosure and is therefore not described or explained.

[0160] The above describes a circuit layout method based on the Welsh-Powell algorithm. This method eliminates circuit modules without mutual exclusion before circuit layout and only lays out circuit modules with mutual exclusion, thereby constructing a feasible and optimal layout model. Compared with existing layout methods, it simplifies the difficulty of circuit layout, avoids blind layout errors, and achieves both efficiency and cost benefits.

[0161] In another embodiment, this disclosure also provides a circuit layout apparatus based on the Welsh-Powell algorithm, comprising:

[0162] The module division is used to divide the circuit to be laid out into modules to obtain the circuit modules of the circuit to be laid out.

[0163] A setting module is used to set module point objects based on the mutually exclusive circuit modules in the circuit module;

[0164] The first building module is used to establish the connection relationship between module point objects and construct the first mathematical model G1;

[0165] The second building module is used to build the second mathematical model G2 based on the first mathematical model G1;

[0166] The third construction module labels the second mathematical model G2 based on the Welsh-Powell algorithm to construct the third mathematical model G3;

[0167] The layout module is used to lay out the circuit to be laid out based on the third mathematical model G3.

[0168] In another embodiment, this disclosure also provides an electronic device, including:

[0169] Memory, processor, and computer programs stored in memory and executable on the processor, wherein,

[0170] When the processor executes the program, it implements the method described in any of the preceding methods.

[0171] In another embodiment, this disclosure also provides a computer storage medium storing computer-executable instructions for performing any of the methods described above.

[0172] This disclosure provides a detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred examples of the present invention and are not limited to the specific embodiments described above. The detailed description is intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of this disclosure. On the contrary, any improvements or modifications made based on the inventive spirit of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A circuit placement method based on the Welsh-Powell algorithm, comprising the following steps: S100: Divide the circuit to be laid out into modules to obtain the circuit modules of the circuit to be laid out; S200: Set module point objects according to the circuit modules that have mutual exclusion relationships in the circuit modules; S300: Establish the connection relationship between module point objects and construct the first mathematical model G1; S400: Construct a second mathematical model G2 based on the first mathematical model G1; S5 00: The second mathematical model G2 is labeled based on the Welsh-Powell algorithm to construct the third mathematical model G3; S600: Layouts the circuit to be laid out based on the third mathematical model G3; Step S300 includes the following steps: S301: Arrange the modules separately according to the mutual exclusion relationship between them; S302: Connect the module point objects corresponding to mutually exclusive modules to obtain the first mathematical model G1; Step S400 includes the following steps: S401: Calculate the degree of each module point object in the first mathematical model G1. d ; S402: Degree of each module point object d The module point objects are sorted and redefined based on the sorting results. The redefined module point objects are represented as follows: V ={ v 1 ，v 2 ，v 3 ，… ，v i }, i Indicates the number of module point objects; S403: Construct a second mathematical model G2 based on the redefined point objects of each module.

2. The method according to claim 1, wherein, In step S100, the circuit to be laid out is divided into modules according to its functions.

3. The method according to claim 1, wherein, In step S500, the second mathematical model G2 is labeled using the following method: S501: Set the flag function π(x): x={v 1 ，v 2 ，v 3 ，… ，v i }，i Indicates the number of module point objects; S502: Based on the association relationships between the redefined module point objects and based on the tagging function. π(x) Mark the point objects of each module.

4. The method according to claim 3, wherein, In step S600, the layout of the circuit to be laid out based on the third mathematical model G3 includes: dividing the single-layer PCB board into regions according to the markings of the module point objects in the third mathematical model G3, sorting the regions by priority, and placing the modules with the same markings in G3 into the corresponding regions.

5. The method according to claim 3, wherein, In step S600, the layout of the circuit to be laid out based on the third mathematical model G3 further includes: dividing the PCB board into corresponding signal layers according to the markings of the module point objects in the third mathematical model G3, prioritizing the divided signal layers, and placing modules with the same markings in G3 into the corresponding signal layers.

6. A circuit layout apparatus based on the Welsh-Powell algorithm, comprising: The module division is used to divide the circuit to be laid out into modules to obtain the circuit modules of the circuit to be laid out. A setting module is used to set module point objects based on the mutually exclusive circuit modules in the circuit module; The first building module is used to establish the connection relationship between module point objects and construct the first mathematical model G1; The second building module is used to build the second mathematical model G2 based on the first mathematical model G1; The third construction module labels the second mathematical model G2 based on the Welsh-Powell algorithm to construct the third mathematical model G3; The layout module is used to lay out the circuit to be laid out based on the third mathematical model G3. Specifically, the first building module includes: Used to separate and deploy modules according to the mutual exclusion relationship between modules; This is used to connect the module point objects corresponding to mutually exclusive modules, thus obtaining the first mathematical model G1. The second building module specifically includes: Used to calculate the degree of each module point object in the first mathematical model G1 d ; Degrees used to measure the points of each module. d The module point objects are sorted and redefined based on the sorting results. The redefined module point objects are represented as follows: V ={ v 1 ，v 2 ，v 3 ，… ，v i }, i Indicates the number of module point objects; Used to construct a second mathematical model G2 based on the redefined module point objects.

7. An electronic device, comprising: Memory, processor, and computer programs stored in memory and executable on the processor, wherein, When the processor executes the program, it implements the method according to any one of claims 1 to 5.

8. A computer storage medium storing computer-executable instructions for performing the method of any one of claims 1 to 5.

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