A method for connecting TLM ports between UVM components

Abstract

The present application relates to the field of digital chip verification, and particularly relates to a TLM port connection method between UVM components, comprising the following steps: S1) creating a class; S2) defining class attributes; S3) establishing function1, which is used for adding a TLM port to a library; S4) establishing function2; S5) instantiating the class in a parent node, and sending a TLM port pointer to a child node; S6) obtaining the pointer and calling function1; S7) calling function2 in the parent node to realize TLM port connection. The present application solves the problems of incorrect connection of child nodes and great difficulty in code reading caused by the digital chip verification platform in the prior art, and can improve verification efficiency and reduce workload.

Description

Technical Field

[0001] This invention relates to the field of digital chip verification, and more specifically to a method for connecting TLM ports between UVM components. Background Technology

[0002] In the development of application-specific integrated circuits (ASICs), chip functional verification is a crucial process. Technological advancements have led to an exponential increase in chip complexity, resulting in a corresponding increase in the number of components in chip verification platforms. This, in turn, places higher demands on the efficiency and reusability of these platforms.

[0003] Currently, UVM (Universal Verification Methodology) has become the mainstream verification methodology due to its advantages such as high flexibility, high reusability, and high standardization. Typically, UVM components communicate with each other through TLM (Transaction Level Modeling). UVM components have several built-in methods or classes, such as `uvm_config_db` and `uvm_port_base`. The specific connection method for UVM components is that the connection between child UVM components is made within the parent node's UVM component. This connection method is highly efficient in verification platforms with simple hierarchical structures, but in complex system-on-a-chip or subsystem verification environments, misconnections can occur, increasing the difficulty of code reading. On the one hand, when UVM components connect ports, they often need to connect to different parent nodes. If a parent node has too many TLM ports, misconnections will occur. On the other hand, complex verification platforms require multiple people to build and maintain them; staff need to understand the communication methods between UVM components in different parent nodes and need to read a large amount of code.

[0004] As mentioned above, the TLM port connection method between UVM components commonly used in the prior art increases the difficulty of building and maintaining the digital chip verification platform and reduces the chip verification efficiency. Summary of the Invention

[0005] This invention provides a method for connecting TLM ports between UVM components, which solves the problems of incorrect connection of child nodes and difficulty in reading code caused by digital chip verification platforms in the prior art.

[0006] The technical solution of the present invention is as follows: A method for connecting TLM ports between UVM components includes the following steps: S1) Create a new class.

[0007] S2) Define member variables in the class, which are of type uvm_port_base. In uvm_port_base, all TLM ports in UVM are subclasses of uvm_port_base, so that uvm_port_base can store TLM ports of various types.

[0008] S3) Create a function function1 in the class; function1 contains a pointer to the TLM port to be connected, the parent node of the TLM port pointer to be connected, the type of the TLM port to be connected, and a label.

[0009] S4) In the class, a function function2 is created. The function2 connects each TLM by polling the parent node of the TLM port pointer to be connected in the library of type uvm_port_base, the type of the TLM port to be connected, and the label parameter.

[0010] S5) Instantiate the class in the parent node and send the pointer of the TLM port to be connected to each child node of the parent node through uvm_config_db.

[0011] S6) Obtain the TLM port pointer to be connected through uvm_config_db in each child node and the node of each child node. After each child node issues a TLM port connection request and the TLM port is instantiated, call function1 and pass the TLM port pointer to be connected, the parent node of the TLM port pointer to be connected, the TLM port type to be connected, and the tag parameter to the TLM port. S7) Call function2 in the parent node to complete the automatic connection of the TLM port.

[0012] Furthermore, the TLM port type to be connected includes initiator and receiver, and the TLM port type is used to determine the connection direction of the TLM port.

[0013] Furthermore, the tag is used to identify TLM ports with a connection relationship. When the tag is passed to the TLM port in step S6), the tags of TLM ports with a connection relationship have the same characters and different characters.

[0014] Due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. This application can efficiently connect TLM ports between UVM components, which helps reduce the phenomenon of misconnection of child nodes caused by digital chip verification platforms.

[0015] 2. The solution provided in this application is simple and clear, which can significantly reduce the workload required to maintain the verification platform and significantly reduce the workload when viewing the connection relationship between ports; 3. This application has a high degree of generality. Its class for automatically connecting to the TLM port can be reused in different UVM verification platforms without modification. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A schematic diagram of the complex verification platform architecture; Figure 2 This application provides a flowchart of a method for connecting TLM ports between UVM components. Detailed Implementation

[0017] As attached Figure 1 As shown, attached Figure 1 This illustrates a relatively complex chip verification platform architecture, with attached... Figure 1 In this verification architecture, multiple components are involved. Using the traditional TLM port connection method, connections between A1 and A2 need to be made in component A, B1, B2, B3, and B4 need to be made in component A1, and C1, C2, C3, and C4 need to be made in component A2. This increases the complexity of connecting TLM ports in the entire verification architecture. Using the method provided in this solution, all TLM ports are connected within component A, which is the parent node. Child nodes under A, and their sub-nodes, only need to place their port pointers in a library that can hold TLM ports. The specific method in this embodiment is as follows: A method for connecting TLM ports between UVM components includes the following steps: S1) Create a new class and name it class P. S2) Define class P as a library with class attribute uvm_port_base. In uvm_port_base, all TLM ports in UVM are subclasses of uvm_port_base, so that uvm_port_base can store various types of TLM ports.

[0018] S3) Create a class function1; function1 contains a pointer to the TLM port to be connected, the parent node of the pointer to the TLM port to be connected, the type of the TLM port to be connected, and a label; the type of the TLM port to be connected includes the initiator and the receiver, and the TLM port type is used to determine the connection direction of the TLM port.

[0019] S4) Create class function2. function2 connects each TLM by polling the parent node of the TLM port pointer to be connected in the library of uvm_port_base, the type of the TLM port to be connected, and the label parameter.

[0020] S5) Instantiate class P in the parent node and send the pointers to the TLM ports to be connected to each child node of the parent node through uvm_config_db.

[0021] S6) In each child node and within each child node's node, the pointer to the TLM port to be connected is obtained through uvm_config_db. After each child node issues a TLM port connection request and the TLM port is instantiated, function1 is called and the TLM port pointer to be connected, the parent node of the TLM port pointer to be connected, the type of the TLM port to be connected, and the tag parameter are passed to the TLM port. The tag is used to identify TLM ports with a connection relationship. In this step, when passing the tag to the TLM port, the tags of TLM ports with a connection relationship have the same characters and different characters. That is, the tags with a connection relationship need to have the same characters but cannot be completely identical to avoid the occurrence of port pointers with the same tag in the library and mutual overwriting. In specific implementation, the tag of the receiver on the TLM port can be set to its initiator tag plus any suffix.

[0022] S7) Call function2 in the parent node. function2 polls the parent node of the TLM port pointer to be connected in the library of uvm_port_base, the type of the TLM port to be connected, and the label parameters to connect each TLM.

[0023] The above description is merely the basic principle and preferred embodiment of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention are within the scope of protection of the present invention.

Claims

1. A method for connecting TLM ports between UVM components, characterized in that, Includes the following steps: S1) Create a new class; S2) Define member variables in the class, the type of which is uvm_port_base. In uvm_port_base, all TLM ports in UVM are subclasses of uvm_port_base, so that uvm_port_base can store TLM ports of various types. S3) Create a function function1 in the class; function1 contains a pointer to the TLM port to be connected, the parent node of the TLM port pointer to be connected, the type of the TLM port to be connected, and a label, the label being used to identify TLM ports with a connection relationship; S4) In the class, a function function2 is created. The function2 connects each TLM by polling the parent node of the TLM port pointer to be connected in the library of type uvm_port_base, the type of the TLM port to be connected, and the label. S5) Instantiate the class in the parent node and send the pointer to the TLM port to be connected to each child node of the parent node through uvm_config_db; S6) Obtain the TLM port pointer to be connected through uvm_config_db in each child node and the node of each child node. After each child node issues a TLM port connection request and the TLM port is instantiated, call function1 and pass the TLM port pointer to be connected, the parent node of the TLM port pointer to be connected, the TLM port type to be connected, and the label to be passed to the TLM port. S7) Call function2 in the parent node to complete the automatic connection of the TLM port.

2. The method for connecting TLM ports between UVM components according to claim 1, characterized in that, The TLM port type to be connected includes initiator and receiver, and the TLM port type is used to determine the connection direction of the TLM port.

3. The method for connecting TLM ports between UVM components according to claim 1, characterized in that, When a tag is passed to a TLM port in step S6), tags on TLM ports with connection relationships have the same characters and different characters.

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