Frame control device, method, display system, electronic device, and storage medium

Abstract

The application provides a frame control device, method, display system, electronic equipment and storage medium. The device comprises a display interface module, which comprises first to third buffers; a frame processing module is used for performing rendering on an Nth image comprising an Nth left eye frame and an Nth right eye frame in an Mth Vsync cycle; if layer synthesis of the Nth left eye frame is performed in an M+1th Vsync cycle, then in an M+2th Vsync cycle, the frame processing module is used for performing rendering on an N+1th image comprising an N+1th left eye frame and an N+1th right eye frame, performing layer synthesis of the Nth right eye frame, and sending the Nth left eye frame into the first buffer; in an M+3th Vsync cycle, the frame processing module is used for performing layer synthesis of the N+1th left eye frame and sending the Nth right eye frame into the second buffer; and in an M+4th Vsync cycle, the frame processing module is used for performing rendering on an N+2th image, performing layer synthesis of the N+1th right eye frame, sending the N+1th left eye frame into the third buffer, and outputting the Nth left eye frame in the first buffer to a display screen, so as to output a stable left and right eye alternating frame sequence.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a frame control device, method, display system, electronic device, and storage medium. Background Technology

[0002] The display pipeline of a display system mainly includes three processes: application rendering, layer compositing, and hardware delivery to the display (i.e., writing to the buffer). To avoid display stuttering and improve the visual performance of graphics, the display system uses vertical synchronization (Vsync) signals to synchronize the various processes in the display pipeline. A key requirement for achieving 3D display is to form a stable frame sequence that alternates between the left and right images. However, an unstable Vsync period (e.g., timeouts) will cause the DSI (Display Pixel Interface) to fail to output a stable alternating frame sequence for the left and right eyes. Summary of the Invention

[0003] This invention provides a frame control device, method, display system, electronic device, and storage medium to solve the problem in the prior art where the DSI cannot output a stable alternating left and right eye frame sequence due to the instability of the Vsync period.

[0004] In a first aspect, the present invention provides a frame control device, the device comprising:

[0005] The display interface module includes a first buffer, a second buffer, and a third buffer;

[0006] The frame processing module is used to perform application rendering in the Mth Vsync cycle to render the Nth image, which includes the Nth left-eye frame and the Nth right-eye frame;

[0007] If the layer composition of the Nth left-eye frame is performed in the (M+1)th Vsync cycle, then

[0008] The application rendering is performed in the M+2 Vsync cycle, including the N+1th image of the N+1th left eye frame and the N+1th right eye frame, performing layer compositing of the Nth right eye frame, and feeding the Nth left eye frame into the first buffer;

[0009] In the M+3 Vsync cycle, the layer composition of the N+1 left eye frame is performed and the Nth right eye frame is sent into the second buffer;

[0010] In the M+4th Vsync cycle, the application rendering is performed, including the N+2th image of the N+2th left eye frame and the N+2th right eye frame, the layer composition of the N+1th right eye frame is performed, and the N+1th left eye frame is sent to the third buffer, while the Nth left eye frame in the first buffer is output to the display screen.

[0011] Where M and N are both positive integers.

[0012] In one embodiment of the present invention, the frame processing module is further configured to:

[0013] In the M+5th Vsync cycle, the layer composition of the N+2th left eye frame is performed and the N+1th right eye frame is sent to the first buffer, while the Nth right eye frame in the second buffer is output to the display screen.

[0014] In the M+6th Vsync cycle, the application rendering is performed, including the N+3rd image of the N+3rd left eye frame and the N+3rd right eye frame, the layer composition of the N+2nd right eye frame is performed, and the N+2nd left eye frame is sent to the second buffer, while the N+1th left eye frame in the third buffer is output to the display screen.

[0015] In the M+7th Vsync cycle, the layer composition of the N+3rd left eye frame is performed and the N+2nd right eye frame is sent to the third buffer, while the N+1th right eye frame in the first buffer is output to the display screen.

[0016] In one embodiment of the present invention, each Vsync period is a preset value. Assuming the (M+8th)th Vsync period is greater than the preset value, then before the (M+8th)th Vsync period arrives, the frame processing module is further configured to:

[0017] The (N+2)th left-eye frame in the second buffer is output to the display screen.

[0018] In one embodiment of the present invention, the frame processing module is further configured to:

[0019] In the M+8th Vsync cycle, the application rendering is performed, including the N+4th image of the N+4th left eye frame and the N+4th right eye frame, the layer composition of the N+3rd right eye frame is performed, and the N+3rd left eye frame is sent to the first buffer, while the N+2th right eye frame in the third buffer is output to the display screen.

[0020] In one embodiment of the present invention, the device further includes:

[0021] Fourth buffer;

[0022] The frame processing module is also used for:

[0023] When the (M+5)th Vsync cycle is less than a preset Vsync cycle value, the layer compositing of the (N+2)th left eye frame is performed and the (N+1)th right eye frame is sent to the fourth buffer during the (M+5)th Vsync cycle.

[0024] Secondly, the present invention also provides a frame control method, the method comprising:

[0025] The application renders the Nth image, which includes the Nth left-eye frame and the Nth right-eye frame, during the Mth Vsync cycle.

[0026] If the layer composition of the Nth left-eye frame is performed in the (M+1)th Vsync cycle, then

[0027] The application rendering is performed in the M+2 Vsync cycle, including the N+1th image of the N+1th left eye frame and the N+1th right eye frame, performing layer compositing of the Nth right eye frame, and feeding the Nth left eye frame into the first buffer;

[0028] In the M+3 Vsync cycle, the layer composition of the N+1 left eye frame is performed and the Nth right eye frame is fed into the second buffer;

[0029] In the M+4th Vsync cycle, the application rendering is performed, including the N+2th image of the N+2th left eye frame and the N+2th right eye frame, the layer composition of the N+1th right eye frame, and the N+1th left eye frame is sent to the third buffer, while the Nth left eye frame in the first buffer is output to the display screen.

[0030] Where M and N are both positive integers.

[0031] In one embodiment of the present invention, the method further includes:

[0032] In the M+5th Vsync cycle, the layer composition of the N+2th left eye frame is performed and the N+1th right eye frame is sent to the first buffer, while the Nth right eye frame in the second buffer is output to the display screen.

[0033] In the M+6th Vsync cycle, the application rendering is performed, including the N+3rd image of the N+3rd left eye frame and the N+3rd right eye frame, the layer composition of the N+2nd right eye frame is performed, and the N+2nd left eye frame is sent to the second buffer, while the N+1th left eye frame in the third buffer is output to the display screen.

[0034] In the M+7th Vsync cycle, the layer composition of the N+3rd left eye frame is performed and the N+2nd right eye frame is sent to the third buffer, while the N+1th right eye frame in the first buffer is output to the display screen.

[0035] In one embodiment of the present invention, each Vsync cycle is a preset value. Assuming the (M+8th)th Vsync cycle is greater than the preset value, the method further includes the following steps before the (M+8th)th Vsync cycle arrives:

[0036] The (N+2)th left-eye frame in the second buffer is output to the display screen.

[0037] In one embodiment of the present invention, the method further includes:

[0038] In the M+8th Vsync cycle, the application rendering is performed, including the N+4th image of the N+4th left eye frame and the N+4th right eye frame, the layer composition of the N+3rd right eye frame is performed, and the N+3rd left eye frame is sent to the first buffer, while the N+2th right eye frame in the third buffer is output to the display screen.

[0039] In one embodiment of the present invention, each Vsync cycle is a preset value. Assuming the (M+5th)th Vsync cycle is less than the preset value, the method further includes:

[0040] In the M+5th Vsync cycle, the layer composition of the N+2th left eye frame is performed and the N+1th right eye frame is fed into the fourth buffer.

[0041] Thirdly, the present invention also provides a display system in which, when displaying a frame sequence of alternating left and right eye images on a display screen, the display system executes the frame control method described in any of the second aspects above.

[0042] Fourthly, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the frame control method as described in any of the second aspects above.

[0043] Fifthly, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the frame control method as described in any of the second aspects above.

[0044] The frame control device, method, display system, electronic device and storage medium provided by the present invention can reserve one more frame buffer by providing at least a first to a third buffer, so that the frame processing module can output a stable left and right eye alternating frame sequence even when the Vsync period is unstable. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the frame control device provided by the present invention;

[0047] Figure 2 This is a schematic diagram of the first Vsync cycle provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the second Vsync cycle provided in an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram of the third Vsync cycle provided in an embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the fourth Vsync cycle provided in an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the 5th Vsync cycle provided in an embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of the 6th Vsync cycle provided in an embodiment of the present invention;

[0053] Figure 8 This is a schematic diagram of the 7th Vsync cycle provided in an embodiment of the present invention;

[0054] Figure 9 This is a schematic diagram of the 8th Vsync cycle provided in an embodiment of the present invention;

[0055] Figure 10 This is a schematic diagram of Vsync cycle timeout provided in an embodiment of the present invention;

[0056] Figure 11 This is a schematic diagram of the 9th Vsync cycle provided in an embodiment of the present invention;

[0057] Figure 12 This is a schematic diagram of the 10th Vsync cycle provided in an embodiment of the present invention;

[0058] Figure 13 This is a schematic diagram of the 11th Vsync cycle provided in an embodiment of the present invention;

[0059] Figure 14This is a schematic diagram of the 12th Vsync cycle provided in an embodiment of the present invention;

[0060] Figure 15 This is a schematic diagram of the 13th Vsync cycle provided in an embodiment of the present invention;

[0061] Figure 16 This is a schematic diagram of Vsync cycle advancement provided in an embodiment of the present invention;

[0062] Figure 17 This is a flowchart illustrating the frame control method provided by the present invention;

[0063] Figure 18 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0065] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein.

[0066] The technical terms involved in this invention are described below:

[0067] The rise of 3D televisions and 3D display devices has brought users a completely new visual experience. The display of 3D images generally employs a parallax barrier system, most commonly divided into naked-eye 3D and glasses-based 3D. Glasses-based 3D is further divided into active and passive glasses. This invention primarily focuses on a 3D display architecture based on a display screen + light valve + glasses.

[0068] Whether active or passive, the principle behind these glasses is to display an alternating sequence of frames showing images for both the left and right eyes on a screen. A light valve is added between the user's eye and the screen, which rotates the angle of the polarized light emitted from the screen. The polarized light after being rotated by the light valve, combined with the orthogonal polarizers on one side of the user's eye, can switch the light on or off for the left or right eye. Ultimately, this creates the effect that the left eye cannot see the image displayed on the screen, and vice versa, thus generating different perspectives for the left and right eyes at the user's end, forming a 3D display.

[0069] Therefore, a key requirement for achieving 3D display is to form a stable frame sequence that alternates between left and right screens. In non-real-time operating systems like Android, the operating efficiency is affected by software scheduling and system load. When the Vsync cycle is unstable, the frame output will also be unstable.

[0070] To address the problem in the prior art where the DSI cannot output a stable alternating left and right eye frame sequence due to the instability of the Vsync period, the frame control device, method, display system, electronic device, and storage medium provided by the present invention can reserve one more frame buffer by providing at least a first to a third buffer, so that the frame processing module can output a stable alternating left and right eye frame sequence even when the Vsync period is unstable.

[0071] The following is combined Figures 1-18 The present invention describes a frame control device, method, display system, electronic device, and storage medium.

[0072] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the frame control device provided by the present invention. A frame control device 100 includes a display interface module (DSI) 110 and a frame processing module 120. The display interface module 110 includes a first buffer (buffer1) 111, a second buffer (buffer2) 112 and a third buffer (buffer3) 113.

[0073] For example, the frame processing module 120 is used to:

[0074] When the application renders the Nth image, which includes the Nth left-eye frame and the Nth right-eye frame, during the Mth (M is a positive integer) Vsync cycle;

[0075] If the layer composition of the Nth left-eye frame is performed in the (M+1)th Vsync cycle, then

[0076] The application rendering is performed in the M+2 Vsync cycle, including the N+1th image of the N+1th left eye frame and the N+1th right eye frame, performing layer compositing of the Nth right eye frame, and feeding the Nth left eye frame into the first buffer;

[0077] In the M+3 Vsync cycle, the layer composition of the N+1 left eye frame is performed and the Nth right eye frame is sent into the second buffer;

[0078] In the M+4th Vsync cycle, the application rendering is performed, including the N+2th image of the N+2th left eye frame and the N+2th right eye frame, the layer composition of the N+1th right eye frame is performed, and the N+1th left eye frame is sent to the third buffer, while the Nth left eye frame in the first buffer is output to the display screen.

[0079] exist Figure 1 In the illustrated architecture, the display interface module 110 has three buffers. When the first buffer 111 outputs a data frame to the MIPI (Mobile Industry Processor Interface) of the display screen for display, the second buffer 112 has already buffered the data frame, and the third buffer 113 is also used to write data frames. Because three buffers reserve one frame for buffering, even if the Vsync cycle times out, there is still data for the next frame in the buffer that can be used for DSI output. Therefore, this invention can maintain a stable frame sequence that alternates between the left and right eyes.

[0080] It should be noted that the write operations of buffers 1 to 3 (first buffer 111 to third buffer 113) are controlled by the Vsync cycle of the frame processing module 120. One frame is written each time a Vsync cycle arrives; theoretically, a Vsync cycle will arrive every preset value (e.g., 8.33ms). The hardware DSI output outputs data strictly according to a preset frequency (e.g., 120Hz) via a hardware clock. When the Vsync cycle times out due to instability, no data will be written to the corresponding buffer, or the writing process will be incomplete. Since the DSI hardware clock needs to output strictly at 120Hz, in existing technologies, the DSI will directly fill in the data from the previous frame.

[0081] For example, when the first buffer 111 is outputting data, there should be a Vsync cycle to write the next frame data to the second buffer 112. However, if the Vsync cycle times out and the second buffer 112 fails to complete the writing of the next frame data within a preset value (e.g., 8.33ms), the DSI in the prior art will continue to output the display data in the first buffer 111 through MIPI, resulting in repeated frames. This makes it impossible to maintain a stable frame sequence that alternates between the left and right eyes, thus affecting the effect of stereoscopic display.

[0082] The process of frame processing described above is described below through specific embodiments.

[0083] Please refer to Figure 2 , Figure 2This is a schematic diagram of the first Vsync cycle provided in an embodiment of the present invention. When M=1 and N=1, the application rendering of the first image is performed in the first Vsync cycle. The first image includes the first left-eye frame and the first right-eye frame.

[0084] It should be noted that when applying the drawing and rendering process, this invention draws the left and right images together, for example, through U3D drawing and rendering, that is, 3D development in Unity software. 3D rendering is the process of generating images based on three-dimensional data stored on a computer.

[0085] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the second Vsync cycle provided in an embodiment of the present invention. Layer compositing of the first left-eye frame is performed in the second Vsync cycle. Although Figure 3 The illustration shows the layer composition of the first left eye frame, but the present invention is not limited to this. In fact, the layer composition of the first right eye frame can also be performed in the second Vsync cycle.

[0086] It should be noted that since the first Vsync cycle has already drawn both the first left-eye frame and the first right-eye frame, therefore... Figure 3 The image was then not rendered.

[0087] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the third Vsync cycle provided in an embodiment of the present invention. In the third Vsync cycle, the application renders and draws the second image, which includes a second left-eye frame and a second right-eye frame. It also performs layer compositing of the first right-eye frame and... Figure 3 The synthesized first left-eye frame is sent to the first buffer.

[0088] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the fourth Vsync cycle provided in an embodiment of the present invention. In the fourth Vsync cycle, layer compositing of the second left-eye frame is performed, and... Figure 4 The synthesized first right-eye frame is sent to the second buffer.

[0089] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the fifth Vsync cycle provided in an embodiment of the present invention. In the fifth Vsync cycle, the application renders the third image, which includes a third left-eye frame and a third right-eye frame. It also performs layer compositing of the second right-eye frame and... Figure 5 The synthesized second left-eye frame is sent to the third buffer, while the first left-eye frame in the first buffer is output to the display screen.

[0090] from Figure 6 It can be seen that the alternating left and right eye frame sequence output to the display screen by the present invention is: the first left eye frame.

[0091] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the 6th Vsync cycle provided in an embodiment of the present invention. In the 6th Vsync cycle, the layer compositing of the 3rd left-eye frame is performed and the 2nd right-eye frame is sent to the first buffer, while the 1st right-eye frame in the second buffer is output to the display screen.

[0092] From the above Figure 6 , Figure 7 It can be seen that, Figure 6 The first left-eye frame is output to the display screen. Figure 7 The first right-eye frame is output to the display screen, thus achieving an alternating frame sequence between the left and right eyes.

[0093] from Figure 7 It can be seen that the alternating left and right eye frame sequence output to the display screen by the present invention is: the first left eye frame - the first right eye frame.

[0094] Please refer to Figure 8 , Figure 8 This is a schematic diagram of the 7th Vsync cycle provided in an embodiment of the present invention. In the 7th Vsync cycle, the application renders the 4th image, which includes the 4th left-eye frame and the 4th right-eye frame. The layer composition of the 3rd right-eye frame is performed, and the 3rd left-eye frame is sent to the second buffer. At the same time, the 2nd left-eye frame in the third buffer is output to the display screen.

[0095] from Figure 8 As can be seen, the alternating left and right eye frame sequence output to the display screen by the present invention is: 1st left eye frame - 1st right eye frame - 2nd left eye frame.

[0096] Please refer to Figure 9 , Figure 9 This is a schematic diagram of the 8th Vsync cycle provided in an embodiment of the present invention. In the 8th Vsync cycle, the layer compositing of the 4th left-eye frame is performed and the 3rd right-eye frame is sent to the third buffer, while the 2nd right-eye frame in the first buffer is output to the display screen.

[0097] from Figure 9 As can be seen, the alternating left and right eye frame sequence output to the display screen by the present invention is: 1st left eye frame - 1st right eye frame - 2nd left eye frame - 2nd right eye frame.

[0098] Please refer to Figure 10 , Figure 10This is a schematic diagram of Vsync cycle timeout provided in an embodiment of the present invention. Each Vsync cycle is a preset value (e.g., 8.33ms). Assuming that the arrival time of the 9th Vsync cycle controlled by the frame processing module is greater than this preset value (e.g., greater than 8.33ms), it means that the 9th Vsync cycle will time out and no data will be written to the buffer. However, the hardware clock of DSI needs to be output strictly according to the preset frequency (e.g., 120Hz). Therefore, before the arrival of the 9th Vsync cycle, the present invention directly outputs the 3rd left-eye frame in the second buffer to the display screen.

[0099] from Figure 10 As can be seen, the alternating left-eye frame sequence output to the display screen by this invention is: 1st left-eye frame - 1st right-eye frame - 2nd left-eye frame - 2nd right-eye frame - 3rd left-eye frame. That is to say, even in the case of Vsync period timeout, this invention can still maintain a stable alternating left-eye frame sequence.

[0100] Please refer to Figure 11 , Figure 11 This is a schematic diagram of the 9th Vsync cycle provided in an embodiment of the present invention. In the 9th Vsync cycle, the application renders the 5th image, which includes the 5th left-eye frame and the 5th right-eye frame. The layer composition of the 4th right-eye frame is performed, and the 4th left-eye frame is sent to the first buffer. At the same time, the 3rd right-eye frame in the third buffer is output to the display screen.

[0101] It should be noted that the fourth left-eye frame is sent to the first buffer here because the ninth Vsync cycle timed out. Figure 10 No data was written to the first buffer, while Figure 11 Write the new data to the first buffer.

[0102] from Figure 11 As can be seen, the alternating left and right eye frame sequence output to the display screen by the present invention is: 1st left eye frame - 1st right eye frame - 2nd left eye frame - 2nd right eye frame - 3rd left eye frame - 3rd right eye frame.

[0103] Please refer to Figure 12 , Figure 12 This is a schematic diagram of the 10th Vsync cycle provided in an embodiment of the present invention. In the 10th Vsync cycle, the layer composition of the 5th left-eye frame is performed and the 4th right-eye frame is sent to the second buffer, while the 4th left-eye frame in the first buffer is output to the display screen.

[0104] from Figure 12 As can be seen, the alternating left and right eye frame sequence output to the display screen by the present invention is: 1st left eye frame - 1st right eye frame - 2nd left eye frame - 2nd right eye frame - 3rd left eye frame - 3rd right eye frame - 4th left eye frame.

[0105] Please refer to Figure 13 , Figure 13 This is a schematic diagram of the 11th Vsync cycle provided in an embodiment of the present invention. If the 11th Vsync cycle is less than a preset Vsync cycle value, it means that the 11th Vsync cycle has been advanced. Since the hardware clock of the DSI needs to be output strictly according to the preset frequency (e.g., 120Hz), the application is executed to render the 6th image in the 11th Vsync cycle. The 6th image includes the 6th left eye frame and the 6th right eye frame. The layer composition of the 5th right eye frame is performed and the 5th left eye frame is sent to the third buffer, while the display continues to display the 4th left eye frame.

[0106] from Figure 13 As can be seen, the alternating left and right eye frame sequence output to the display screen by the present invention is: 1st left eye frame - 1st right eye frame - 2nd left eye frame - 2nd right eye frame - 3rd left eye frame - 3rd right eye frame - 4th left eye frame.

[0107] Please refer to Figure 14 , Figure 14 This is a schematic diagram of the 12th Vsync cycle provided in an embodiment of the present invention. In the 12th Vsync cycle, the layer compositing of the 6th left-eye frame is performed and the 5th right-eye frame is sent to the first buffer, while the 4th right-eye frame in the second buffer is output to the display screen.

[0108] from Figure 14 As can be seen, the alternating left and right eye frame sequence output to the display screen by the present invention is: 1st left eye frame - 1st right eye frame - 2nd left eye frame - 2nd right eye frame - 3rd left eye frame - 3rd right eye frame - 4th left eye frame - 4th right eye frame.

[0109] Please refer to Figure 15 , Figure 15 This is a schematic diagram of the 13th Vsync cycle provided in an embodiment of the present invention. In the 13th Vsync cycle, the application renders the 7th image, which includes the 7th left-eye frame and the 7th right-eye frame. The layer composition of the 6th right-eye frame is performed, and the 6th left-eye frame is sent to the second buffer. At the same time, the 5th left-eye frame in the third buffer is output to the display screen.

[0110] from Figure 15 As can be seen, the alternating left and right eye frame sequence output to the display screen by the present invention is: 1st left eye frame - 1st right eye frame - 2nd left eye frame - 2nd right eye frame - 3rd left eye frame - 3rd right eye frame - 4th left eye frame - 4th right eye frame - 5th left eye frame.

[0111] Similarly, the operations after the 13th Vsync cycle are performed in the same manner as described above, and will not be repeated here.

[0112] Therefore, it can be seen that regardless of whether the Vsync period times out or the Vsync period advances, the frame control device of the present invention has one left-eye frame and one right-eye frame buffered in the first buffer to the third buffer. After the second frame is written to the second buffer, the display can start. At this time, the third buffer that buffers the third frame is empty. Therefore, the third frame can be written to the third buffer synchronously when the second frame is displayed on the screen. Thus, it can ensure the maintenance of a stable left-eye alternating frame sequence.

[0113] In another embodiment of the present invention, provided that the first to third buffers of the above embodiments of the present invention have cached 1 left-eye frame and 1 right-eye frame, only one buffer in the three-buffer mode can be used for writing the next frame. However, when the Vsync period is relatively short (e.g., the Vsync period is advanced), there may be a situation where there is no additional buffer to write to. Therefore, the present invention can also configure at least three or more buffers, for example, four buffers.

[0114] Please refer to Figure 16 , Figure 16 This is a schematic diagram illustrating the advance of the Vsync period provided in this embodiment of the invention. For example, when the third frame (i.e., the second left-eye frame) is sent to the third buffer, if the Vsync period is less than a preset value (e.g., 8.33ms), it is possible that after the third frame is sent to the third buffer, the fourth frame (i.e., the second right-eye frame) is prepared to be sent to the fourth buffer, but the DSI has not yet completed sending the second frame to the display screen. Therefore, if a fourth buffer is configured for caching, the situation where there is no spare buffer to cache the fourth frame can be avoided.

[0115] For example, if a fourth buffer is configured, then layer compositing of the third left-eye frame and feeding the second right-eye frame into the fourth buffer (buffer4) can be performed when the sixth Vsync cycle arrives early, based on the previous five Vsync cycles. Figure 16 The alternating left and right eye frame sequence output to the display screen is: the first left eye frame.

[0116] Understandably, configuring three buffers is the better option in practical applications, but whether four or more buffers are needed depends on the actual Vsync cycle.

[0117] The frame control device provided by the present invention is described below. The frame control device described below can be referred to in correspondence with the frame control method described above.

[0118] Please refer to Figure 17 , Figure 17 This is a flowchart illustrating the frame control method provided by the present invention. A frame control method, the method comprising:

[0119] Step 170: Execute application rendering in the Mth Vsync cycle to render the Nth image, which includes the Nth left-eye frame and the Nth right-eye frame. Here, M and N are both positive integers.

[0120] Step 171: Assume that the layer composition of the Nth left eye frame is performed in the M+1th Vsync cycle.

[0121] Step 172: In the M+2 Vsync cycle, perform application rendering including the N+1th image of the N+1th left eye frame and the N+1th right eye frame, perform layer compositing of the Nth right eye frame, and send the Nth left eye frame into the first buffer.

[0122] Step 173: In the M+3 Vsync cycle, perform layer compositing of the N+1 left-eye frame and send the Nth right-eye frame into the second buffer.

[0123] Step 174: In the M+4th Vsync cycle, the application rendering is performed, including the N+2nd image of the N+2nd left eye frame and the N+2nd right eye frame, the layer composition of the N+1st right eye frame is performed, and the N+1st left eye frame is sent to the third buffer. At the same time, the Nth left eye frame in the first buffer is output to the display screen.

[0124] The present invention also provides a display system that, when displaying a frame sequence of alternating left and right eye images on a display screen, executes the frame control method described above.

[0125] For example, the display system further includes a display screen for displaying a stereoscopic image by showing an alternating frame sequence of left and right eye images transmitted from the frame control device.

[0126] It should be noted that the frame control method provided in this embodiment of the invention can achieve the functions implemented in the above-mentioned device embodiment and can achieve the same technical effects. Here, the parts and beneficial effects that are the same as those in the device embodiment will not be described in detail.

[0127] Figure 18 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 18 As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 830, and a communication bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other via the communication bus 840. The processor 810 can call logical instructions in the memory 830 to execute the frame control method, the method including:

[0128] The application renders the Nth image, which includes the Nth left-eye frame and the Nth right-eye frame, during the Mth Vsync cycle.

[0129] If the layer composition of the Nth left-eye frame is performed in the (M+1)th Vsync cycle, then

[0130] The application rendering is performed in the M+2 Vsync cycle, including the N+1th image of the N+1th left eye frame and the N+1th right eye frame, performing layer compositing of the Nth right eye frame, and feeding the Nth left eye frame into the first buffer;

[0131] In the M+3 Vsync cycle, the layer composition of the N+1 left eye frame is performed and the Nth right eye frame is fed into the second buffer;

[0132] In the M+4th Vsync cycle, the application rendering is performed, including the N+2th image of the N+2th left eye frame and the N+2th right eye frame, the layer composition of the N+1th right eye frame, and the N+1th left eye frame is sent to the third buffer, while the Nth left eye frame in the first buffer is output to the display screen.

[0133] Where M and N are both positive integers.

[0134] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0135] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, and when the program instructions are executed by a computer, the computer is able to execute the frame control method provided by the above methods.

[0136] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the frame control methods provided above.

[0137] The present invention provides an electronic device, a computer program product, and a processor-readable storage medium, wherein the computer program stored thereon enables the processor to implement all the method steps implemented in the above method embodiments and achieve the same technical effect. Here, the parts that are the same as those in the method embodiments and the beneficial effects will not be described in detail.

[0138] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0139] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A frame control device, characterized in that, The device includes: The display interface module includes a first buffer, a second buffer, a third buffer, and a fourth buffer; The frame processing module is used to perform application rendering in the Mth Vsync cycle to render the Nth image, which includes the Nth left-eye frame and the Nth right-eye frame; If the layer composition of the Nth left-eye frame is performed in the (M+1)th Vsync cycle, then The application rendering is performed in the M+2 Vsync cycle, including the N+1th image of the N+1th left eye frame and the N+1th right eye frame, performing layer compositing of the Nth right eye frame, and feeding the Nth left eye frame into the first buffer; In the M+3 Vsync cycle, the layer composition of the N+1 left eye frame is performed and the Nth right eye frame is fed into the second buffer; In the M+4th Vsync cycle, the application rendering is performed, including the N+2th image of the N+2th left eye frame and the N+2th right eye frame, the layer composition of the N+1th right eye frame is performed, and the N+1th left eye frame is sent to the third buffer, while the Nth left eye frame in the first buffer is output to the display screen. The frame processing module is also used to: when the M+5th Vsync cycle is less than a preset Vsync cycle value, perform layer synthesis of the N+2th left eye frame and send the N+1th right eye frame into the fourth buffer in the M+5th Vsync cycle. Where M and N are both positive integers.

2. The frame control device according to claim 1, characterized in that, The frame processing module is also used for: In the M+5th Vsync cycle, the layer composition of the N+2th left eye frame is performed and the N+1th right eye frame is sent to the first buffer, while the Nth right eye frame in the second buffer is output to the display screen. In the M+6th Vsync cycle, the application rendering is performed, including the N+3rd image of the N+3rd left eye frame and the N+3rd right eye frame, the layer composition of the N+2nd right eye frame is performed, and the N+2nd left eye frame is sent to the second buffer, while the N+1th left eye frame in the third buffer is output to the display screen. In the M+7th Vsync cycle, the layer composition of the N+3rd left eye frame is performed and the N+2nd right eye frame is sent to the third buffer, while the N+1th right eye frame in the first buffer is output to the display screen.

3. The frame control device according to claim 2, characterized in that, Each Vsync cycle has a preset value. Assuming the (M+8th)th Vsync cycle is greater than the preset value, then before the (M+8th)th Vsync cycle arrives, the frame processing module is further configured to: The (N+2)th left-eye frame in the second buffer is output to the display screen.

4. The frame control device according to claim 3, characterized in that, The frame processing module is also used for: In the M+8th Vsync cycle, the application rendering is performed, including the N+4th image of the N+4th left eye frame and the N+4th right eye frame, the layer composition of the N+3rd right eye frame is performed, and the N+3rd left eye frame is sent to the first buffer, while the N+2th right eye frame in the third buffer is output to the display screen.

5. A frame control method, characterized in that, The method includes: The application renders the Nth image, which includes the Nth left-eye frame and the Nth right-eye frame, during the Mth Vsync cycle. If the layer composition of the Nth left-eye frame is performed in the (M+1)th Vsync cycle, then The application rendering is performed in the M+2 Vsync cycle, including the N+1th image of the N+1th left eye frame and the N+1th right eye frame, performing layer compositing of the Nth right eye frame, and feeding the Nth left eye frame into the first buffer; In the M+3 Vsync cycle, the layer composition of the N+1 left eye frame is performed and the Nth right eye frame is fed into the second buffer; In the M+4th Vsync cycle, the application rendering is performed, including the N+2th image of the N+2th left eye frame and the N+2th right eye frame, the layer composition of the N+1th right eye frame, and the N+1th left eye frame is sent to the third buffer, while the Nth left eye frame in the first buffer is output to the display screen. When the M+5th Vsync cycle is less than the preset value, the layer composition of the N+2th left eye frame is performed and the N+1th right eye frame is sent into the fourth buffer in the M+5th Vsync cycle. Where M and N are both positive integers.

6. The frame control method according to claim 5, characterized in that, The method further includes: In the M+5th Vsync cycle, the layer composition of the N+2th left eye frame is performed and the N+1th right eye frame is sent to the first buffer, while the Nth right eye frame in the second buffer is output to the display screen. In the M+6th Vsync cycle, the application rendering is performed, including the N+3rd image of the N+3rd left eye frame and the N+3rd right eye frame, the layer composition of the N+2nd right eye frame is performed, and the N+2nd left eye frame is sent to the second buffer, while the N+1th left eye frame in the third buffer is output to the display screen. In the M+7th Vsync cycle, the layer composition of the N+3rd left eye frame is performed and the N+2nd right eye frame is sent to the third buffer, while the N+1th right eye frame in the first buffer is output to the display screen.

7. The frame control method according to claim 6, characterized in that, Each Vsync cycle is a preset value. Assuming the (M+8th)th Vsync cycle is greater than the preset value, the method further includes the following steps before the (M+8th)th Vsync cycle arrives: The (N+2)th left-eye frame in the second buffer is output to the display screen.

8. The frame control method according to claim 7, characterized in that, The method further includes: In the M+8th Vsync cycle, the application rendering is performed, including the N+4th image of the N+4th left eye frame and the N+4th right eye frame, the layer composition of the N+3rd right eye frame is performed, and the N+3rd left eye frame is sent to the first buffer, while the N+2th right eye frame in the third buffer is output to the display screen.

9. A display system, characterized in that, When the display system displays a frame sequence of alternating left and right eye images on the display screen, it executes the frame control method described in any one of claims 5 to 8.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the frame control method as described in any one of claims 5 to 8.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the frame control method as described in any one of claims 5 to 8.

Images