Pixel driving circuit and driving method thereof, display panel

Abstract

The application discloses a pixel driving circuit and a driving method thereof and a display panel. The pixel circuit comprises a first driving module, a second driving module and a light-emitting module. The output end of the first driving module is connected with the control end of the second driving module. The first driving module comprises a first driving unit, a first voltage writing unit, a second voltage writing unit, a third voltage writing unit, a coupling unit and a storage unit. The storage unit is connected with the intermediate node of the first voltage writing unit. The first voltage writing unit is used for writing the data voltage corresponding to the next display frame into the storage unit during the last display frame and transmitting the data voltage to the first end of the coupling unit during the next display frame. The technical scheme provided by the embodiment can realize the writing of the data voltage corresponding to the next display frame during the light-emitting process, greatly saves the data writing time, can complete the picture switching in a smaller clock cycle, and is favorable for improving the flickering phenomenon.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel driving circuit and its driving method, and a display panel. Background Technology

[0002] With the continuous development of display technology, micro light emitting diodes (Micro-LEDs) are widely used in the display field due to their advantages such as wide color gamut, fast response speed, high brightness and long life.

[0003] Currently, Micro-LED display panels typically include pixel circuits and light-emitting elements. The pixel circuits usually use digital driving methods to control the light-emitting elements. However, existing display panels are prone to flickering during display, which reduces the display effect. Summary of the Invention

[0004] This invention provides a pixel driving circuit and its driving method, as well as a display panel, to improve the flickering phenomenon of the displayed image.

[0005] According to one aspect of the present invention, a pixel driving circuit is provided, comprising: a first driving module, a second driving module, and a light-emitting module, wherein the output terminal of the first driving module is connected to the control terminal of the second driving module, and the second driving module and the light-emitting module are connected between a first power line and a second power line.

[0006] The first driving module includes a first driving unit, a first voltage writing unit, a second voltage writing unit, a third voltage writing unit, a coupling unit, and a storage unit. The first voltage writing unit is connected between a data line and a first end of the coupling unit. The storage unit is connected to an intermediate node of the first voltage writing unit. The first voltage writing unit is used to write the data voltage corresponding to the next display frame to the storage unit during the previous display frame and to transmit the data voltage to the first end of the coupling unit during the next display frame.

[0007] The second voltage writing unit is used to transmit a sweep frequency signal to the first end of the coupling unit during the voltage writing stage. The coupling unit is used to couple the data voltage and the sweep frequency signal to the control end of the first driving unit. The third voltage writing unit is used to transmit a fixed voltage to the control end of the first driving unit.

[0008] The first driving unit is connected between the first power line and the control terminal of the second driving module, and is used to control the voltage of the control terminal of the second driving module according to the data voltage and the frequency sweep signal, so as to control the light emission time of the light-emitting module.

[0009] Optionally, the first voltage writing unit includes a pre-charge sub-unit and a data voltage writing sub-unit; a first terminal of the pre-charge sub-unit is connected to the data line, a second terminal of the pre-charge sub-unit is connected to the first terminal of the data voltage writing sub-unit, the second terminal of the data voltage writing sub-unit is connected to the first terminal of the coupling unit, a control terminal of the pre-charge sub-unit is connected to a first scan line, and a control terminal of the data voltage writing sub-unit is connected to a second scan line; a first terminal of the storage unit is connected to the second terminal of the pre-charge sub-unit, and a second terminal of the storage unit is connected to the first power line.

[0010] Preferably, the precharge sub-unit includes a first transistor, the data voltage write sub-unit includes a second transistor, the storage unit includes a first capacitor, the first terminal of the first transistor is connected to the data line, the second terminal of the first transistor is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the first end of the coupling unit, the first capacitor is connected between the second terminal of the first transistor and the first power line, the gate of the first transistor is connected to the first scan line, and the gate of the second transistor is connected to the second scan line.

[0011] Optionally, the pre-charge subunit is configured to write the data voltage corresponding to the current display frame to the storage unit before the voltage writing phase, and the data voltage writing subunit is configured to transmit the data voltage to the first end of the coupling unit during the voltage writing phase.

[0012] Optionally, the fixed voltage includes the power supply voltage, the first end of the third voltage writing unit is connected to the first power line, the second end of the third voltage writing unit is connected to the control terminal of the first driving unit, and the third voltage writing unit is used to transmit the power supply voltage transmitted on the first power line to the control terminal of the first driving unit during the voltage writing stage.

[0013] Optionally, the first driving module further includes a compensation unit and a reset unit. The compensation unit is connected between the control terminal and the second terminal of the first driving unit, and the reset unit is connected between the reset signal line and the control terminal of the second driving module. The reset unit is used to transmit the reset voltage transmitted on the reset signal line to the control terminal of the second driving module during the reset phase.

[0014] Preferably, the fixed voltage includes an initialization voltage, the first end of the third voltage writing unit is connected to the initialization signal line, the second end of the third voltage writing unit is connected to the control end of the first driving unit, and the third voltage writing unit is used to transmit the initialization voltage transmitted on the initialization signal line to the control end of the first driving unit during the voltage writing stage.

[0015] Preferably, the first driving unit includes a third transistor, the compensation unit includes a fourth transistor, the third voltage writing unit includes a fifth transistor, the second voltage writing unit includes a sixth transistor, the reset unit includes a seventh transistor, and the coupling unit includes a second capacitor;

[0016] The first terminal of the third transistor is connected to the first power supply line, and the second terminal of the third transistor is connected to the control terminal of the second drive module. The first terminal of the fourth transistor is connected to the second terminal of the third transistor, and the second terminal of the fourth transistor is connected to the gate of the third transistor. The gate of the fourth transistor is connected to the third scan line. The first terminal of the fifth transistor is connected to the initialization signal line, and the second terminal of the fifth transistor is connected to the gate of the third transistor. The gate of the fifth transistor is connected to the fourth scan line. The first terminal of the sixth transistor is connected to the sweep frequency signal, and the second terminal of the sixth transistor is connected to the first terminal of the second capacitor. The second terminal of the second capacitor is connected to the gate of the third transistor, and the gate of the sixth transistor is connected to the fifth scan line. The first terminal of the seventh transistor is connected to the reset signal line, and the second terminal of the seventh transistor is connected to the control terminal of the second drive module. The gate of the seventh transistor is connected to the sixth scan line.

[0017] Preferably, the initialization signal line is multiplexed as the reset signal line.

[0018] Optionally, the second driving module includes a second driving unit, the control terminal of the second driving unit is connected to the output terminal of the first driving module as the control terminal of the second driving module, the first terminal of the second driving unit is connected to the power supply voltage transmitted on the first power line, the second terminal of the second driving unit is connected to the first terminal of the light-emitting module, and the second terminal of the light-emitting module is connected to the second power line.

[0019] Preferably, the second driving module further includes a light-emitting control unit, which is connected between the first power line and the first end of the second driving unit, and the control terminal of the light-emitting control unit is connected to the light-emitting control signal line;

[0020] Preferably, the second driving unit includes an eighth transistor, the light-emitting control unit includes a ninth transistor, the first terminal of the ninth transistor is connected to the first power line, the second terminal of the ninth transistor is connected to the first terminal of the eighth transistor, the second terminal of the eighth transistor is connected to the first terminal of the light-emitting module, the gate of the eighth transistor is connected to the output terminal of the first driving module, and the gate of the ninth transistor is connected to the light-emitting control signal line.

[0021] Optionally, the control terminal of the second voltage writing unit is connected to the fifth scan line, and the control terminal of the third voltage writing unit is connected to the fourth scan line. The first scan line, the second scan line, the fourth scan line, and the fifth scan line are configured to transmit scan line numbers to satisfy the following:

[0022] The precharged sub-unit is turned on before the voltage writing phase;

[0023] During the voltage writing phase, the data voltage writing subunit, the second voltage writing unit, and the third voltage writing unit are turned on, but the data voltage writing subunit and the second voltage writing unit are not turned on simultaneously.

[0024] During the light-emitting phase, the second driving module is turned on.

[0025] According to another aspect of the present invention, a driving method for a pixel driving circuit is provided. The pixel circuit includes a first driving module, a second driving module, and a light-emitting module. The output terminal of the first driving module is connected to the control terminal of the second driving module. The second driving module and the light-emitting module are connected between a first power line and a second power line. The first driving module includes a first driving unit, a first voltage writing unit, a second voltage writing unit, a third voltage writing unit, a coupling unit, and a storage unit. The first voltage writing unit is connected between a data line and a first terminal of the coupling unit. The storage unit is connected to an intermediate node of the first voltage writing unit. The first driving unit is connected between the first power line and the control terminal of the second driving module. The driving method for the pixel driving circuit includes:

[0026] During the previous display frame, the first voltage writing unit is controlled to write the data voltage corresponding to the next display frame to the storage unit;

[0027] During the next display frame, in the voltage writing phase, the third voltage writing unit is controlled to transmit a fixed voltage to the control terminal of the first driving unit, and the first voltage writing unit is controlled to transmit the data voltage to the first terminal of the coupling unit. Then, the second voltage writing unit is controlled to transmit a sweep signal to the first terminal of the coupling unit, so as to control the coupling unit to couple the data voltage and the sweep signal to the control terminal of the first driving unit.

[0028] During the light-emitting phase, the voltage of the control terminal of the second driving module is controlled according to the data voltage and the frequency sweep signal to control the light-emitting time of the light-emitting module.

[0029] Optionally, the first voltage writing unit includes a pre-charge sub-unit and a data voltage writing sub-unit. A first terminal of the pre-charge sub-unit is connected to the data line, a second terminal of the pre-charge sub-unit is connected to the first terminal of the data voltage writing sub-unit, the second terminal of the data voltage writing sub-unit is connected to the first terminal of the coupling unit, a first terminal of the storage unit is connected to the second terminal of the pre-charge sub-unit, and a second terminal of the storage unit is connected to the first power line. The first driving module further includes a compensation unit connected between the control terminal and the second terminal of the first driving unit. A first terminal of the third voltage writing unit is connected to an initialization signal line, and a second terminal of the third voltage writing unit is connected to the control terminal of the first driving unit. The voltage writing stage includes an initialization stage, a data writing and threshold compensation stage, and a voltage normalization stage. The specific steps of the pixel driving circuit in the voltage writing stage include:

[0030] During the initialization phase, the third voltage writing unit is controlled to write the initialization voltage transmitted on the initialization signal line to the control terminal of the first driving unit.

[0031] During the data writing and threshold compensation stage, the compensation unit is controlled to compensate the threshold voltage of the first driving unit, while the second voltage writing unit is controlled to transmit the first level of the sweep frequency signal to the first end of the coupling unit, and the data voltage writing subunit is controlled to write the data voltage stored on the storage unit to the first end of the coupling unit.

[0032] During the voltage normalization stage, the second voltage writing unit is controlled to transmit the second level of the sweep frequency signal to the first terminal of the coupling unit, so as to control the coupling unit to couple the data voltage and the sweep frequency signal to the control terminal of the first driving unit;

[0033] Preferably, the first driving module further includes a reset unit connected between the reset signal line and the control terminal of the second driving module. After the voltage writing stage, the driving method of the pixel driving circuit further includes:

[0034] During the reset phase, the reset unit controls the reset voltage transmitted on the reset signal line to the control terminal of the second drive module.

[0035] According to another aspect of the present invention, a display panel is provided, including the pixel driving circuit provided in any embodiment of the present invention.

[0036] The technical solution provided by this embodiment of the invention sets up a first voltage writing unit and a storage unit, and connects the storage unit to the intermediate node of the first voltage writing unit. This allows the first voltage writing unit to write the data voltage corresponding to the next display frame to the storage unit during the previous display frame (such as the light emission stage). When entering the next display frame, the data voltage stored in the storage unit is directly transmitted to the first end of the coupling unit through the first voltage writing unit. The technical solution provided by this embodiment can realize the writing of the data voltage corresponding to the next display frame during the light emission process, which greatly saves the data writing time. The screen switching can be completed in a shorter clock cycle, which helps to improve the flickering phenomenon and thus improve the display effect. Moreover, since the data writing time is reduced, the light emission time can be increased accordingly, which helps to ensure the maximum brightness of the light emission and the reliability of grayscale expansion. On the other hand, the data voltage and the sweep frequency signal are set separately and do not affect each other, which helps to improve the reliability of signal transmission. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0045] Figure 8 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0046] Figure 9 A timing control waveform diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0047] Figure 10 A flowchart illustrating a driving method for a pixel driving circuit provided in an embodiment of the present invention;

[0048] Figure 11 A flowchart of another pixel driving circuit driving method provided in an embodiment of the present invention;

[0049] Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0050] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0052] As described in the background section, display panels driven by existing pixel driving circuits are prone to screen flickering. After careful research, the inventors discovered that the cause of this problem is as follows: When existing pixel driving circuits use a digital driving method, after the data signal is written, all pixel circuits in the front display panel switch to a SWEEP signal for overall operation, thereby controlling the light-emitting time of the light-emitting devices. Therefore, during the data signal writing process, the light-emitting devices need to be kept off, and they can only emit light uniformly after the data signal is completely written. This causes the light-emitting time of the light-emitting devices to be affected by the data signal writing time of the entire display panel. For large screens or screens with high PPI, the data writing time for the entire display panel is longer, meaning the display panel is not emitting light for a longer period, causing screen flickering during screen transitions. Furthermore, within a single frame, the longer data writing time reduces the light-emitting time, affecting the maximum brightness of the display panel and severely degrading the display effect.

[0053] To address the aforementioned problems, this invention provides a pixel driving circuit that allows data signals to be written during the light-emitting phase, significantly reducing the time the display panel is not emitting light and thus improving the display effect. The pixel driving circuit provided in this embodiment is applicable to both digital driving and mixed-signal driving. Figure 1 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention, with reference to... Figure 1 The pixel driving circuit includes: a first driving module 10, a second driving module 20, and a light-emitting module 30. The output terminal of the first driving module 10 is connected to the control terminal G2 of the second driving module 20. The second driving module 20 and the light-emitting module 30 are connected between the first power line L1 and the second power line L2. The first driving module 10 includes a first driving unit 101, a first voltage writing unit 102, a second voltage writing unit 103, a third voltage writing unit 104, a coupling unit 106, and a storage unit 107. The first voltage writing unit 102 is connected between the data line and the first terminal of the coupling unit 106. The storage unit 107 is connected to the intermediate node M of the first voltage writing unit 102. The first voltage writing unit 102 is used to write the data voltage Vdata corresponding to the next display frame to the storage unit during the previous display frame and to transmit the data voltage Vdata to the first terminal of the coupling unit 106 during the next display frame.

[0054] The second voltage writing unit 103 is used to transmit the sweep frequency signal SWEEP to the first terminal of the coupling unit 106 during the voltage writing stage. The coupling unit 106 is used to couple the data voltage Vdata and the sweep frequency signal SWEEP to the control terminal G1 of the first driving unit 101. The third voltage writing unit 104 is used to transmit a fixed voltage V1 to the control terminal G1 of the first driving unit 101.

[0055] The first driving unit 101 is connected between the first power line L1 and the control terminal G2 of the second driving module 20. It is used to control the voltage of the control terminal G2 of the second driving module 20 according to the data voltage Vdata and the sweep frequency signal SWEEP, so as to control the light emission time of the light emission module 30.

[0056] Specifically, the first power line L1 can be used to transmit the first power supply voltage VDD, and the second power line L2 can be used to transmit the second power supply voltage VSS. In this embodiment, the second driving module 20 can be used for switching functions, that is, driving the light-emitting module 30 to emit light in a digital driving manner; the second driving module 20 can also be used for driving functions, that is, driving the light-emitting module 30 to emit light in a mixed digital-analog driving manner. This embodiment does not impose any special limitations on this.

[0057] The first driving unit 101 is connected between the first power line L1 and the control terminal G2 of the second driving module 20. It controls the voltage of the control terminal G2 of the second driving module 20 based on the voltage of its control terminal G1. The second driving module 20 controls the discharge path between the first power line L1 and the second power line L2 based on the voltage of its control terminal G2, thereby controlling the light-emitting time of the light-emitting module 30. The display brightness can be adjusted based on the light-emitting time of the light-emitting module 30, thus achieving grayscale expansion. The operation of the pixel driving circuit provided in this embodiment includes at least a voltage writing stage and a light-emitting stage.

[0058] During the voltage writing stage, the data voltage Vdata is transmitted to the first terminal of the coupling unit 106. The second terminal of the coupling unit 106 is a constant voltage (which can be a fixed voltage V1 or other voltages), and a potential difference exists between the two terminals of the coupling unit 106. When the second voltage writing unit 103 transmits the sweep frequency signal SWEEP to the first terminal of the coupling unit 106, the potential of the first terminal of the coupling unit 106 changes. Under the coupling effect of the coupling unit 106, the voltage change at the first terminal is coupled to the second terminal. Therefore, the voltage at the second terminal of the coupling unit 106 is related to the data voltage Vdata and the sweep frequency signal SWEEP. That is, the data voltage Vdata and the sweep frequency signal SWEEP are written to the control terminal G1 of the first driving unit 101 through the coupling unit 106. During the light emission stage, as the sweep frequency signal SWEEP gradually changes, under the coupling effect of the coupling unit 106, the potential of the control terminal G1 of the first driving unit 101 changes synchronously, thereby controlling the voltage of the control terminal G2 of the second driving module 20.

[0059] In this embodiment, the first voltage writing unit 102 is used to write the data voltage Vdata corresponding to the next display frame to the storage unit 107 during the previous display frame, and to transmit the data voltage Vdata stored in the storage unit 107 to the first end of the coupling unit 106 during the next display frame. The storage unit 107 is connected to the intermediate node M of the first voltage writing unit 102. That is, the data voltage Vdata corresponding to the current display frame is provided by the storage unit 107. During the display of the current display frame, the data voltage Vdata corresponding to the next display frame is transmitted on the data line and stored in the storage unit 107 for use in the next display frame. For example, the data voltage corresponding to the first display frame is Vdata1, and the data voltage corresponding to the second display frame is Vdata2. During the first display frame, Vdata2 has already been written to the storage unit 107 by the first voltage writing unit 102. Therefore, when switching to the second display frame, during the voltage writing stage, Vdata2 can be directly written from the storage unit 107 to the coupling unit 106. For the entire screen, the data voltage corresponding to the next display frame can be written simultaneously with the screen emitting light, effectively reducing data writing time and shortening the time between adjacent display frames when the screen is not emitting light, thereby improving screen flicker. Here, during the second display frame, the data voltage Vdata3 corresponding to the third display frame is also written to the storage unit 107, realizing the writing of the data voltage corresponding to the next display frame to the storage unit 107 during the light emission process, thus saving data writing time.

[0060] The technical solution provided by this embodiment of the invention sets up a first voltage writing unit and a storage unit, and connects the storage unit to the intermediate node of the first voltage writing unit. This allows the first voltage writing unit to write the data voltage corresponding to the next display frame to the storage unit during the previous display frame (such as the light emission stage). When entering the next display frame, the data voltage stored in the storage unit is directly transmitted to the first end of the coupling unit through the first voltage writing unit. The technical solution provided by this embodiment can realize the writing of the data voltage corresponding to the next display frame during the light emission process, which greatly saves the data writing time. The screen switching can be completed in a shorter clock cycle, which helps to improve the flickering phenomenon and thus improve the display effect. Moreover, since the data writing time is reduced, the light emission time can be increased accordingly, which helps to ensure the maximum brightness of the light emission and the reliability of grayscale expansion. On the other hand, the data voltage and the sweep frequency signal are set separately and do not affect each other, which helps to improve the reliability of signal transmission.

[0061] Figure 2 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, with reference to... Figure 2 Based on the above technical solution, optionally, the first voltage writing unit 102 includes a pre-charge sub-unit 111 and a data voltage writing sub-unit 112; the first end of the pre-charge sub-unit 111 is connected to the data line, the second end of the pre-charge sub-unit 111 is connected to the first end of the data voltage writing sub-unit 112, the second end of the data voltage writing sub-unit 112 is connected to the first end of the coupling unit 106, the control end of the pre-charge sub-unit 111 is connected to the first scan line S1, and the control end of the data voltage writing sub-unit 112 is connected to the second scan line S2; the first end of the storage unit 107 is connected to the second end of the pre-charge sub-unit 111, and the second end of the storage unit 107 is connected to the first power line L1.

[0062] The connection node between the pre-charge subunit 111 and the data voltage writing subunit 112 is the intermediate node M of the first voltage writing unit 102, and the storage unit 107 is connected between the first power line L1 and the intermediate node M. The pre-charge subunit 111 writes the data voltage Vdata corresponding to the next display frame into the storage unit 107 during the previous display frame, while the data voltage writing subunit 112 is in a turned-off state. When switching to the next display frame, the data voltage writing subunit 112 is turned on, transmitting the data voltage Vdata stored in the storage unit 107 to the first terminal of the coupling unit 106.

[0063] Specifically, Figure 3 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, with reference to... Figure 3Based on the above technical solution, the pre-charge subunit 111 includes a first transistor M1, the data voltage writing subunit 112 includes a second transistor M1, and the storage unit 107 includes a first capacitor C1. The first terminal of the first transistor M1 is connected to the data line, the second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2, the second terminal of the second transistor M2 is connected to the first terminal of the coupling unit 106, the first capacitor C1 is connected between the second terminal of the first transistor M1 and the first power line L1, the gate of the first transistor M1 is connected to the first scan line S1, and the gate of the second transistor M2 is connected to the second scan line S2. Before the voltage writing stage, for example, corresponding to the light emission stage of the previous display frame, the first transistor M1 is turned on in response to the first scan signal S1 transmitted by the first scan line, and the second transistor M2 is turned off in response to the second scan signal S2 transmitted by the second scan line. The first transistor M1 transmits the data voltage Vdata corresponding to the next display frame transmitted on the data line to the intermediate node M and stores it on the first capacitor C1, thereby realizing the writing of the data voltage Vdata corresponding to the next display frame during the light emission of the light emission module 30. When switching from the previous display frame to the next display frame, the first transistor M1 turns off in response to the first scan signal S1 transmitted by the first scan line, and the second transistor M2 turns on in response to the second scan signal S2 transmitted by the second scan line. The data voltage Vdata stored on the first capacitor C1 is transmitted to the first terminal of the coupling unit 106. During the light-emitting stage, the first driving unit 101 controls the voltage of the control terminal G2 of the second driving module 20 according to the data voltage Vdata and the sweep frequency signal SWEEP, thereby controlling the light-emitting time of the light-emitting module 30. Since the data voltage Vdata corresponding to the next display frame is written during the display of the previous display frame, the data writing time can be reduced. During the switching between adjacent display frames, the time during which the light-emitting module 30 does not emit light is greatly shortened, which helps to improve the screen flickering phenomenon.

[0064] It should be noted that, for ease of description, the scan lines and their output scan signals are represented by the same reference numerals in this embodiment, and the same applies below.

[0065] Figure 4 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, with reference to... Figure 4 Based on the above technical solutions, optionally, the fixed voltage V1 includes the power supply voltage, the first end of the third voltage writing unit 104 is connected to the first power line L1, the second end of the third voltage writing unit 104 is connected to the control terminal G1 of the first driving unit 101, and the third voltage writing unit 104 is used to transmit the power supply voltage transmitted on the first power line L1 to the control terminal G1 of the first driving unit 101 during the voltage writing stage.

[0066] Specifically, the power supply voltage transmitted on the first power line L1 can be the first power supply voltage VDD. During the voltage writing stage, the third voltage writing unit 104 transmits the first power supply voltage VDD to the control terminal G1 of the first driving unit 101, initializes the potential of the control terminal G1 of the first driving unit 101, and keeps the first driving unit 101 off. At the same time, the data voltage Vdata stored on the storage unit 107 is written to the first terminal of the coupling unit 106 through the data voltage writing sub-unit 112, and the voltage difference across the coupling unit 106 is stabilized at VDD-Vdata. Then, the sweep frequency signal SWEEP is written to the first terminal of the coupling unit 106, so that the coupling unit 106 couples the data voltage Vdata to the control terminal G1 of the first driving unit 101. After entering the light emission stage, the second driving module 20 is turned on, and the light emission module 30 emits light. As the sweep frequency signal SWEEP changes, the potential of the control terminal G1 of the first driving unit 101 changes synchronously under the coupling effect of the coupling unit 106. When the potential of its control terminal G1 causes the first driving unit 101 to be turned on, the first power supply voltage VDD is transmitted to the control terminal G2 of the second driving module 20, controlling the second driving module 20 to be turned off, thereby controlling the light-emitting module 30 to be turned off.

[0067] Figure 5 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, with reference to... Figure 5 Based on the above technical solutions, optionally, the first driving module 10 further includes a compensation unit 108, which is connected between the control terminal G1 and the second terminal of the first driving unit 101. The fixed voltage V1 includes the initialization voltage VINIT. The first terminal of the third voltage writing unit 104 is connected to the initialization signal line, and the second terminal of the third voltage writing unit 104 is connected to the control terminal G1 of the first driving unit 101. The third voltage writing unit 104 is used to transmit the initialization voltage VINIT transmitted on the initialization signal line to the control terminal G1 of the first driving unit 101 during the voltage writing stage.

[0068] The compensation unit 108 is used to compensate the threshold voltage of the first drive unit 101 to ensure the accuracy of the data voltage Vdata being converted into a time control signal and to improve the reliability of the control of the second drive module 20.

[0069] Further reference Figure 5 As a preferred embodiment provided in this example, the first driving module 10 further includes a reset unit 105. The reset unit 105 is connected between the reset signal line and the control terminal G2 of the second driving module 20. The reset unit 105 is used to transmit the reset voltage Vset transmitted on the reset signal line to the control terminal G2 of the second driving module 20 during the reset phase, thereby controlling at least some functional units in the second driving module 20 to be turned on.

[0070] Figure 6 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, showing the specific structure of the first driving module 10. (Refer to...) Figure 6 The first driving unit 101 includes a third transistor M3, the compensation unit 108 includes a fourth transistor M4, the third voltage writing unit 104 includes a fifth transistor M5, the second voltage writing unit 103 includes a sixth transistor M6, the reset unit 105 includes a seventh transistor M7, and the coupling unit 106 includes a second capacitor C2. The first terminal of the third transistor M3 is connected to the first power line L1, the second terminal of the third transistor M3 is connected to the control terminal G2 of the second driving module 20, the first terminal of the fourth transistor M4 is connected to the second terminal of the third transistor M3, the second terminal of the fourth transistor M4 is connected to the gate of the third transistor M3, and the gate of the fourth transistor M4 is connected to the third scan line S3. Connections: The first terminal of the fifth transistor M5 is connected to the initialization signal line; the second terminal of the fifth transistor M5 is connected to the gate of the third transistor M3; the gate of the fifth transistor M5 is connected to the fourth scan line S4; the first terminal of the sixth transistor M6 is connected to the sweep frequency signal SWEEP; the second terminal of the sixth transistor M6 is connected to the first terminal of the second capacitor C2; the second terminal of the second capacitor C2 is connected to the gate of the third transistor M3; the gate of the sixth transistor M6 is connected to the fifth scan line S5; the first terminal of the seventh transistor M7 is connected to the reset signal line; the second terminal of the seventh transistor M7 is connected to the control terminal G2 of the second drive module 20; the gate of the seventh transistor M7 is connected to the sixth scan line S6.

[0071] Specifically, this explanation uses a P-channel transistor as an example; in other embodiments, each transistor can also be an N-channel transistor. During the voltage writing phase, the fifth transistor M5 turns on in response to the fourth scan signal S4 output from the fourth scan line, transmitting the initialization voltage VINIT transmitted on the initialization signal line to the gate of the third transistor M3, thus initializing the gate potential of the third transistor M3. Simultaneously, the sixth transistor M6 turns on in response to the fifth scan signal S5 output from the fifth scan line, transmitting the low level of the sweep frequency signal SWEEP to the first terminal of the second capacitor C2, thereby initializing the potential across the second capacitor C2. At this time, the third transistor M3 is in the on state under its gate voltage control. Afterwards, the fourth transistor M4 turns on in response to the third scan signal S3 output from the third scan line. The first power supply voltage VDD transmitted on the first power supply line L1 is written to the gate of the third transistor M3 through the third transistor M3 and the fourth transistor M4. When the gate potential of the third transistor M3 is VDD + Vth3, the third transistor M3 is turned off, where Vth3 is the threshold voltage of the third transistor M3. After compensation, the gate of the third transistor M3 reaches a stable potential (VDD + Vth3). Then, the second transistor M2 turns on in response to the second scan signal S2 output by the second scan line. The data voltage Vdata stored on the first capacitor C1 is written to the first terminal of the second capacitor C2 through the second transistor M2. After the data writing is complete, the sixth transistor M6 turns on again, transmitting the high level of the sweep signal SWEEP to the first terminal of the second capacitor C2. Under the coupling effect of the second capacitor C2, the data voltage Vdata is coupled to the gate of the third transistor M3. In this embodiment, the high level of the sweep signal SWEEP is greater than or equal to the maximum value of the data voltage Vdata.

[0072] Then, in the reset phase, the seventh transistor M7 turns on in response to the sixth scan signal S6 output by the sixth scan line, transmitting the reset voltage Vset to the control terminal G2 of the second driving module 20. During the light-emitting phase, the second driving module 20 turns on according to the voltage at its control terminal G2, connecting the discharge path between the first power line L1 and the second power line L2, causing the light-emitting module 30 to emit light. The sweep frequency signal SWEEP gradually changes from high to low level. Due to the coupling effect of the second capacitor C2, the gate voltage of the third transistor M3 gradually decreases until the third transistor M3 turns on. The first power supply voltage VDD is then transmitted to the control terminal G2 of the second driving module 20, the second driving module 20 turns off, and the light-emitting module 30 turns off.

[0073] In this embodiment, during the change of the sweep frequency signal SWEEP, the first transistor M1 turns on in response to the first scan signal S1 output by the first scan line, and writes the data voltage corresponding to the next display frame to the first capacitor C1, and the first capacitor C1 stores the data voltage.

[0074] Continue to refer to Figure 6 Preferably, the initialization signal line can be reused as a reset signal line, that is, the first terminal of the fifth transistor M5 and the first terminal of the seventh transistor M7 are both connected to the initialization voltage VINIT. This helps to save the number of signal lines, and thus helps to improve PPI.

[0075] Figure 7 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, with reference to... Figure 7 Based on the above technical solutions, optionally, the second driving module 20 includes a second driving unit 201. The control terminal of the second driving unit 201 is connected to the output terminal of the first driving module 10 as the control terminal G2 of the second driving module 20. The first terminal of the second driving unit 201 is connected to the power supply voltage (such as the first power supply voltage VDD) transmitted on the first power line L1. The second terminal of the second driving unit 201 is connected to the first terminal of the light-emitting module 30. The second terminal of the light-emitting module 30 is connected to the second power line L2 and connected to the power supply voltage (such as the second power supply voltage VSS) transmitted on the second power line L2.

[0076] Preferably, the second driving module 20 further includes a light-emitting control unit 202, which is connected between the first power line L1 and the first end of the second driving unit 201. The control end of the light-emitting control unit 202 is connected to the light-emitting control signal line EM to improve the reliability of the pixel driving circuit and prevent the light-emitting module 30 from emitting light during the non-light-emitting stage.

[0077] Figure 8 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, with reference to... Figure 8 The second driving unit 201 includes an eighth transistor M8, and the light-emitting control unit 202 includes a ninth transistor M9. The first terminal of the ninth transistor M9 is connected to the first power line L1, the second terminal of the ninth transistor M9 is connected to the first terminal of the eighth transistor M8, the second terminal of the eighth transistor M8 is connected to the first terminal of the light-emitting module 30, the gate of the eighth transistor M8 is connected to the output terminal of the first driving module 10, and the gate of the ninth transistor M9 is connected to the light-emitting control signal line EM. Here, the second terminal of the third transistor M3 serves as the output terminal of the first driving module 10.

[0078] Figure 9 The timing control waveform diagram of a pixel driving circuit provided in this embodiment of the invention is applicable to... Figure 8 The pixel driving circuit shown is combined with Figure 8 and Figure 9The operation of the pixel driving circuit provided in this embodiment of the invention includes at least a voltage writing stage T1, a reset stage T2, and a light emission stage T3, wherein the voltage writing stage T1 includes an initialization stage t1, a data writing and threshold compensation stage t2, and a voltage normalization stage t3.

[0079] Before the voltage writing stage T1, i.e., the light-emitting stage of the previous display frame, the first scan line is configured to transmit a low-level first scan signal S1, the second scan line is configured to transmit a high-level second scan signal S2, the third scan line is configured to transmit a high-level third scan signal S3, the fourth scan line is configured to transmit a high-level fourth scan signal S4, the fifth scan line is configured to transmit a low-level fifth scan signal S5, and the sixth scan line is configured to transmit a high-level sixth scan signal S6. The light-emitting control signal line is configured to transmit a high-level light-emitting control signal EM. Then, the first transistor M1, the sixth transistor M6, and the ninth transistor M9 are turned on, and the light-emitting module 30 is in the light-emitting state. The gate voltage of the third transistor M3 is controlled by the sweep frequency signal SWEEP, thereby controlling the conduction state of the third transistor M3. When the third transistor M3 is turned on according to its gate voltage, the first power supply voltage VDD is transmitted to the gate of the eighth transistor M8, controlling the eighth transistor M8 to turn off, and the light-emitting module 30 is turned off. The light-emitting of the previous display frame ends. Since the first transistor M1 is in the ON state, the data voltage Vdata corresponding to the next display frame can be written to the first capacitor C1 for storage during the illumination process of the previous display frame. Because this scheme can write the data voltage of the next display frame during the illumination process, it eliminates the need for the pixel driving circuit to completely write the data voltage before unified illumination, greatly saving data writing time. This shortens the time the illumination module 30 is not illuminating during the switching of adjacent display frames, allowing the display frame switching to be completed in a shorter time, which helps to improve the flickering phenomenon during screen transitions.

[0080] When switching to the next display frame, during the initialization phase t1, the first scan line is configured to transmit a high-level first scan signal S1, the second scan line is configured to transmit a high-level second scan signal S2, the third scan line is configured to transmit a high-level third scan signal S3, the fourth scan line is configured to transmit a low-level fourth scan signal S4, the fifth scan line is configured to transmit a low-level fifth scan signal S5, and the sixth scan line is configured to transmit a high-level sixth scan signal S6. The light emission control signal line is configured to transmit a low-level light emission control signal EM. Then, the fifth transistor M5 and the sixth transistor M6 are turned on. The initialization voltage VINIT transmitted on the initialization signal line is transmitted through the fifth transistor M5 to the gate of the third transistor M3 (i.e., the second terminal of the second capacitor C2), thereby initializing the gate potential of the third transistor M3 and preventing residual charge from the previous display frame from affecting the current display frame. The sweep frequency signal SWEEP remains at a low level SL, and the low level SL of the sweep frequency signal SWEEP is transmitted through the sixth transistor M6 to the first terminal of the second capacitor C2. At this time, the third transistor M3 is in the on state.

[0081] During the data writing and threshold compensation phase t2, the first scan line is configured to transmit a high-level first scan signal S1, the second scan line is configured to first transmit a high-level second scan signal S2, followed by a low-level second scan signal S2, the third scan line is configured to transmit a low-level third scan signal S3, the fourth scan line is configured to transmit a high-level fourth scan signal S4, and the fifth scan line is configured to first transmit a low-level fifth scan signal S5. When the second scan signal S2 transitions to a low level, the fifth scan signal S5 transitions to a high level. The sixth scan line is configured to transmit a high-level sixth scan signal S6, and the light emission control signal line is configured to transmit a low-level light emission control signal EM. When the fifth scan signal S5 is low, the fourth transistor M4 and the sixth transistor M6 are turned on, and the first power supply voltage VDD transmitted on the first power supply line L1 charges the gate of the third transistor M3 through the third transistor M3 and the fourth transistor M4. At this time, because the sixth transistor M6 is turned on, the potential at the first terminal of the second capacitor C2 maintains the low level SL of the sweep signal SWEEP. When the sixth transistor M6 is turned off, the first terminal of the second capacitor C2 is initialized. When the fifth scan signal S5 jumps to a high level, the second scan signal S2 jumps to a low level, and the second transistor M2 turns on. The data voltage Vdata stored on the first capacitor C1 is written to the first terminal of the second capacitor C2 through the second transistor M2. Here, because the fourth transistor M4 remains on, when the gate voltage of the third transistor M3 is charged to VDD+Vth3, the third transistor M3 turns off, and the voltage difference across the second capacitor C2 is VDD+Vth3-Vdata, realizing threshold compensation for the third transistor M3 and writing the data voltage Vdata to the first terminal of the second capacitor C2. And during the period when the sixth transistor M6 is turned off, the sweep signal SWEEP jumps from a low level SL to a high level SH.

[0082] In this embodiment, the data voltage Vdata is written to the first capacitor C1 during the display of the previous display frame, and then written to the first terminal of the second capacitor C2 during the next display frame. The data voltage Vdata is the voltage corresponding to the next display frame. For example, if the voltage to be written to the first terminal of the second capacitor C2 in the next display frame is X, then the data voltage Vdata transmitted on the data line is = [C1(X-SL)+C2*X] / C2.

[0083] During the voltage normalization phase t3, the first scan line is configured to transmit a high-level first scan signal S1, the second scan line is configured to transmit a high-level second scan signal S2, the third scan line is configured to transmit a high-level third scan signal S3, the fourth scan line is configured to transmit a high-level fourth scan signal S4, the fifth scan line is configured to transmit a low-level fifth scan signal S5, and the sixth scan line is configured to transmit a high-level sixth scan signal S6. The light emission control signal line is configured to transmit a low-level light emission control signal EM. Then, the sixth transistor M6 is turned on, and the high-level SH of the sweep frequency signal SWEEP is transmitted to the first terminal of the second capacitor C2. Under the coupling effect of the second capacitor C2, the voltage X at the first terminal of the second capacitor C2 is coupled to the gate of the third transistor M3, that is, the data voltage Vdata is written to the gate of the third transistor M3. At this time, the gate voltage of the third transistor M3 is VDDVDD+Vth3-X+SH, where X is related to the data voltage Vdata. This completes the writing of the data signal corresponding to the next display frame.

[0084] During the reset phase t2, the first scan line is configured to transmit a high-level first scan signal S1, the second scan line is configured to transmit a high-level second scan signal S2, the third scan line is configured to transmit a high-level third scan signal S3, the fourth scan line is configured to transmit a high-level fourth scan signal S4, the fifth scan line is configured to transmit a low-level fifth scan signal S5, the sixth scan line is configured to transmit a low-level sixth scan signal S6, and the light emission control signal line is configured to transmit a low-level light emission control signal EM. Then, the sixth transistor M6 and the seventh transistor M7 are turned on, the sweep frequency signal SWEEP remains high at SH, and the reset voltage Vset is transmitted through the seventh transistor M7 to the gate of the eighth transistor M8, controlling the eighth transistor M8 to turn on.

[0085] During the light-emitting phase t3, the first scan line is configured to transmit a low-level first scan signal S1, the second scan line is configured to transmit a high-level second scan signal S2, the third scan line is configured to transmit a high-level third scan signal S3, the fourth scan line is configured to transmit a high-level fourth scan signal S4, the fifth scan line is configured to transmit a low-level fifth scan signal S5, and the sixth scan line is configured to transmit a high-level sixth scan signal S6. The light-emitting control signal line is configured to transmit a high-level light-emitting control signal EM. Then, the first transistor M1, the sixth transistor M6, and the ninth transistor M9 are turned on, and the light-emitting module 30 is in the light-emitting state. The sweep frequency signal SWEEP gradually changes from a high level SH to a low level SL. Under the coupling effect of the second capacitor C2, the gate voltage of the third transistor M3 changes synchronously. When the third transistor M3 is turned on according to its gate voltage, the first power supply voltage VDD is transmitted to the gate of the eighth transistor M8, controlling the eighth transistor M8 to turn off, and the light-emitting module 30 is turned off. The current display frame's light emission ends. Since the first transistor M1 is in the on state, during the light emission process, the data voltage Vdata corresponding to the next display frame can be written to the first capacitor C1 for storage.

[0086] It should be noted that the above is only an example of digital driving. In other embodiments, the second driving module 20 can also be an analog driving architecture, which will not be elaborated here.

[0087] In this embodiment, the light-emitting module 30 may include LED, OLED, Micro-LED or Mini-LED, etc.

[0088] Optionally, embodiments of the present invention also provide a driving method for a pixel driving circuit, applicable to the pixel driving circuits provided in any of the above embodiments. In conjunction with... Figure 1 The pixel driving circuit includes a first driving module 10, a second driving module 20, and a light-emitting module 30. The output terminal of the first driving module 10 is connected to the control terminal G2 of the second driving module 20. The second driving module 20 and the light-emitting module 30 are connected between a first power line L1 and a second power line L2. The first driving module 10 includes a first driving unit 101, a first voltage writing unit 102, a second voltage writing unit 103, a third voltage writing unit 104, a coupling unit 106, and a storage unit 107. The first voltage writing unit 102 is connected between a data line and the first end of the coupling unit 106. The storage unit 107 is connected to the intermediate node M of the first voltage writing unit 102. The first driving unit 101 is connected between the first power line L1 and the control terminal G2 of the second driving module 20.

[0089] Figure 10A flowchart of a pixel driving circuit driving method provided in an embodiment of the present invention is shown below. Figure 10 The driving method of the pixel driving circuit includes:

[0090] S110. During the previous display frame, control the first voltage writing unit to write the data voltage corresponding to the next display frame to the storage unit.

[0091] S120. During the next display frame, in the voltage writing phase, the third voltage writing unit is controlled to transmit a fixed voltage to the control terminal of the first driving unit, and the first voltage writing unit is controlled to transmit a data voltage to the first terminal of the coupling unit. Then, the second voltage writing unit is controlled to transmit a sweep signal to the first terminal of the coupling unit, so as to control the coupling unit to couple the data voltage and the sweep signal to the control terminal of the first driving unit.

[0092] S130. During the light-emitting stage, the voltage of the control terminal of the second driving module is controlled according to the data voltage and the frequency sweep signal to control the light-emitting time of the light-emitting module.

[0093] The technical solution provided by this embodiment of the invention sets up a first voltage writing unit and a storage unit, and connects the storage unit to the intermediate node of the first voltage writing unit. This allows the first voltage writing unit to write the data voltage corresponding to the next display frame to the storage unit during the previous display frame (such as the light emission stage). When entering the next display frame, the data voltage stored in the storage unit is directly transmitted to the first end of the coupling unit through the first voltage writing unit. The technical solution provided by this embodiment can realize the writing of the data voltage corresponding to the next display frame during the light emission process, which greatly saves the data writing time. The screen switching can be completed in a shorter clock cycle, which helps to improve the flickering phenomenon and thus improve the display effect. Moreover, since the data writing time is reduced, the light emission time can be increased accordingly, which helps to ensure the maximum brightness of the light emission and the reliability of grayscale expansion. On the other hand, the data voltage and the sweep frequency signal are set separately and do not affect each other, which helps to improve the reliability of signal transmission.

[0094] Optionally, continue to refer to Figure 5 and Figure 8The first voltage writing unit 102 includes a pre-charge sub-unit 111 and a data voltage writing sub-unit 112. The first end of the pre-charge sub-unit 111 is connected to the data line, and the second end of the pre-charge sub-unit 111 is connected to the first end of the data voltage writing sub-unit 112. The second end of the data voltage writing sub-unit 112 is connected to the first end of the coupling unit 106. The first end of the storage unit 107 is connected to the second end of the pre-charge sub-unit 111, and the second end of the storage unit 107 is connected to the first power line L1. The first driving module 10 also includes a compensation unit 108, which is connected between the control terminal G1 and the second terminal of the first driving unit 101. The first end of the third voltage writing unit 104 is connected to the initialization signal line, and the second end of the third voltage writing unit 104 is connected to the control terminal G1 of the first driving unit 101. The first driving module 10 also includes a reset unit 105, which is connected between the reset signal line and the control terminal G2 of the second driving module 20.

[0095] Figure 11 A flowchart of another pixel driving circuit driving method provided in an embodiment of the present invention is shown below. Figure 11 The voltage writing stage includes an initialization stage, a data writing and threshold compensation stage, and a voltage normalization stage. The specific driving method of this pixel driving circuit includes:

[0096] S110. During the previous display frame, control the first voltage writing unit to write the data voltage corresponding to the next display frame to the storage unit.

[0097] S1201. During the initialization phase, the control third voltage writing unit writes the initialization voltage transmitted on the initialization signal line to the control terminal of the first driving unit.

[0098] S1202. During the data writing and threshold compensation stage, the control compensation unit compensates the threshold voltage of the first driving unit, and simultaneously controls the second voltage writing unit to transmit the first level of the sweep frequency signal to the first end of the coupling unit, and controls the data voltage writing subunit to write the data voltage stored on the storage unit to the first end of the coupling unit.

[0099] S1203. During the voltage normalization stage, the second voltage writing unit is controlled to transmit the second level of the sweep frequency signal to the first end of the coupling unit, so as to control the coupling unit to couple the data voltage and the sweep frequency signal to the control end of the first driving unit.

[0100] S210. During the reset phase, the control reset unit transmits the reset voltage transmitted on the reset signal line to the control terminal of the second drive module.

[0101] S130. During the light-emitting stage, the voltage of the control terminal of the second driving module is controlled according to the data voltage and the frequency sweep signal to control the light-emitting time of the light-emitting module.

[0102] Specifically, Figure 11 For the specific working process of the driving method shown, please refer to the documentation. Figure 8 The relevant descriptions will not be repeated here.

[0103] Optionally, embodiments of the present invention also provide a display panel, which includes the pixel driving circuit provided in embodiments of the present invention. Figure 12 This is a schematic diagram of a display panel provided in an embodiment of the present invention. This display panel can be applied to tablets, mobile phones, watches, wearable devices, as well as automotive displays, camera displays, televisions, computer screens, and all other display-related devices. Since this display panel includes the pixel driving circuit provided in any embodiment of the present invention, it also possesses the beneficial effects described in any embodiment of the present invention.

[0104] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0105] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel driving circuit, characterized in that, include: The system comprises a first driving module, a second driving module, and a light-emitting module. The output terminal of the first driving module is connected to the control terminal of the second driving module. The second driving module and the light-emitting module are connected between a first power line and a second power line. The first driving module includes a first driving unit, a first voltage writing unit, a second voltage writing unit, a third voltage writing unit, a coupling unit, and a storage unit. The first voltage writing unit is connected between a data line and a first end of the coupling unit. The storage unit is connected to an intermediate node of the first voltage writing unit. The first voltage writing unit is used to write the data voltage corresponding to the next display frame to the storage unit during the previous display frame and to transmit the data voltage to the first end of the coupling unit during the next display frame. The second voltage writing unit is used to transmit a sweep frequency signal to the first end of the coupling unit during the voltage writing stage. The coupling unit is used to couple the data voltage and the sweep frequency signal to the control end of the first driving unit. The third voltage writing unit is used to transmit a fixed voltage to the control end of the first driving unit. The first driving unit is connected between the first power line and the control terminal of the second driving module, and is used to control the voltage of the control terminal of the second driving module according to the data voltage and the frequency sweep signal, so as to control the light emission time of the light-emitting module. The first voltage writing unit includes a pre-charge sub-unit and a data voltage writing sub-unit; The first end of the pre-charge subunit is connected to the data line, the second end of the pre-charge subunit is connected to the first end of the data voltage writing subunit, the second end of the data voltage writing subunit is connected to the first end of the coupling unit, the control end of the pre-charge subunit is connected to the first scan line, and the control end of the data voltage writing subunit is connected to the second scan line. The first end of the storage unit is connected to the second end of the precharge sub-unit, and the second end of the storage unit is connected to the first power line; The connection node between the pre-charge subunit and the data voltage writing subunit is the intermediate node of the first voltage writing unit, and the storage unit is connected between the first power line and the intermediate node. The pre-charge subunit is used to write the data voltage corresponding to the next display frame into the storage unit during the previous display frame. At this time, the data voltage writing subunit is in the off state. When switching to the next display frame, the data voltage writing subunit is turned on and the data voltage stored in the storage unit is transmitted to the first end of the coupling unit.

2. The pixel driving circuit according to claim 1, characterized in that, The precharge sub-unit includes a first transistor, the data voltage write sub-unit includes a second transistor, the storage unit includes a first capacitor, the first terminal of the first transistor is connected to the data line, the second terminal of the first transistor is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to the first end of the coupling unit, the first capacitor is connected between the second terminal of the first transistor and the first power line, the gate of the first transistor is connected to the first scan line, and the gate of the second transistor is connected to the second scan line.

3. The pixel driving circuit according to claim 1, characterized in that, The fixed voltage includes the power supply voltage. The first end of the third voltage writing unit is connected to the first power line, and the second end of the third voltage writing unit is connected to the control terminal of the first driving unit. The third voltage writing unit is used to transmit the power supply voltage transmitted on the first power line to the control terminal of the first driving unit during the voltage writing stage.

4. The pixel driving circuit according to claim 1, characterized in that, The first driving module further includes a compensation unit and a reset unit. The compensation unit is connected between the control terminal and the second terminal of the first driving unit, and the reset unit is connected between the reset signal line and the control terminal of the second driving module. The reset unit is used to transmit the reset voltage transmitted on the reset signal line to the control terminal of the second driving module during the reset phase.

5. The pixel driving circuit according to claim 4, characterized in that, The fixed voltage includes an initialization voltage. The first end of the third voltage writing unit is connected to the initialization signal line, and the second end of the third voltage writing unit is connected to the control terminal of the first driving unit. The third voltage writing unit is used to transmit the initialization voltage transmitted on the initialization signal line to the control terminal of the first driving unit during the voltage writing stage.

6. The pixel driving circuit according to claim 5, characterized in that, The first driving unit includes a third transistor, the compensation unit includes a fourth transistor, the third voltage writing unit includes a fifth transistor, the second voltage writing unit includes a sixth transistor, the reset unit includes a seventh transistor, and the coupling unit includes a second capacitor; The first terminal of the third transistor is connected to the first power line, the second terminal of the third transistor is connected to the control terminal of the second driving module, the first terminal of the fourth transistor is connected to the second terminal of the third transistor, the second terminal of the fourth transistor is connected to the gate of the third transistor, and the gate of the fourth transistor is connected to the third scan line; the first terminal of the fifth transistor is connected to the initialization signal line, the second terminal of the fifth transistor is connected to the gate of the third transistor, and the gate of the fifth transistor is connected to the fourth scan line; the first terminal of the sixth transistor is connected to the sweep frequency signal, the second terminal of the sixth transistor is connected to the first terminal of the second capacitor, the second terminal of the second capacitor is connected to the gate of the third transistor, and the gate of the sixth transistor is connected to the fifth scan line; the first terminal of the seventh transistor is connected to the reset signal line, the second terminal of the seventh transistor is connected to the control terminal of the second driving module, and the gate of the seventh transistor is connected to the sixth scan line.

7. The pixel driving circuit according to claim 5, characterized in that, The initialization signal line is multiplexed as the reset signal line.

8. The pixel driving circuit according to claim 1, characterized in that, The second driving module includes a second driving unit. The control terminal of the second driving unit is connected to the output terminal of the first driving module as the control terminal of the second driving module. The first terminal of the second driving unit is connected to the power supply voltage transmitted on the first power line. The second terminal of the second driving unit is connected to the first terminal of the light-emitting module. The second terminal of the light-emitting module is connected to the second power line.

9. The pixel driving circuit according to claim 8, characterized in that, The second driving module further includes a light-emitting control unit, which is connected between the first power line and the first end of the second driving unit, and the control terminal of the light-emitting control unit is connected to the light-emitting control signal line.

10. The pixel driving circuit according to claim 9, characterized in that, The second driving unit includes an eighth transistor, and the light-emitting control unit includes a ninth transistor. The first terminal of the ninth transistor is connected to the first power line, the second terminal of the ninth transistor is connected to the first terminal of the eighth transistor, the second terminal of the eighth transistor is connected to the first terminal of the light-emitting module, the gate of the eighth transistor is connected to the output terminal of the first driving module, and the gate of the ninth transistor is connected to the light-emitting control signal line.

11. The pixel driving circuit according to claim 2, characterized in that, The control terminal of the second voltage writing unit is connected to the fifth scan line, and the control terminal of the third voltage writing unit is connected to the fourth scan line. The first scan line, the second scan line, the fourth scan line, and the fifth scan line are configured to transmit scan line numbers to satisfy the following: The precharged sub-unit is turned on before the voltage writing phase; During the voltage writing phase, the data voltage writing subunit, the second voltage writing unit, and the third voltage writing unit are turned on, but the data voltage writing subunit and the second voltage writing unit are not turned on simultaneously. During the light-emitting phase, the second driving module is turned on.

12. A driving method for a pixel driving circuit, characterized in that, The pixel circuit includes a first driving module, a second driving module, and a light-emitting module. The output terminal of the first driving module is connected to the control terminal of the second driving module. The second driving module and the light-emitting module are connected between a first power line and a second power line. The first driving module includes a first driving unit, a first voltage writing unit, a second voltage writing unit, a third voltage writing unit, a coupling unit, and a storage unit. The first voltage writing unit is connected between a data line and a first terminal of the coupling unit. The storage unit is connected to an intermediate node of the first voltage writing unit. The first driving unit is connected between the first power line and the control terminal of the second driving module. The driving method of the pixel driving circuit includes: During the previous display frame, the first voltage writing unit is controlled to write the data voltage corresponding to the next display frame to the storage unit; During the next display frame, in the voltage writing phase, the third voltage writing unit is controlled to transmit a fixed voltage to the control terminal of the first driving unit, and the first voltage writing unit is controlled to transmit the data voltage to the first terminal of the coupling unit. Then, the second voltage writing unit is controlled to transmit a sweep signal to the first terminal of the coupling unit, so as to control the coupling unit to couple the data voltage and the sweep signal to the control terminal of the first driving unit. During the light emission stage, the voltage of the control terminal of the second driving module is controlled according to the data voltage and the frequency sweep signal to control the light emission time of the light emission module; The first voltage writing unit includes a pre-charge sub-unit and a data voltage writing sub-unit; The first end of the pre-charge subunit is connected to the data line, the second end of the pre-charge subunit is connected to the first end of the data voltage writing subunit, the second end of the data voltage writing subunit is connected to the first end of the coupling unit, the control end of the pre-charge subunit is connected to the first scan line, and the control end of the data voltage writing subunit is connected to the second scan line. The first end of the storage unit is connected to the second end of the precharge sub-unit, and the second end of the storage unit is connected to the first power line; The connection node between the pre-charge subunit and the data voltage writing subunit is the intermediate node of the first voltage writing unit, and the storage unit is connected between the first power line and the intermediate node. The pre-charge subunit is used to write the data voltage corresponding to the next display frame into the storage unit during the previous display frame. At this time, the data voltage writing subunit is in the off state. When switching to the next display frame, the data voltage writing subunit is turned on and the data voltage stored in the storage unit is transmitted to the first end of the coupling unit.

13. The driving method for the pixel driving circuit according to claim 12, characterized in that, The first driving module further includes a compensation unit, which is connected between the control terminal and the second terminal of the first driving unit. The first terminal of the third voltage writing unit is connected to the initialization signal line, and the second terminal of the third voltage writing unit is connected to the control terminal of the first driving unit. The voltage writing stage includes an initialization stage, a data writing and threshold compensation stage, and a voltage normalization stage. The specific steps of the pixel driving circuit in the voltage writing stage include: During the initialization phase, the third voltage writing unit is controlled to write the initialization voltage transmitted on the initialization signal line to the control terminal of the first driving unit. During the data writing and threshold compensation stage, the compensation unit is controlled to compensate the threshold voltage of the first driving unit, while the second voltage writing unit is controlled to transmit the first level of the sweep frequency signal to the first end of the coupling unit, and the data voltage writing subunit is controlled to write the data voltage stored on the storage unit to the first end of the coupling unit. During the voltage normalization stage, the second voltage writing unit is controlled to transmit the second level of the sweep frequency signal to the first terminal of the coupling unit, so as to control the coupling unit to couple the data voltage and the sweep frequency signal to the control terminal of the first driving unit.

14. The driving method for the pixel driving circuit according to claim 13, characterized in that, The first driving module further includes a reset unit connected between the reset signal line and the control terminal of the second driving module. After the voltage writing stage, the driving method of the pixel driving circuit further includes: During the reset phase, the reset unit controls the reset voltage transmitted on the reset signal line to the control terminal of the second drive module.

15. A display panel, characterized in that, Includes the pixel driving circuit as described in any one of claims 1-11.

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