A dual-latch display system and method

Abstract

The application discloses a double-latch display system and method, and belongs to the technical field of LED display, which comprises a serial-parallel converter, an instruction decoder, a first display data latch, a second display data latch and an output driver.The serial-parallel converter is used for converting input serial data into parallel data.The instruction decoder is used for pulling the LOCK signal to a high level and keeping it until the next instruction recognition process starts.The first display data latch is used for receiving the parallel data and the LOCK signal and latching the parallel data at the rising edge of the LOCK signal.The second display data latch is used for latching the latched data output by the first display data latch at the falling edge of the LOCK signal.The output driver is used for receiving the output data of the second display data latch and driving the LED.The application solves the contradiction between the display quality and the power consumption of high-speed moving images in the prior art by setting an image data latching display, adopting a double-buffering area alternating display mode and using a shared cathode LED display device, so that clear and low-power-consumption display of high-speed moving images is realized.

Description

Technical Field

[0001] This invention relates to the field of LED display technology, and more specifically, to a dual-latch display system and method. Background Technology

[0002] LED (Light Emitting Diode) displays are high-efficiency, high-brightness, and high-reliability display devices widely used in various applications. However, due to limitations in their working principle, LED displays have certain limitations in terms of grayscale and refresh rate. In the field of electronic displays, high grayscale and high refresh rate display technologies have always been a research hotspot.

[0003] Currently, there are two main methods to improve the grayscale and refresh rate of LED displays: one is to adjust the LED brightness through PWM (Pulse Width Modulation); the other is to increase the refresh rate by increasing the LED driving frequency. However, this method leads to increased energy consumption and more complex driving circuitry. Insufficient grayscale levels can result in insufficient color gradation or uneven color smoothness, failing to fully display the colors of the video and significantly reducing the LED display effect. If the refresh rate is too low, obvious horizontal stripes will appear when shooting with a high-definition camera or mobile phone, resulting in poor image quality. Of course, even some high refresh rate screens can sometimes produce noticeable stripes when photographed, due to factors such as lighting flicker in the shooting environment. Prolonged viewing of a low refresh rate, low grayscale screen can damage the human eye.

[0004] The common power supply method is common anode power supply. Originally, common anode power supply involved connecting the anodes of diodes together for a unified power supply. Therefore, it's necessary to meet the voltage requirements of the diodes with the highest voltage requirements in parallel circuits. For diodes with lower voltage requirements, voltage divider resistors must be added, which generate power consumption and heat. If a clear display of high-speed moving images is required, the current technology results in relatively high overall power consumption. Summary of the Invention

[0005] 1. Technical problems to be solved

[0006] To address the contradiction between display quality and power consumption in high-speed moving images in existing technologies, this invention provides a dual-latch display system and method. By setting up image data latch display, adopting a dual-buffer alternating display method, and using LED display devices with a shared cathode, clear and low-power display of high-speed moving images is achieved.

[0007] 2. Technical Solution

[0008] One aspect of this specification provides a dual-latch display system, including: a serial-to-parallel converter for converting input serial data into parallel data; an instruction decoder for pulling a LOCK signal high and holding it until the start of the next instruction recognition process; a first display data latch for receiving parallel data and the LOCK signal, and latching the parallel data on the rising edge of the LOCK signal; a second display data latch for latching the latched data output by the first display data latch on the falling edge of the LOCK signal; and an output driver for receiving the output data from the second display data latch and driving an LED.

[0009] Furthermore, the clock generation module generates the serial data clock SCLK, the parallel data clock PCLK, and the latch enable signal LE.

[0010] Furthermore, the LED array is a common cathode array.

[0011] Another aspect of the embodiments of this specification also provides a dual-latch display method, comprising: outputting a serial signal SIN and converting it into a parallel signal through a serial-to-parallel converter; inputting the parallel signal into a first display data latch; latching the parallel data in the first display data latch at the rising edge of the LOCK signal; latching the output data of the first display data latch in the falling edge of the LOCK signal; and receiving the output data of the second display data latch and driving the LED display.

[0012] Furthermore, on the rising edge of the LOCK signal, the first display data latch latches the input data DATA that has been transmitted.<N-1:0> _A; On the falling edge of the LOCK signal, the second display data latch latches the data in the first display data latch and displays it; simultaneously with the data in the second display data latch, new data DATA is transmitted.<N-1:0> _B;DATA<N-1:0> After _B is transmitted, the first display data latch latches DATA.<N-1:0> _B; DATA in the second display data latch<N-1:0> After _A ends, the second display data latch latches the DATA in the first display data latch.<N-1:0> _B, and display the output; repeat all operations, continue to latch the newly transmitted data, and alternately display the output.

[0013] Furthermore, the data bit width output by the first display data latch and the second display data latch is 2M, where M is a positive integer.

[0014] Furthermore, the 2M bit-width data is broken down into 2M groups, each group containing M high-order bits and M low-order bits.

[0015] Furthermore, the 2M-bit data is grouped in such a way that the M adjacent bits are taken as the high-order bits and the M subsequent adjacent bits are taken as the low-order bits; that is, the first to the Mth bits are taken as the high-order bits of the first group, and the (M+1)th to the 2Mth bits are taken as the low-order bits of the first group; the (2M+1)th to the 3Mth bits are taken as the high-order bits of the second group, and the (3M+1)th to the 4Mth bits are taken as the low-order bits of the second group; and so on, to obtain 2M groups of data.

[0016] Furthermore, the 2M groups of data, after being grouped, are output through cascaded circuits and control signals to form control signals for each pixel, thereby driving the light-emitting diodes of each pixel to display the image.

[0017] Furthermore, the first display data latch latches data on the rising edge of the LOCK signal; the second display data latch latches the output data of the first display data latch on the falling edge of the LOCK signal.

[0018] 3. Beneficial effects

[0019] Compared with the prior art, the advantages of this invention are:

[0020] (1) Using a dual latch register can achieve multi-bit data input. In LED displays, each bit of data corresponds to a grayscale level. Multi-bit data input can achieve a higher grayscale value, thereby improving the grayscale of the display;

[0021] (2) With the same amount of input data, the three-segment structure of the dual latch register can achieve a higher refresh rate. This is because using the dual latch register allows the LED driver chip to output more data at the same time. Moreover, the three-segment structure of the dual latch register can ensure the stability of the data and reduce the possibility of jitter and interference, thereby making the LED display refresh frequency higher and thus appearing smoother. In summary, using the dual latch register can simultaneously improve the grayscale and refresh rate of the LED, achieve better visual effects, and reduce cost and power consumption.

[0022] In summary, image data is first converted from serial to parallel to generate parallel data. Then, with the coordination of clock and latch control signals, a two-stage latch performs pipelined latching to accurately acquire complete image data and achieve alternating display of dual buffers. This avoids image tearing and frequent refreshes, enabling continuous and clear display of high-speed moving images. Simultaneously, the use of a common-cathode LED display array and group transmission simplifies system complexity and reduces display driver power consumption. This dual-latch display method and system can significantly reduce system power consumption while ensuring display quality, achieving low-power, clear display of high-speed moving images. Attached Figure Description

[0023] Figure 1 This is a timing diagram illustrating the data transmission and display process using existing technologies.

[0024] Figure 2 This is a schematic diagram of data grouping according to an embodiment of the present invention;

[0025] Figure 3 This is a flowchart of an embodiment of the present invention;

[0026] Figure 4 This is a structural block diagram of an embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram illustrating the timing of data transmission and data display according to an embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of data transmission and data grayscale 3 according to an embodiment of the present invention;

[0029] Figure 7 This is a schematic diagram of grayscale data transmission and display using existing technologies. Detailed Implementation

[0030] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0031] Glossary

[0032] A serial-to-parallel converter (SPC) is a circuit used for signal conversion, which can convert input serial data into parallel data output. In this scheme, the SPC's function is as follows: it receives serial data of the image signal at the input end; it converts the input serial data into parallel data through parallel conversion processing; and it outputs the converted data in parallel at the output end. Converting the input serial signal into a parallel signal can achieve the following functions: improving the data transmission rate to meet the needs of displaying a large number of dynamic images; accurately latching complete image data in conjunction with a parallel latching mechanism; and providing a parallel data source for subsequent parallel display driving. Therefore, in this scheme, the SPC acts as a bridge between serial and parallel signals, realizing high-speed serial-to-parallel signal conversion to meet the needs of subsequent parallel latching and driving, thereby enabling continuous low-power display of high frame rate dynamic images.

[0033] An instruction decoder is a circuit used to parse and decode input control instructions. In this scheme, the instruction decoder's function is to: receive system control instructions at its input terminal; parse the instructions and extract the timing signals for controlling the display; and output a LOCK signal as the control signal for the subsequent display latch. Specifically, the instruction decoder performs the following functions: receives various system control instructions, including latch display control; identifies the control sequence number or code for the latch display; generates a LOCK control signal based on the latch display instructions; and drives the LOCK signal to appropriate timing and level as the control signal for the subsequent latch. Therefore, in this scheme, the instruction decoder plays the role of instruction identification and LOCK control signal generation to produce accurate display latch control signals, thereby achieving accurate latching of display data and ensuring the normal and reliable operation of the system.

[0034] A display data latch is a circuit device used to buffer and temporarily store display data. This solution includes two levels of display data latches: The first display data latch latches the parallel-converted image display data at the rising edge of the LOCK control signal. The second display data latch latches the data output by the first display data latch at the falling edge of the LOCK control signal. The function of the display data latch is: to receive parallel-formatted image display data at its input; to latch the input data according to the latch enable signal at a defined edge of the clock signal; and to continue outputting the latched data until it is replaced by new data. Through the combined use of the two-level latches, alternating display of image data with dual buffers can be achieved, avoiding image tearing and enabling continuous and clear display of moving images. Therefore, the display data latch plays a crucial role in accurately latching and buffering display data in this solution, and is the core component for achieving low-power, high-speed dual-latch display.

[0035] The rising edge refers to the instant a digital signal transitions from a low level to a high level. In this scheme, the rising edge specifically refers to the transition moment when the LOCK control signal changes from a low level to a high level. The function of the rising edge is to trigger the first display data latch to perform a latching operation. That is, when the first display data latch detects the rising edge of the LOCK signal, it latches the data input at the current moment. Using rising edge triggering for display latching ensures that the complete image data of each frame is accurately latched, avoiding image tearing caused by latching incomplete frames. Therefore, the rising edge is a very important timing control signal for this scheme, ensuring that each frame of data is accurately and reliably latched, thereby achieving continuous and clear display of high-speed moving images.

[0036] The serial clock signal (SCLK) plays a crucial role in this scheme. It provides the clock for the input serial image data and controls the timing of the serial image data transmission. Specifically, SCLK performs the following functions: it is generated by the clock generation module and synchronized with the serial image data; it operates at a specific clock frequency on the serial data lines; serial data is transmitted bit-by-bit on the data lines according to its rising or falling edge; and it coordinates the transmission rate of the serial data. Therefore, SCLK is a critical clock signal for providing the serial data timing. By sampling this clock signal, the serial-to-parallel converter can correctly acquire the serial data and convert it into parallel data for output. The existence of SCLK ensures that the serial signal is reliably transmitted with correct timing, thus providing the correct data source for subsequent parallel conversion and display operations.

[0037] The parallel clock signal (PCLK) plays a crucial role in this scheme. It provides a clock for the parallel display data and controls the timing of its transmission. Specifically, PCLK performs the following functions: it is generated by the clock generation module and synchronized with the parallel display data; it operates at a specific clock frequency on the parallel data lines; parallel data is transmitted on the data lines according to its rising or falling edge; and it coordinates the transmission rate of the parallel data. Therefore, PCLK is a key clock signal for providing the timing of the parallel data. The display data latch, by sampling this clock signal, can correctly acquire the parallel data and latch it at the clock edge. The existence of PCLK ensures that the parallel display data is transmitted and latched in the correct timing, thereby achieving precise control over the high-speed parallel display data.

[0038] LE stands for Latch Enable. In this scheme, the LE signal triggers the display data latch to perform a latching operation. Specifically, when the LE signal is valid, the display data latch is allowed to latch at the edge of the clock signal. Specifically, LE performs the following functions: it is generated by the clock generation module according to the display data timing; it remains valid during parallel display data transmission; it becomes invalid when display data transmission ends; and the display data latch performs a latching operation when it detects a valid LE signal. Therefore, LE is a key control signal determining the latching timing of the display data latch. Its presence ensures that the display data is latched at the correct time, thereby achieving precise double-buffered display control.

[0039] A common cathode array is an LED display assembly method. Its characteristics include: multiple LEDs sharing a common cathode terminal; and each LED's anode connected to an independent control line. The advantages of using a common cathode array include: simplified control circuitry and reduced complexity; control of all LEDs by controlling a shared cathode voltage; more precise anode control; and the ability to control each LED individually. In this solution, the benefits of using a common cathode LED array are: simplified driving circuitry, reduced system cost and power consumption; efficient control of the on / off state of each pixel; and compatibility with the parallel transmission and driving of display image data. Therefore, using a common cathode LED array can better realize the parallel control and driving mechanism of this solution, achieving the advantages of low power consumption, precise control, and low cost.

[0040] SIN stands for Serial Input. In this solution, SIN carries the input serial image display data. Specifically, SIN performs the following functions: it carries the digital video data of the image frames to be displayed on the screen; the data is transmitted serially on the SIN signal line; transmission is synchronized according to the serial clock SCLK; and the data format can be a serial signal converted from parallel data. The existence of SIN allows image display data to be input into this solution in serial format. The serial-to-parallel converter samples and converts SIN to obtain parallel data for subsequent display operations. Therefore, SIN is the data input port of the display system, providing source data for subsequent image processing and display. Its serial data input enables high-speed data transmission.

[0041] Bit width refers to the number of binary bits that a data line in a digital system can transmit or process simultaneously. In this solution, the data bit width specifically refers to the bit width of parallel display data, i.e., the number of bits that a parallel data line can transmit simultaneously. Increasing the bit width offers the following advantages: improved data transmission rate, meeting the needs of displaying large amounts of dynamic images; support for higher display resolution and color depth; and the ability to drive more pixels simultaneously, enabling large-size splicing displays. This solution uses a 2M bit width, meaning: 2 million bits of parallel display data can be transmitted at a time; significantly improved transmission bandwidth and display capabilities; and the ability to drive a larger number of pixels, achieving high-resolution, large-size LED displays. Therefore, bit width is one of the key parameters for achieving high-capacity, high-speed display in this solution, and the 2M bit width supports the system's high-speed dynamic display requirements.

[0042] High-order bit data refers to the data with the highest bit order in each group after the display data is divided into multiple groups. Specifically, high-order bit data represents the first bit of each group after the 2M bits of display data are grouped according to certain rules. For example, if the data is divided into 2M groups, each containing M high-order bits and M low-order bits, then the high-order bit data is the first M bits of each group. High-order bit data has the following characteristics: it carries important information about the on / off state of pixels in the image data; it has a relatively high bit width, corresponding to the key content of the displayed image; it works with low-order bit data to represent the complete control information of each pixel; and it is usually connected to the high-active control terminal of the pixel. Therefore, high-order bit data plays a crucial role in image display during group transmission, typically determining the on / off state and color control of pixels, and is the key data part for achieving correct display.

[0043] Low-order data refers to the data with the lowest bit order in each group after the display data is divided into multiple groups. Specifically, low-order data represents the last bit of each group within the 2M-bit display data set according to a certain rule. For example, if the data is divided into 2M groups, each containing M high-order bits and M low-order bits, then the low-order data is the last M bits of each group. Low-order data has the following characteristics: it carries pixel details and auxiliary information from the image data; it has a lower bit width, corresponding to the detailed content of the displayed image; it works with high-order data to represent the complete control information for each pixel; and it is usually connected to the low-signal control terminal of the pixel. Therefore, low-order data plays an auxiliary role in image display during group transmission, providing additional pixel control information and, together with high-order data, determining the displayed content, making it an important component for achieving correct display.

[0044] Cascading circuits refer to a circuit method that connects multiple identical circuit devices together to expand the system's processing capacity. In this scheme, cascading mainly refers to connecting multiple display data latches together; connecting their input and output terminals in series; and achieving pipelined transmission of display data. The advantages of using cascading circuits include: expanding data processing capabilities and achieving higher data bit widths; pipelined operation, improving processing efficiency; and modular connection, simplifying system design. For example, the two-stage display data latches in this scheme are connected in a cascaded manner to transmit and latch display data with double the bit width. Therefore, cascading circuits in this scheme expand the display data processing capability to support higher-speed and higher-bandwidth large-volume display data transmission.

[0045] Example 1

[0046] This invention provides a high grayscale and high refresh rate dual-latch display principle, which enables clear display of high-speed moving images. It solves the problems of grayscale and refresh rate in LED displays.

[0047] Figure 1 This is a timing diagram illustrating the data transmission and display of existing technologies, such as... Figure 1 As shown, the existing technology, which transmits the high-order data first and then the low-order data, does not make good use of display time and data transmission time. In existing technologies, image data is transmitted serially, separating the high-order and low-order bits of the image data. For example... Figure 1 As shown, the high-order data DATA is transmitted first.<N-1:0> After _A, transmit the lower-order data DATA.<N-1:0> _B. The display driver module can only start driving the display panel to display the image after both high and low bit data have been transmitted. This transmission method has the following problems: low data transmission efficiency. Because the display can only start after the low bit data is transmitted, the display panel is in a waiting state for a period of time during the data transmission cycle, and cannot be fully utilized; poor display quality of moving images. In high-speed moving image display scenarios, due to the long data transmission cycle and the time interval between high and low bit data, image damage and tearing may occur, reducing display quality; high system power consumption. The long waiting time will cause the display driver system to operate in a high-power state for a long time, increasing system power consumption. To address the above problems, this invention adopts a dual-buffer alternating transmission and display method, which can effectively improve data transmission efficiency, reduce system power consumption, and improve the display quality of high-speed moving images.

[0048] This embodiment provides a high grayscale, high refresh rate dual-latch display method. The principle mainly includes the following steps:

[0049] The input serial signal SIN is converted into a parallel signal by a serial-to-parallel converter and then sampled. The parallel signal is temporarily stored in the first display data latch via high-speed transmission. During the refresh cycle of each line, the LE control instruction generates a LOCK signal through the instruction decoder. When the rising edge of the LOCK signal arrives, the pixel data of the current line in the first display data latch is latched and transmitted to the second display data latch. When the falling edge of the LOCK signal arrives, the second display data latch sends the pixel data to the driver for display. At the same time, the first display data latch is responsible for receiving and buffering the pixel data of the next line. Through the above working principle, the two latches work alternately, one responsible for displaying the current line and the other responsible for acquiring the next line, realizing double buffering and ensuring accurate and reliable data transmission. Compared with the traditional single-buffering method, this embodiment, by setting up dual latches, can hide the data loading time, effectively improve the refresh rate, and ensure the smoothness of moving image display. At the same time, the use of high-speed transmission and sampling processing can display high grayscale images, achieving a clear image display effect. This display method can effectively solve the problems of low refresh rate and blurry moving images in existing technologies, and achieve clear and smooth high-speed moving image display.

[0050] The dual-latch register outputs data with a width of 2M bits. This data is broken down into 2M groups, resulting in a total output data width of 2M bits. This data is not simply divided into 2M equal groups, but rather recombined and divided in a specific order. The total data is then concatenated bit by bit, expanding and concatenating the original 2M bits; where M bits represent the high-order data (M bits). Figure 2 Data11 to Data6 shown in the figure, M bits are the low-order data ( Figure 2 The data shown is Data5 to Data0. Taking a total of 12 bits as an example, the specific method is: to shuffle and recombine the total 12 bits according to certain rules and expand it into a longer sequence. For example, repeat the recombination to form 12 x 64 = 768 bits. Then, this 768 bits is regrouped, and the first 6 bits of each group are taken as the high-order data and the last 6 bits are taken as the low-order data. In this way, it is divided into 64 groups, each group has 12 bits, of which 6 bits are high-order data and 6 bits are low-order data. For a total of 6 bits, a similar operation is performed + expanded and recombine to form a longer sequence, and then grouped. Through this "expansion and recombination + regrouping" method, the required number of high-order and low-order data groups can be divided from a shorter total bit width; taking a 6-bit data as an example, the 6-bit data is shuffled into 8 (23) groups, with 3 bits of high-order data and 3 bits of low-order data.

[0051] Figure 2 This is a schematic diagram of data grouping according to an embodiment of the present invention, as shown below. Figure 2As shown, the data is broken down into several parts. Specifically, the 2M-bit data is broken down into 2M groups. After breaking it down into 2M groups, the M-bit high-order data and M-bit low-order data are combined. After combination, each group of data consists of one high-order data and one low-order data. The data after high-low order combination is processed by LE... After the control signal is received, a control signal for each pixel is generated. This method can shorten the data transmission time required for each pixel and can simultaneously transmit information from more pixels, significantly improving the refresh rate of the LED display. Taking 12-bit data as an example, the data is broken down into 64 groups. After being broken down into 64 groups, the 6-bit high-order data is combined with the 6-bit low-order data.

[0052] The control signal is sent to the LED dot matrix through the LED driver chip to complete the refresh and grayscale display of the LED screen.

[0053] This solution utilizes a method of shuffling data and combining the high and low bits. This approach shortens the data transmission time for each pixel and allows for the simultaneous transmission of information from more pixels, significantly improving the refresh rate of the LED display. Typically, a traditional LED display requires a long refresh time to illuminate the entire screen because a single latch needs to refresh multiple times to fully illuminate the LED panel. This solution uses a dual-latch principle, allowing for rapid alternation between two latches to transmit data, thus significantly reducing the refresh time for each LED. While one register displays data, the other register stores the next set of serial data, saving write time. Adding a set of latches and integrating dual latches improves the control precision and stability of the LED display, thereby achieving higher grayscale performance.

[0054] The dual-latch display principle utilizes two latches in each row's refresh cycle to achieve rapid switching of displayed content, thereby improving the refresh speed and performance of the LED display screen. Specifically, the dual-latch display principle works as follows: In each row's refresh cycle, the LE control command generates a LOCK signal through the command decoder. The first display data latch is responsible for latching the pixel data of the current row. When the control signal... When the rising edge arrives, data will be transferred from the first display data latch to the second display data latch, and will be stored by the second display data latch; when the control signal arrives... When the rising edge arrives, the second display data latch sends data to the driver for display. Simultaneously, the first display data latch receives and buffers the pixel data for the next line, and so on. In this way, the dual latches can utilize almost all available refresh time to transmit pixel data, maximizing the refresh rate and performance of the LED display.

[0055] The specific operation process involves storing the data of each pixel simultaneously in two latches. When refreshing the next frame, the data in the second display data latch is first refreshed onto the display screen, and then the data in the first display data latch is stored in the second display data latch. This splits the signal, which originally had only one clock cycle, into two clock cycles, thereby improving grayscale. By adding a set of latches, integrating dual latches can effectively reduce errors in the transmission of control signals and can simultaneously control the state of more LEDs, achieving higher grayscale performance. Dual latches allow for more stable signal storage, avoiding data errors, improving the grayscale performance of LEDs, effectively reducing image flicker, and improving image stability. Therefore, adding a set of latches and integrating dual latches can improve the grayscale of LEDs.

[0056] In traditional LED dot matrix displays, each pixel typically requires 3-4 bits of data to control its brightness and color. Using a traditional row-column driving method, the data for each pixel needs to be transmitted separately to the designated row and column, a process that takes time. Addressing the shortcomings of the conventional method of transmitting high-order data first and then low-order data, this invention breaks down the display data into multiple parts and combines the high-order and low-order data according to time. This allows the time spent displaying high-order data to be used for data transmission, or in other words, the time spent transmitting data to display high-order data. This perfect coordination of data transmission and display allows different data from the same pixel to be transmitted to different locations simultaneously, and data from different pixels can also be transmitted simultaneously, thus shortening transmission time and effectively increasing the display refresh rate. A higher refresh rate results in a more stable image and less visual flicker. It also effectively reduces the probability of data errors, improving the reliability of data transmission. By controlling the LED's conduction frequency through this breakdown method, the light output of the LED becomes more stable and consistent, avoiding light output distortion or insufficient brightness caused by uneven conduction, thereby enhancing the reliability and stability of the LED.

[0057] LED displays require precise control of each LED within a very short time to achieve grayscale adjustment and image display effects. Both traditional matrix-based driving methods and the more commonly used dot-matrix driving methods rely on latches to temporarily store various signals from the host processor. This ensures stable signal delivery to the LEDs without errors and allows for more accurate control of LED brightness. Common-anode technology, due to the need for voltage divider resistors, struggles to achieve this level of energy efficiency. With common-cathode technology, the operating voltages of red, green, and blue LEDs differ, with red LEDs operating at lower voltages than green and blue LEDs. In a common-cathode circuit, red, green, and blue LEDs are powered separately, allowing for precise voltage control and eliminating the need for voltage divider resistors.

[0058] Figure 3 This is a flowchart of an embodiment of the present invention. Figure 4 This is a structural block diagram of an embodiment of the present invention; as shown below. Figure 3 and Figure 4 As shown, this invention employs a common-cathode LED driving method to reduce system power consumption and improve the reliability of the display device. In this technical solution, data DATA_REG <x>The output driver transmits data to the LEDs, with drivers 0-15 connected to the anodes of the LEDs respectively. Simultaneously, the cathodes of all LEDs are connected together via a switch VLINE. The advantages of this common-cathode structure are: it reduces the LED operating voltage, typically from 4.2V-5V to 2.8V-3.3V, directly reducing power consumption by over 25%; reduced LED power consumption lowers the display temperature, improving LED stability and lifespan. LED stability and lifespan are inversely proportional to temperature; it eliminates the need for independent cathode resistors, increasing integration and reducing the number of components on the PCB; and it improves the overall system stability. By employing a common-cathode LED driving method, this invention effectively solves the heat generation problem caused by high power consumption in existing LED displays. Lowering the operating voltage not only effectively reduces system power consumption but also improves LED reliability and extends lifespan, thus achieving a highly efficient and reliable LED display effect.

[0059] like Figure 4 As shown, the system in this embodiment is divided into 5 modules:

[0060] (1) Serial to Parallel Converter: This module takes SIN and CLK as input signals and outputs DATA<15:0>. The serial to parallel converter module converts the serial data of SIN into parallel data DATA<15:0>.

[0061] (2) Instruction decoder: The input signals of this module are CLK and LE, and the output signal is LOCK. This module recognizes the LE instruction. When it receives a latch instruction, it pulls LOCK high and holds it until the next instruction recognition process begins.

[0062] (3) First display data latch: The input signals of this module are DATA<15:0> and LOCK signal, and the output signal is DATA_LOCK<15:0>. On the rising edge of LOCK, buffer 1 latches DATA<15:0> and refreshes the output so that DATA_LOCK<15:0> is equal to the latched DATA<15:0>.

[0063] (4) Second display data latch: The input signals for this module are DATA_LOCK<15:0> and The output signal is DATA_REG<15:0>. The rising edge of the buffer 2 latches DATA_LOCK<15:0> and refreshes the output so that DATA_REG<15:0> is equal to the latched DATA_LOCK<15:0>.

[0064] (5) Output driver 0~15: The input signal of this module is DATA_REG <x>(DATA_REG <x>Corresponding output driver X) and The output signal is OUTX (OUTX corresponds to output driver X). When DATA_REG is low, <x>When DATA_REG is high, the output driver X generates a high-level output at OUTX; <x>When the output is low, the output driver X keeps OUTX low.

[0065] Figure 5 This is a schematic diagram illustrating the timing of data transmission and data display according to an embodiment of the present invention, as follows: Figure 5 As shown, the specific steps for data transmission and data display timing in this embodiment are as follows:

[0066] When DATA<N-1:0> After _A is transmitted, a latch signal is generated on LE, and the first display data latch latches DATA.<N-1:0> _A;

[0067] Complete DATA<N-1:0> After _A is latched, OE changes from 1 to 0, and the second display data latch latches DATA.<N-1:0> _A and display DATA<N-1:0> _A;

[0068] In displaying DATA<N-1:0> At the same time as _A, for DATA<N-1:0> _B is used for transmission;

[0069] DATA<N-1:0> After the _B transmission is completed, LE generates a latch signal, and the first display data latch latches DATA.<N-1:0> _B, and then transmit DATA<N-1:0> _C;

[0070] Complete DATA<N-1:0> After _A is displayed, the second display data latch latches DATA.<N-1:0> _B and display DATA<N-1:0> _B;

[0071] Complete DATA<N-1:0> The _C transfer completes the DATA process.<N-1:0> The display of _B;

[0072] Continue the cyclic latching process, latching DATA.<N-1:0> _C and transferring DATA<N-1:0> _D, repeat the previous steps.

[0073] Figure 6 This is a schematic diagram of data transmission and data grayscale 3 according to an embodiment of the present invention. Figure 7 This is a schematic diagram of grayscale data transmission and display in existing technologies; such as... Figure 6 As shown, assuming a simplified dual-latch system with 60 frames per second, 4 scatter groups, and grayscale values ​​of 0-7 defined as low grayscale dual-latch display system, then the waveform configuration for displaying grayscale 3 on 16 channels is as follows: Figure 6 As shown. The existing technology displays a waveform configured for grayscale 3 as follows: Figure 7 As shown. Figure 6 and Figure 7 The diagrams illustrate the data transmission and display timing of this invention and existing technologies when displaying a grayscale level of 3. As can be seen from the diagrams, this invention employs a dual-buffer design and shuffles and reassembles the image data compared to existing technologies. This invention uses two latches, A and B, operating alternately; one displays the current frame image, while the other acquires the next frame image data. The input image data is shuffled and grouped according to its high and low bits, and then interleaved and transmitted to latch A. For example, DATA A1 represents bits 1 to 4, and DATA B1 represents bits 5 to 8. The LOCK signal controls latch A to latch the data, which is then transmitted to latch B in the next frame. Latch B drives the LED display. This hides the data loading time, effectively improving the refresh rate and ensuring smooth image movement. Existing technologies transmit high and low bit data sequentially, resulting in discontinuous data transmission. When displaying a grayscale level of 3, this invention can complete data loading within one frame, while existing technologies require two frames. Therefore, this invention, through alternating dual-buffer display and data shuffling and reassembly, can improve the refresh rate and grayscale effect of the LED display, achieving smooth and clear image display.

[0074] from Figure 1 and Figure 5 , Figure 6 and Figure 7 As shown in the timing diagram, compared with existing technologies, this invention employs a dual-latch register and a common-cathode structure, achieving improvements in LED display performance and reduced power consumption. The dual-latch register design, with one latch responsible for display and the other for data acquisition, hides the data loading time, effectively increasing the display refresh rate. It also combines high and low bits of the display data for time-interval transmission, allowing excess display time for high-bit data to be used for low-bit data transmission. This improves both data transmission efficiency and display grayscale. Grouping and interleaving the input signal into high and low bits further enhances the display refresh rate, ensuring smooth and clear moving images. The common-cathode LED structure reduces the operating voltage, directly reducing system power consumption by over 25%. Reduced LED power consumption improves stability and lifespan. Through these technical means, this invention achieves reduced power consumption while maintaining image display quality, solving the problems of insufficient refresh rate and excessive power consumption in existing technologies. This results in a smoother, clearer LED display with higher reliability, ultimately improving the overall performance of the LED display system.

[0075] The present invention and its embodiments have been described above illustratively. This description is not restrictive, and the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. The accompanying drawings are only one embodiment of the present invention, and the actual structure is not limited thereto. No reference numerals in the claims should limit the scope of the claims. Therefore, if a person skilled in the art is inspired by this description and designs a similar structure and embodiment without departing from the spirit of the invention, such design should fall within the scope of protection of this patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" preceding an element does not exclude the inclusion of "a plurality" of that element. Multiple elements stated in the product claims may also be implemented by a single element through software or hardware. The terms "first," "second," etc., are used to indicate names and do not indicate any specific order.< / x> < / x> < / x> < / x> < / x>

Claims

1. A dual-latch display system, characterized in that: include, A serial-to-parallel converter converts input serial data into parallel data. The instruction decoder pulls the LOCK signal high and holds it until the next instruction recognition process begins; The first display data latch receives parallel data and a LOCK signal, and latches the parallel data on the rising edge of the LOCK signal; The second display data latch latches the latched data output by the first display data latch when the LOCK signal falls; The output driver receives the output data from the second display data latch and drives the LEDs. The clock generation module generates the serial data clock SCLK, the parallel data clock PCLK, and the latch enable signal LE. The LED array is a common cathode array; Specifically, at the rising edge of the LOCK signal, the first display data latch latches the input data DATA that has been transmitted.<N-1:0> _A; On the falling edge of the LOCK signal, the second display data latch latches the data in the first display data latch and displays the output; The second display data latch displays the output data DATA<N-1:0> Simultaneously with _A, transmit new data DATA<N-1:0> _B; DATA<N-1:0> After _B is transmitted, the first display data latch latches DATA.<N-1:0> _B; The second display shows the DATA in the data latch.<N-1:0> After display A ends, the second display data latch stores the DATA in the first display data latch.<N-1:0> _B, and display the output; Repeat all operations to continue latching newly transmitted data and alternately displaying the output.

2. A dual-latch display method, applied to the dual-latch display system of claim 1, characterized in that: The output serial signal SIN is converted into a parallel signal by a serial-to-parallel converter. Parallel signal input to the first display data latch; At the rising edge of the LOCK signal, the first display data latch latches the parallel data; At the falling edge of the LOCK signal, the second display data latch latches the output data of the first display data latch; The output driver receives the output data from the second display data latch and drives the LED display.

Images