A delay adjustment method, a memory chip architecture, and a semiconductor memory.

Abstract

This disclosure provides a delay adjustment method, a memory chip architecture, and a semiconductor memory. The method includes: measuring a first delay of a first signal path; decoding a corresponding delay cycle number based on the first delay, wherein the delay cycle number represents the ratio of the first delay to a clock cycle; and controlling a second delay of a second signal path to be an integer multiple of the clock cycle based on the delay cycle number. This disclosure enables synchronization of different signal paths, reducing the risk of signal transmission errors in the chip.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a delay adjustment method, a memory chip architecture, and a semiconductor memory. Background Technology

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speed when manufacturing and using devices such as computers. In order to obtain faster data transmission speeds, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.

[0003] In designs that double the data transmission rate, an on-die termination (ODT) path is added. Simply put, the value of the termination resistance (RTT) can be switched, and the switching must follow a specific timing sequence. For example, the state of the ODT pin on the memory chip can control the value of the RTT.

[0004] However, the increased signal paths also bring about synchronization problems and increase the risk of signal transmission errors. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a delay adjustment method, a memory chip architecture, and a semiconductor memory, which can synchronize different signal paths and reduce the risk of signal transmission errors in the chip.

[0006] The technical solution of this disclosure embodiment is implemented as follows:

[0007] This disclosure provides a delay adjustment method, including:

[0008] Measure the first delay of the first signal path;

[0009] Based on the first delay, the corresponding delay cycle number is decoded; the delay cycle number represents the ratio of the first delay to the clock cycle;

[0010] Based on the number of delay cycles, the second delay of the second signal path is controlled to be an integer multiple of the clock cycle.

[0011] In the above scheme, the second signal path includes at least one load unit, and the second delay includes an adjustable delay; the step of controlling the second delay of the second signal path to be an integer multiple of the clock cycle based on the number of delay cycles includes: activating the first load unit corresponding to the at least one load unit based on the number of delay cycles, changing the electrical load value of the first load unit to adjust the adjustable delay, thereby controlling the second delay to be an integer multiple of the clock cycle.

[0012] In the above scheme, activating the first load unit corresponding to the at least one load unit based on the number of delay cycles includes: generating a corresponding load activation signal based on the number of delay cycles; and transmitting the load activation signal to the first load unit to activate the first load unit.

[0013] In the above scheme, the second signal path further includes at least one shift register, and the second delay further includes a shift delay; the step of controlling the second delay of the second signal path to be an integer multiple of the clock cycle based on the number of delay cycles further includes: controlling the at least one shift register to adjust the shift delay based on the number of delay cycles, so as to control the second delay to be a target integer multiple of the clock cycle.

[0014] This disclosure also provides a memory chip architecture, which includes: a first signal path, a second signal path, and a delay adjustment device; the delay adjustment device includes:

[0015] The delay measurement unit is configured to measure the first delay of the first signal path;

[0016] The delay decoding unit is configured to receive the first delay and, based on the first delay, decode the corresponding delay cycle number; the delay cycle number represents the ratio of the first delay to the clock cycle.

[0017] A self-alignment control unit is configured to receive the number of delay cycles and, based on the number of delay cycles, control the second delay of the second signal path to be an integer multiple of the clock cycle.

[0018] In the above scheme, the self-alignment control unit is further configured to generate a corresponding load activation signal based on the number of delay cycles.

[0019] In the above scheme, the second signal path includes: a delay control module; the delay control module is configured to control the second delay of the second signal path to be synchronized with the clock cycle;

[0020] The delay control module includes: at least one load unit; the load connection terminal of the at least one load unit is connected to any position on the main path in the delay control module; the at least one load unit is configured to be activated by the corresponding load activation signal, and change the electrical load value to adjust the adjustable delay in the second delay.

[0021] In the above scheme, the load unit includes: an input subunit configured to receive the load activation signal and generate two control signals based on the load activation signal; and a capacitor subunit connected to the input subunit and configured to be activated by the two control signals to change the electrical load value of the load unit.

[0022] In the above scheme, the input subunit includes: a first inverter, used to receive the load activation signal and output the first control signal of the two control signals; and a second inverter, the input terminal of the second inverter being connected to the output terminal of the first inverter, and the second inverter being used to output the second control signal of the two control signals.

[0023] In the above scheme, the capacitor sub-unit includes: a first MOS transistor, the source and drain of which are both connected to the output terminal of the first inverter; and a second MOS transistor, the source and drain of which are both connected to the output terminal of the second inverter, and the gate of the second MOS transistor is connected to the gate of the first MOS transistor and together serve as the load connection terminal of the load unit.

[0024] In the above scheme, the first MOS transistor is an NMOS transistor, and the second MOS transistor is a PMOS transistor.

[0025] In the above scheme, the second signal path is an on-chip termination path; the second signal path further includes: a receiver configured to receive an on-chip termination pin signal and a clock signal; an enable module connected to the receiver configured to control the operating state of the second signal path; at least one shift register connected to the enable module and the delay control module configured to generate and adjust the shift delay in the second delay; and a termination resistor control module connected to the delay control module configured to control the switching of the termination resistor value.

[0026] In the above scheme, the first signal path is a delayed phase-locked loop path.

[0027] This disclosure also provides a semiconductor memory, which includes the memory chip architecture described above.

[0028] In the above scheme, the semiconductor memory is a synchronous dynamic random access memory (SDRAM) chip.

[0029] In the above scheme, the synchronous dynamic random access memory (SDRAM) chip conforms to the DDR4 memory specification.

[0030] Therefore, the embodiments of this disclosure provide a delay adjustment method, a memory chip architecture, and a semiconductor memory. This method measures the first delay of a first signal path and decodes the corresponding delay cycle number based on the first delay. The delay cycle number represents the ratio of the first delay to the clock cycle. Then, based on the delay cycle number, the second delay of the second signal path is controlled to be an integer multiple of the clock cycle. In this way, the second delay is adjusted according to the delay cycle number corresponding to the first delay, ensuring that the ratio of the second delay to the clock cycle is an integer. This synchronizes different signal paths, thereby ensuring that the chip delay meets design requirements and reducing the risk of signal transmission errors in the chip. Attached Figure Description

[0031] Figure 1 A flowchart of a delay adjustment method provided in this embodiment of the present disclosure Figure 1 ;

[0032] Figure 2 A flowchart of a delay adjustment method provided in this embodiment of the present disclosure Figure 2 ;

[0033] Figure 3 An explanatory diagram illustrating a delay adjustment method provided in an embodiment of this disclosure;

[0034] Figure 4 A schematic diagram of a memory chip architecture provided in this disclosure embodiment. Figure 1 ;

[0035] Figure 5 A schematic diagram of a memory chip architecture provided in this disclosure embodiment. Figure 2 ;

[0036] Figure 6 A schematic diagram of a memory chip architecture provided in this disclosure embodiment. Figure 3 ;

[0037] Figure 7 A schematic diagram of a memory chip architecture provided in this disclosure embodiment. Figure 4 ;

[0038] Figure 8 A schematic diagram of a memory chip architecture provided in this disclosure embodiment. Figure 5 ;

[0039] Figure 9 This is a schematic diagram of the structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0041] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] If similar descriptions such as "first / second" appear in the invention document, the following description shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0044] With the rapid development of semiconductor technology, chips employ an increasing number of signal paths. The timing of signals transmitted along different paths needs to be aligned, meaning synchronization is required between different signal paths. Taking Synchronous Dynamic Random Access Memory (SDRAM) as an example, SDRAM includes multiple signal paths such as DLL (Delay-Locked Loop), Read, Write, and ODT (On-Die Termination). Since SDRAM is a synchronous device, the physical delay of each path must be controlled to be an integer multiple of the clock cycle to align the edges of the clock signals passing through each path. Physical delay includes route path delay and circuit delay; therefore, each path must satisfy the following:

[0045] αL+βM=N*t CK (1);

[0046] In the above formula, αL represents the trace delay, where α is the unit trace delay and L is the trace length of each path (in μm); βM represents the circuit delay, where β is the delay of each stage of the circuit and M is the stage number of each path; t CK This represents the clock cycle, where N is a positive integer.

[0047] In physical delays, circuit delays are more sensitive than trace delays and are more susceptible to the effects of PVT (Process, Voltage, Temperature) conditions. A process corner represents the actual operating conditions of a circuit. Different process corners characterize different PVT conditions. Under certain process corners, such as the fast corner, the circuit delay remains relatively stable with changes in clock frequency. However, under other process corners, such as the typical corner or the worst corner, the circuit delay varies significantly with clock frequency, meaning it is difficult to maintain stability. Therefore, PVT conditions have a significant impact on circuit delays.

[0048] It's important to note that under poor PVT conditions—specifically, slow process corners with lower voltages and higher temperatures—the physical delays of the Read, Write, and ODT paths are shorter than those of the DLL path. This is because the clock signals for the Read, Write, and ODT paths require a wait for enable, resulting in fewer stages and longer route metal compared to the DLL. Typically, the clock signals for the Read, Write, and ODT paths are adjusted and balanced when the process corner is typical. However, it cannot be guaranteed that the physical delays of different paths will match across all process corners.

[0049] Figure 1 This is an optional flowchart illustrating the delay adjustment method provided in this embodiment of the disclosure, which will be combined with... Figure 1 The steps shown will be explained. It should be noted that the delay adjustment method in the embodiments of this disclosure can be executed by a delay adjustment device.

[0050] S101, Measure the first delay of the first signal path.

[0051] In this embodiment of the disclosure, the delay adjustment device can measure the first delay of the first signal path, wherein the first signal path can be a delay-locked loop (DLL).

[0052] It should be noted that a DLL is a feedback control circuit that automatically adjusts the delay of the output signal to ensure that the output signal is in phase with the input signal, meaning the output signal is delayed by an integer number of cycles relative to the input signal. Specifically, the DLL can control the delay and phase of the internal oscillation signal based on the input signal, achieving automatic tracking of the input signal by the output signal. The output signal maintains a fixed phase difference with the input signal; that is, the phase of the output signal and the input signal is locked and unaffected by PVT conditions. Therefore, the DLL can adjust the delay of the clock signal, controlling the delay of the output clock signal relative to the input clock signal to be an integer multiple of the clock cycle, i.e., the first delay is an integer multiple of the clock cycle.

[0053] It should be noted that when PVT conditions are worse, i.e., in the case of a slow process corner, decreased voltage and increased temperature, the loop delay (i.e., the first delay) of the DLL path will increase. The loop delay is the physical delay from the clock pin (CKTpad) to the data pin (DQS pad). It includes the clock signal receiver (Clock Buffer), CDL (Coarse Delay Line), FDL (Fine Delay Line), clock tree, and DQ driver circuitry. Most of these circuits are of a fixed number of stages, and their physical delay depends on the PVT conditions.

[0054] S102. Based on the first delay, decode the corresponding delay cycle number; the delay cycle number represents the ratio of the first delay to the clock cycle.

[0055] In this embodiment, after the delay adjustment device measures the first delay, it can decode the first delay to obtain the number of delay cycles N corresponding to the first delay, which is the ratio of the first delay to the clock cycle. Since the first delay is an integer multiple of the clock cycle, the number of delay cycles N is a positive integer. It should be noted that if the first delay is a loop delay, then the number of delay cycles is the loop delay number.

[0056] S103. Based on the number of delay cycles, control the second delay of the second signal path to be an integer multiple of the clock cycle.

[0057] In this embodiment, the second signal path can be an ODT path, which includes an ODT resistor. During signal transmission, the ODT resistor performs impedance matching on the transmission line to reduce energy loss and reflection during transmission, thereby ensuring the integrity of the signal received at the receiving end. To implement the function of the ODT resistor, the ODT path includes a certain number of logic circuits. These logic circuits generate circuit delays, which vary significantly under different process corners. Therefore, the delay of the ODT path needs to be adjusted to synchronize it with other paths. In other words, it is necessary to reduce the impact of PVT conditions on the physical delay of the ODT path and improve the PVT tolerance of the ODT path.

[0058] In this embodiment, after determining the number of delay periods N, the delay adjustment device can control the second delay of the second signal path to ensure that the second delay is also an integer multiple of the clock period. In other words, the delay adjustment device can adjust the second delay based on the number of delay periods N of the first delay. Since the first delay satisfies the synchronization requirements of the signal path, the adjusted second delay can also satisfy the synchronization requirements of the signal path.

[0059] Understandably, the second delay is adjusted based on the number of delay cycles compared to the first delay, ensuring that the ratio of the second delay to the clock cycle is an integer. This synchronizes different signal paths, allowing the chip's delay to meet design requirements and reducing the risk of signal transmission errors within the chip.

[0060] In some embodiments of this disclosure, the second signal path includes at least one load unit, and the second delay includes an adjustable delay; it can be used... Figure 2 The shown S104 implements Figure 1 S103, shown below, will be explained in conjunction with each step.

[0061] S104. Based on the number of delay cycles, activate the corresponding first load unit in at least one load unit, change the electrical load value of the first load unit to adjust the adjustable delay, thereby controlling the second delay to be an integer multiple of the clock cycle.

[0062] In this embodiment of the disclosure, such as Figure 3As shown, the second signal path 20 includes multiple circuit modules 001, which generate physical delays. At least one load unit 401 can be provided in the second signal path 20, and each load unit 401 is connected to the second signal path 20. When each load unit 401 is activated, its electrical load value changes, generating a certain load delay, thus affecting the second delay. The load delays generated by each load unit 401 can be the same or different. The second delay includes an adjustable delay, which includes the delays generated by all load units 401.

[0063] In this embodiment, the delay adjustment device can determine, based on the number of delay cycles, the amount of adjustment required to make the adjustable delay reach the target number of delay cycles for the second delay, and then determine the first load unit that needs to be activated in at least one load unit 401 to achieve the adjustment amount. Furthermore, the delay adjustment device can generate a corresponding load activation signal, transmit the load activation signal to the first load unit, activate the first load unit, change the electrical load value of the first load unit, and cause the first load unit to generate a load delay, thereby adjusting the adjustable delay and controlling the second delay to be an integer multiple of the clock cycle. For example, if load units 6 to 9 are determined as the first load unit, the delay adjustment device will generate a load activation signal N. A <6:9> means transmitting load activation signals to load units 6 through 9 to activate them.

[0064] Accordingly, in order to achieve the target number of delay cycles for the second delay, the delay adjustment device can also determine that a second load unit needs to be deactivated in at least one load unit 401, i.e., the second load unit is already in an activated state. Furthermore, the delay adjustment device can generate a corresponding load stop signal, transmit the load stop signal to the second load unit, stop the activation state of the second load unit, change the electrical load value of the second load unit, and cause the second load unit to stop generating load delay, thereby adjusting the adjustable delay and controlling the second delay to be an integer multiple of the clock cycle.

[0065] In this embodiment, the load activation signal and the load stop signal can be at different levels, with the load activation signal being a first level and the load stop signal being a second level. The delay adjustment device can transmit the first level to the first load unit to activate it; correspondingly, the delay adjustment device can also transmit the second level to the second load unit to deactivate it.

[0066] It should be noted that the processes of activating the first load unit and stopping the activation of the second load unit described above can be performed simultaneously or separately. That is to say, the delay adjustment device can flexibly adjust the adjustable delay by transmitting load activation signals and / or load stop signals as needed, without any restrictions.

[0067] It is understandable that by setting a load unit with a variable electrical load value in the second signal path, and controlling the load delay generated by the load unit, the overall delay of the second signal path (i.e., the second delay) is controlled. This allows different signal paths to be synchronized, thereby ensuring that the chip delay meets design requirements and reducing the risk of signal transmission errors in the chip.

[0068] In some embodiments of this disclosure, the implementation Figure 2 The method shown in S104 also includes S201 to S202, which will be explained in conjunction with each step.

[0069] S201. Generate the corresponding load activation signal based on the number of delay cycles.

[0070] In this embodiment of the present disclosure, the delay adjustment device can determine the adjustment amount required to make the second delay reach the target delay period based on the delay period number, and then determine the first load unit that needs to be activated in at least one load unit 401 to achieve the adjustment amount, and generate the corresponding load activation signal.

[0071] S202. Transmit the load activation signal to the first load unit to activate the first load unit.

[0072] In this embodiment of the disclosure, after the delay adjustment device generates a load activation signal, it can transmit the load activation signal to the first load unit to activate the first load unit, change the electrical load value of the first load unit, and cause the first load unit to generate a load delay, thereby controlling the second delay to be an integer multiple of the clock cycle. For example, if load units 6 to 9 are determined to be the first load unit, the delay adjustment device will transmit the load activation signal to load units 6 to 9 to activate them.

[0073] Understandably, based on the situation of each load unit, the first load unit that needs to be activated is determined, and an activation signal is transmitted to the first load unit to activate it. In this way, precise control of the load delay generated by each load unit is achieved, thereby making the adjustment result of the second delay more accurate.

[0074] In some embodiments of this disclosure, the second signal path further includes at least one shift register, and the second delay further includes a shift delay; [implementation] Figure 2 The method shown in S104 also includes S203, which will be explained in conjunction with each step.

[0075] S203. Based on the number of delay cycles, control at least one shift register to adjust the shift delay so that the second delay is a target integer multiple of the clock cycle.

[0076] In this embodiment of the disclosure, the second signal path further includes at least one shift register. The shift register, triggered by a clock signal, can shift the signal transmitted in the second signal path, i.e., adjust the shift delay in the second delay. Since the shift register is triggered by a clock signal, the adjustment amount of the shift delay is measured in clock cycles, i.e., the adjustment amount of the shift delay is an integer number of clock cycles. Therefore, after adjusting the shift delay, it can still be guaranteed that the second delay is an integer multiple of the clock cycle.

[0077] In this embodiment of the present disclosure, when the second signal path is an ODT path, the delay adjustment device can control the shift register to adjust the shift delay so that the ratio of the second delay to the clock cycle is CWL (CAS Write Latency, column address write delay) minus 2(CWL-2), thereby meeting the requirements of memory specifications such as DDR4 (4th Double Data Rate). Specifically, after the delay adjustment device decodes the number of delay cycles corresponding to the first delay as N, it can adjust the adjustable delay in the second delay so that the ratio of the second delay to the clock cycle is also N; then, the delay adjustment device can control the shift register to shift CWL minus 2 and then minus N(CWL-2-N) clock cycles, so that the ratio of the second delay to the clock cycle satisfies the value of CWL minus 2(CWL-2).

[0078] It's important to note that the DDR4 technical specifications regarding ODT (Optical Distribution Path) essentially state that the RTT (Termination Resistance) value within the ODT can be switched, but this switching must adhere to specific timing rules. One mode is synchronous ODT, where the signal level at the ODT pin on the memory chip controls the RTT resistance value to achieve impedance matching of the transmission line, reducing energy loss and reflection during signal transmission. The ODT path latency is related to the CWL (Constant Width Level), therefore, the ODT path latency needs to be controlled to meet CWL-related timing requirements.

[0079] It is understandable that by utilizing the shift register's ability to shift according to the clock cycle, the shift delay in the second delay can be adjusted. This ensures, on the one hand, the synchronization between signal paths is guaranteed, meaning the second delay is an integer multiple of the clock cycle; on the other hand, it ensures that the second delay meets the design requirements.

[0080] Figure 4 This is a schematic diagram of an optional structure of the memory chip architecture provided in this disclosure embodiment, such as... Figure 4 As shown, the memory chip architecture 80 includes: a first signal path 10, a second signal path 20, and a delay adjustment device 30.

[0081] The delay adjustment device 30 includes a delay measurement unit 301, a delay decoding unit 302, and a self-alignment control unit 303. The delay measurement unit 301 is connected to the first signal path 10 and is configured to measure a first delay of the first signal path 10. The delay decoding unit 302 is configured to receive the first delay from the delay measurement unit 301 and decode the corresponding delay cycle number based on the first delay, where the delay cycle number represents the ratio of the first delay to the clock cycle. The self-alignment control unit 303 is connected to the second signal path 20 and is configured to receive the delay cycle number from the delay decoding unit 302, and based on the delay cycle number, control the second delay of the second signal path 20 to be an integer multiple of the clock cycle.

[0082] In this embodiment, the delay measurement unit 301 can measure the first delay of the first signal path 10 and transmit the first delay to the delay decoding unit 302. The delay decoding unit 302 can decode the first delay to obtain the number of delay cycles corresponding to the first delay, that is, the ratio of the first delay to the clock cycle. Since the first delay is an integer multiple of the clock cycle, the ratio of the first delay to the clock cycle is an integer N. The self-alignment control unit 303 can then adjust the second delay of the second signal path 20 according to the number of delay cycles N corresponding to the first delay, so that the ratio of the second delay to the clock cycle is also an integer.

[0083] Understandably, the delay adjustment device adjusts the second delay based on the number of delay cycles of the first delay, ensuring that the ratio of the second delay to the clock cycle is an integer. This synchronizes different signal paths, allowing the chip delay to meet design requirements and reducing the risk of signal transmission errors within the chip.

[0084] In some embodiments of this disclosure, such as Figure 5 As shown, the second signal path 20 includes a latency control module 201. The latency control module 201 is configured to control the second latency of the second signal path 20 to be synchronized with the clock cycle. The latency control module 201 includes at least one load unit 401. The load connection terminal of the at least one load unit 401 is connected to any position in the main path of the latency control module 201.

[0085] In this embodiment of the disclosure, the self-alignment control unit 303 is further configured to generate a corresponding load activation signal based on the number of delay cycles, and transmit the load activation signal to the corresponding load unit 401. The load unit 401 is activated by the corresponding load activation signal, and changes the electrical load value to adjust the adjustable delay in the second delay.

[0086] In this embodiment of the disclosure, the adjustment amount that each load unit 401 can bring to the second delay after being activated can be predetermined. The self-alignment control unit 303 can determine which load units 401 can be activated and whose second delay can be adjusted to match the first delay based on the delay period of the first delay and the adjustment amount of each load unit, that is, determine the first load unit that needs to be activated, and then transmit the activation signal to the first load unit.

[0087] Understandably, by setting up a load unit in the delay control module that can change the electrical load value, the self-alignment control unit can control the load delay generated by the load unit, thereby controlling the overall delay of the second signal path (i.e., the second delay). This allows different signal paths to be synchronized, thus ensuring that the chip delay meets design requirements and reducing the risk of signal transmission errors in the chip.

[0088] In some embodiments of this disclosure, such as Figure 6 As shown, the load unit 401 includes an input subunit 402 and a capacitor subunit 403. The input subunit 402 is configured to receive a load activation signal N. A Based on load activation signal N A Two control signals Va and Vb are generated. The capacitor subunit 403 is connected to the input subunit 402 and is also connected to the main path of the delay control module. The capacitor subunit 403 is configured to be activated by the two control signals Va and Vb, thereby changing the electrical load value of the load unit 401.

[0089] In some embodiments of this disclosure, such as Figure 7 As shown, the input subunit 402 includes a first inverter 501 and a second inverter 502. The first inverter 501 is used to receive the load activation signal N. A The first control signal Va is output from the two control signals. The input of the second inverter 502 is connected to the output of the first inverter 501, and the second inverter 502 is used to output the second control signal Vb from the two control signals.

[0090] The capacitor sub-unit 403 includes a first MOSFET 503 and a second MOSFET 504. The source and drain of the first MOSFET 503 are both connected to the output of the first inverter 501. The source and drain of the second MOSFET 504 are both connected to the output of the second inverter 502. The gate of the second MOSFET 504 is connected to the gate of the first MOSFET 503 and together they serve as the load connection terminal of the load unit 401, connected to the main path of the delay control module.

[0091] In this embodiment of the disclosure, the first MOS transistor 503 and the second MOS transistor 504 are different types of MOS transistors. For example, the first MOS transistor 503 is an NMOS transistor, and the second MOS transistor 504 is a PMOS transistor. The first MOS transistor 503 and the second MOS transistor 504 together constitute a capacitor unit (MOS CAP).

[0092] Load activation signal N A After passing through the first inverter 501 and the second inverter 502, a first control signal Va and a second control signal Vb are obtained. The levels of the first control signal Va and the second control signal Vb are inverted, therefore, two different types of MOSFETs, the first MOSFET 503 and the second MOSFET 504, can be turned on simultaneously. Taking the first MOSFET 503 as an NMOS transistor and the second MOSFET 504 as a PMOS transistor as an example, the load unit 401 receives a high-level load activation signal N... A After passing through the first inverter 501 and the second inverter 502, the first control signal Va is low and the second control signal Vb is high. Then, the first MOS transistor 503 is turned on by the first control signal Va, forming a gate capacitor and connected to the main path as a capacitive load. Correspondingly, the first MOS transistor 504 is turned on by the second control signal Vb, forming a gate capacitor and connected to the main path as a capacitive load. In this way, the load value of the load unit 401 is changed, which affects the delay on the main path, that is, it plays an adjustment role in the second delay.

[0093] Understandably, a capacitor unit is formed using two different types of MOSFETs. Simultaneously, two inverters provide different voltage levels to the two MOSFETs, turning them on and forming gate capacitors. These gate capacitors are then connected to the main path of the second signal path as a capacitive load to adjust the second delay. This allows different signal paths to be synchronized, ensuring the chip delay meets design requirements and reducing the risk of signal transmission errors within the chip.

[0094] In some embodiments of this disclosure, such as Figure 8As shown, the second signal path 20 is an on-chip termination (ODT) path. The second signal path 20 further includes: a receiver 202, an enable module 203, at least one shift register 204, and a termination resistor control module 205. The receiver 202 is configured to receive the on-chip termination pin signal and the clock signal. The enable module 203 is connected to the receiver 202 and is configured to control the operating state of the second signal path 20. At least one shift register 204 is connected to the enable module 203 and the delay control module 201, and is configured to generate and adjust the shift delay in the second delay. The termination resistor control module 205 is connected to the delay control module 201 and is configured to control the switching of the termination resistor value.

[0095] In this embodiment, the first signal path uses a DLL path, which can lock the phase of the output signal with the input signal, controlling the delay of the output clock signal relative to the input clock signal to be an integer multiple of the clock period. The second signal path 20 uses an ODT path, which is a very complex path, including physical delay (independent of the clock period) and clock delay (delay is an integer multiple of the clock period). Since the final delay of the entire path (i.e., the second delay) needs to be an integer multiple of the clock period, the delay control module 201 uses the first delay of the DLL path (first signal path) to synchronize the signal at the end of the ODT path with the clock signal. In this way, by compensating for the physical delay, the delay of the entire path is made to be an integer multiple of the clock period, ultimately enabling control of the resistance value of the termination resistor RTT.

[0096] Understandably, by aligning with the DLL path and adjusting the physical delay of the ODT path, the PVT tolerance of the physical delay of the ODT path is significantly improved, thereby enabling different signal paths to be synchronized and reducing the risk of signal transmission errors in the chip.

[0097] It should be noted that, Figure 9 An optional structural schematic diagram of a semiconductor memory provided in an embodiment of this disclosure is shown below. Figure 9 As shown, the semiconductor memory 90 includes a memory chip architecture 80.

[0098] In some embodiments of this disclosure, the semiconductor memory 90 is a synchronous dynamic random access memory (SDRAM) chip. The synchronous dynamic random access memory (SDRAM) chip conforms to the DDR4 memory specification.

[0099] It should be noted that the descriptions of the above-described memory and device embodiments are similar to those of the above-described method embodiments, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0100] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0101] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0102] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of the embodiments of this disclosure, depending on actual needs.

[0103] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0104] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory chip architecture, characterized in that, The memory chip architecture includes: a first signal path, a second signal path, and a delay adjustment device; the delay adjustment device includes: The delay measurement unit is configured to measure the first delay of the first signal path; The delay decoding unit is configured to receive the first delay and, based on the first delay, decode the corresponding delay cycle number; the delay cycle number represents the ratio of the first delay to the clock cycle. A self-alignment control unit is configured to receive the number of delay cycles and, based on the number of delay cycles, control the second delay of the second signal path to be an integer multiple of the clock cycle; The self-alignment control unit is also configured to generate a corresponding load activation signal based on the number of delay cycles; The second signal path includes: a delay control module; The delay control module is configured to control the second delay of the second signal path to be synchronized with the clock cycle; The delay control module includes: at least one load unit; the load connection terminal of the at least one load unit is connected to any position on the main path in the delay control module; the at least one load unit is configured to be activated by the corresponding load activation signal, and change the electrical load value to adjust the adjustable delay in the second delay; The load unit includes: The input subunit is configured to receive the load activation signal and generate two control signals based on the load activation signal. A capacitor subunit, connected to the input subunit, is configured to be activated by the two control signals to change the electrical load value of the load unit; The input subunit includes: The first inverter is used to receive the load activation signal and output the first control signal of the two control signals; The second inverter has its input connected to the output of the first inverter, and is used to output the second control signal of the two control signals.

2. The memory chip architecture according to claim 1, characterized in that, The capacitor subunit includes: The first MOSFET has its source and drain both connected to the output of the first inverter. The second MOSFET has its source and drain both connected to the output of the second inverter, and its gate is connected to the gate of the first MOSFET, together serving as the load connection terminal of the load unit.

3. The memory chip architecture according to claim 2, characterized in that, The first MOS transistor is an NMOS transistor, and the second MOS transistor is a PMOS transistor.

4. The memory chip architecture according to claim 1, characterized in that, The second signal path is an on-chip termination path; The second signal path also includes: The receiver is configured to receive on-chip termination pin signals and clock signals; The enable module, connected to the receiver, is configured to control the operating state of the second signal path; At least one shift register, connected to the enable module and the delay control module, is configured to generate and adjust the shift delay in the second delay; The termination resistor control module, connected to the delay control module, is configured to control the switching of the termination resistor value.

5. The memory chip architecture according to any one of claims 1 to 4, characterized in that, The first signal path is a delayed phase-locked loop path.

6. A semiconductor memory, characterized in that, The semiconductor memory includes the memory chip architecture as described in any one of claims 1 to 5.

7. The semiconductor memory according to claim 6, characterized in that, The semiconductor memory is a synchronous dynamic random access memory (SDRAM) chip.

8. The semiconductor memory according to claim 7, characterized in that, The synchronous dynamic random access memory (SDRAM) chip conforms to the DDR4 memory specification.

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