Semiconductor devices used to perform data alignment operations

Abstract

A semiconductor device includes: an alignment data generation circuit that aligns first latched data and second latched data generated from a first set of input data in sync with a first internal strobe signal, outputs the aligned first latched data and second latched data as first alignment data, aligns first latched data and second latched data generated from a second set of input data in sync with a second internal strobe signal, and outputs the aligned first latched data and second latched data as second alignment data; and a write data generation circuit that generates first write data and second write data from the first alignment data and second alignment data in sync with a latch clock after the start of a first operating mode, and generates the first write data and second write data from the first alignment data in sync with a latch clock after the start of a second operating mode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2022-0066390, filed with the Korean Intellectual Property Office on May 30, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a device for performing data alignment operations on a semiconductor memory device. Background Technology

[0004] Typically, semiconductor memory devices, including Double Data Rate Synchronous DRAM (DDR SRAM), perform read and write operations in response to commands received from an external device. To perform such operations, semiconductor memory devices can use data alignment circuitry to align multiple consecutively received data.

[0005] In addition, semiconductor memory devices can use strobe signals to select data in order to perform read and write operations. Summary of the Invention

[0006] In one embodiment, a semiconductor device includes: an alignment data generation circuit configured to align first latched data and second latched data generated from a first set of input data in sync with a first internal strobe signal, configured to output the aligned first latched data and second latched data as first aligned data, configured to align the first latched data and second latched data generated from a second set of input data in sync with a second internal strobe signal, and configured to output the aligned first latched data and second latched data as second aligned data; and a write data generation circuit configured to generate first write data and second write data from the first aligned data and second aligned data in sync with a latch clock after the start of a first operating mode, and configured to generate the first write data and second write data from the first aligned data in sync with a latch clock after the start of a second operating mode. In successive operation of the first operating mode and the second operating mode, the first write data and the second write data have the same data window.

[0007] In one embodiment, a semiconductor device includes: a mode control circuit configured to generate a burst enable signal enabled in a second operating mode based on a mode register signal, a burst control signal, and a mode setting signal for setting a first operating mode and a second operating mode, synchronized with a latch clock generated from a clock; and a data alignment circuit configured to align a first set of input data and a second set of input data based on a first internal strobe signal to a third internal strobe signal generated from a strobe signal, configured to generate first write data and second write data from at least one of the aligned first set of input data and the second set of input data based on a logic level of the burst enable signal, synchronized with the latch clock, and configured to generate internal data from the first write data and the second write data. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an example semiconductor system according to an embodiment of the present disclosure.

[0009] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A block diagram of an example semiconductor device is shown in the figure.

[0010] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram of an example clock control circuit is shown.

[0011] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2 The block diagram of the example gating control circuit is shown in the image.

[0012] Figure 5 It is used to describe embodiments according to this disclosure. Figure 4 The timing diagram shows the operation of the example gating control circuit.

[0013] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram of the example mode control circuit.

[0014] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 2 The block diagram of the example data alignment circuit is shown in the image.

[0015] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 7 The block diagram of the example latch data generation circuit is shown in the image.

[0016] Figure 9 This illustrates an embodiment according to the present disclosure. Figure 7 The example in the diagram is a block diagram of a write-aligned circuit.

[0017] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 9 The block diagram of an example aligned data generation circuit is shown in the figure.

[0018] Figure 11 This illustrates an embodiment according to the present disclosure. Figure 10 The block diagram of the example first aligned data generation circuit is shown in the figure.

[0019] Figure 12 This illustrates an embodiment according to the present disclosure. Figure 10 The block diagram of the example second aligned data generation circuit is shown in the figure.

[0020] Figure 13 This illustrates an embodiment according to the present disclosure. Figure 9 The block diagram of the example write data generation circuit is shown in the figure.

[0021] Figure 14 This illustrates an embodiment according to the present disclosure. Figure 13 The block diagram of the example first write data generation circuit is shown in the figure.

[0022] Figure 15 This illustrates an embodiment according to the present disclosure. Figure 13 The block diagram of the example second write data generation circuit is shown in the figure.

[0023] Figure 16 This illustrates an embodiment according to the present disclosure. Figure 7 The block diagram of the example internal data generation circuit is shown in the figure.

[0024] Figures 17 to 19 This is a timing diagram describing an example data alignment operation according to an embodiment of the present disclosure.

[0025] Figure 20 This illustrates the application of embodiments according to this disclosure. Figures 1 to 19 The diagram shows an example electronic system of a semiconductor system. Detailed Implementation

[0026] In the following description of the implementation, the term "preset" means that the value of a parameter is determined before the parameter is used in the processing or algorithm. The value of the parameter can be set before the processing or algorithm begins, at the start of the processing or algorithm, or while the processing or algorithm is being executed.

[0027] Terms such as “first” and “second” (used as markers to distinguish various parts) are not limited to parts, nor do they necessarily indicate a specific order. For example, in a description, the first part can be referred to as the second part, and vice versa.

[0028] When a component is referred to as "coupled" or "connected" to another component, it should be understood that these components may be directly coupled or connected to each other, or coupled or connected to each other through another component placed between them. Conversely, when a component is referred to as "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or connected to each other without any other component placed between them.

[0029] "Logic high" and "logic low" are used to describe the logic level of a signal, not necessarily the voltage level. For a "high active" signal, the active signal can be at a logic high level (equivalent to a high voltage level), and the inactive signal can be at a logic low level (equivalent to a low voltage level). For a "low active" signal, the active signal can be at a logic high level (equivalent to a low voltage level), and the inactive signal can be at a logic low level (equivalent to a high voltage level). Some low active signals can be indicated by appending the letter "n" to the signal name. For example, a low active error signal can be labeled "nERROR," while a high active error signal can be labeled "ERROR."

[0030] The teachings of this disclosure will be described in more detail below through various embodiments. These embodiments are merely illustrative of the teachings of this disclosure, and the scope of this disclosure is not limited to these exemplary embodiments.

[0031] Figure 1 This is a block diagram illustrating an example semiconductor system according to an embodiment of the present disclosure. (As shown) Figure 1 As shown, the semiconductor system 1 may include a controller 10 and a semiconductor device 20. The semiconductor device 20 may include a clock control circuit (CLK CTR) 240, a gating control circuit (DQS CTR) 250, a mode control circuit (MODE CTR) 260, and a data alignment circuit (DATAALIGN) 270.

[0032] The controller 10 may include a first control pin 11_1, a second control pin 11_2, a third control pin 11_3, and a fourth control pin 11_4. The semiconductor device 20 may include a first device pin 13_1, a second device pin 13_2, a third device pin 13_3, and a fourth device pin 13_4. A first transmission line 12_1 may be connected between the first control pin 11_1 and the first device pin 13_1. A second transmission line 12_2 may be connected between the second control pin 11_2 and the second device pin 13_2. A third transmission line 12_3 may be connected between the third control pin 11_3 and the third device pin 13_3. A fourth transmission line 12_4 may be connected between the fourth control pin 11_4 and the fourth device pin 13_4.

[0033] Controller 10 can output clock CLK and strobe signal DQS to semiconductor device 20 via the first transmission line 12_1. Controller 10 can output command CMD to semiconductor device 20 via the second transmission line 12_2. Controller 10 can output address ADD to semiconductor device 20 via the third transmission line 12_3. Controller 10 can output data DATA to semiconductor device 20 via the fourth transmission line 12_4, and can also receive data DATA from semiconductor device 20 via the fourth transmission line 12_4.

[0034] Clock CLK can be a periodic signal used for the operation of synchronous controller 10 and semiconductor device 20. Strobe signal DQS can be a signal triggered to strobe data DATA only within the range of input or output data DATA. Command CMD can be a set of commands, each of which can be used to control the operation of semiconductor device 20. Address ADD can be used to address the core circuitry (…). Figure 2 One or more storage units in 280) Figure 1 (Not shown) is used to enable the semiconductor device 20 to store and output data DATA. After the first operating mode begins in a write operation, data DATA can be provided with a first burst length BL16. The first burst length BL16 can mean an operation where 16 bits of data DATA<1:16> are output via controller 10. Data DATA can also use a second burst length BL8 after the second operating mode begins in a write operation. The second burst length BL8 can mean an operation where 8 bits of data DATA<1:8> are output via controller 10. Various embodiments can use different burst lengths with different bit widths.

[0035] The clock control circuit 240 can control the input clock generated from the clock CLK. Figure 2 The IN_CLK signal in the signal is synchronously shifted and written. Figure 2 (WT in the middle) to generate latch clock ( Figure 2 The clock control circuit 240 can be controlled by the input clock (WL). Figure 2 The IN_CLK in the clock is synchronously shifted and latched. Figure 2 WL in the middle) to generate data pulse signals ( Figure 4 (DSP in the middle).

[0036] The gating control circuit 250 can control the input gating signal generated from the gating signal DQS ( Figure 2 The frequency of IN_DQS in the signal is divided to generate the first frequency-divided gating signal. Figure 2 IDQS), the second frequency divider gating signal ( Figure 2 QDQS in the middle), the third frequency divider gating signal ( Figure 2The IBDQS and the fourth frequency divider gating signal (in the middle) Figure 2 The gating control circuit 250 can be based on the second frequency division gating signal (QBDQS). Figure 2 The QDQS and the fourth frequency divider gating signal (in the middle) Figure 2 The QBDQS in the middle generates a first internal strobe signal for aligning data in the first and second operating modes. Figure 2 DDQS1), the second internal strobe signal ( Figure 2 DDQS2) and the third internal strobe signal ( Figure 2 (DDQS3 in the middle).

[0037] The mode control circuit 260 can be synchronized with the latch clock. Figure 2 WL in the middle) and based on the mode register signal ( Figure 2 MR in the middle), burst control signal ( Figure 2 (BC in the middle), and mode setting signal for setting the first operating mode and the second operating mode ( Figure 2 The OTF in the middle is used to generate a burst enable signal that is enabled in the second operating mode. Figure 2 (BCEN in the middle).

[0038] The data alignment circuit 270 can be synchronized with the first internal strobe signal ( Figure 2 DDQS1), the second internal strobe signal ( Figure 2 DDQS2) and the third internal strobe signal ( Figure 2 (DDQS3 in the data) and align the first group of input data generated from the data DATA. Figure 2 IN_D<1:8> in the second group ( Figure 2 In IN_D<9:16>). The data alignment circuit 270 can be synchronized with the latch clock (in the data alignment circuit 270). Figure 2 WL in the middle) and based on the burst enable signal ( Figure 2 The logic level of BCEN in the first group of aligned input data is from the first group of BCEN. Figure 2 IN_D<1:8> in the second group ( Figure 2 At least one of IN_D<9:16> in the middle generates internal data ( Figure 2 ID<1:16> in the middle.

[0039] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A block diagram of an example semiconductor device is shown. (As shown) Figure 2As shown, the semiconductor device 20 may include a buffer circuit 210, a command decoder (CMD DEC) 220, an address decoder (ADDDEC) 230, a clock control circuit 240, a gating control circuit 250, a mode control circuit 260, a data alignment circuit 270, and a core circuit (CORE) 280.

[0040] The buffer circuit 210 may include a first buffer 211, a second buffer 212, a third buffer 213, a fourth buffer 214, and a fifth buffer 215. The first buffer 211 can generate the first to Lth input commands IN_CMD<1:L> by buffering the first to Lth commands CMD<1:L>. The second buffer 212 can generate the first to Mth input addresses IN_ADD<1:M> by buffering the first to Mth addresses ADD<1:M>. The third buffer 213 can generate the input clock IN_CLK by buffering the clock CLK. The fourth buffer 214 can generate the input strobe signal IN_DQS by buffering the strobe signal DQS. The fifth buffer 215 can generate the first to sixteenth input data IN_D<1:16> by buffering the first to sixteenth data DATA<1:16>.

[0041] Command decoder 220 can generate a write signal WT by decoding the first to Lth input commands IN_CMD<1:L>. When the first to Lth input commands IN_CMD<1:L> are received as a combination of logic levels for performing a write operation, command decoder 220 can generate an enabled write signal WT. Command decoder 220 is implemented to generate the write signal WT, but it can also be implemented to generate various signals for performing operations such as read operations, precharge operations, and refresh operations of the semiconductor device 20. The number of bits “L” in the first to Lth commands CMD<1:L> and the first to Lth input commands IN_CMD<1:L> can be a positive integer.

[0042] Address decoder 230 can generate first to Nth internal addresses IADD<1:N> by decoding the first to Mth input addresses IN_ADD<1:M>. The number of bits "M" in the first to Mth addresses ADD<1:M> and the first to Mth input addresses IN_ADD<1:M> can be positive integers. The number of bits "N" in the first to Nth internal addresses IADD<1:N> can be positive integers.

[0043] The clock control circuit 240 can generate a latch clock WL and a data pulse signal DSP that are sequentially enabled by shifting the write signal WT in sync with the input clock IN_CLK. The clock control circuit 240 can also generate the latch clock WL by shifting the write signal WT in sync with the input clock IN_CLK. The shift amount used to generate the latch clock WL and the data pulse signal DSP can be set to a different number of cycles of the input clock IN_CLK.

[0044] The gating control circuit 250 can generate a first frequency-divided gating signal IDQS, a second frequency-divided gating signal QDQS, a third frequency-divided gating signal IBDQS, and a fourth frequency-divided gating signal QBDQS by dividing the frequency of the input gating signal IN_DQS. The gating control circuit 250 can also generate a first frequency-divided gating signal IDQS, a second frequency-divided gating signal QDQS, a third frequency-divided gating signal IBDQS, and a fourth frequency-divided gating signal QBDQS with a 90° phase difference between them by dividing the frequency of the input gating signal IN_DQS. Based on the second frequency-divided gating signal QDQS and the fourth frequency-divided gating signal QBDQS, the gating control circuit 250 can generate a first internal gating signal DDQS1, a second internal gating signal DDQS2, and a third internal gating signal DDQS3 for aligning the first to sixteenth data DATA<1:16> in both the first and second operating modes.

[0045] The data alignment circuit 270 can synchronize with the first frequency divider strobe signal IDQS, the second frequency divider strobe signal QDQS, the third frequency divider strobe signal IBDQS, and the fourth frequency divider strobe signal QBDQS to align the first group of IN_D<1:8> and the second group of IN_D<9:16> of the input data. The data alignment circuit 270 can also synchronize with the first internal strobe signal DDQS1, the second internal strobe signal DDQS2, and the third internal strobe signal DDQS3 to align the first group of IN_D<1:8> and the second group of IN_D<9:16> of the input data.

[0046] The data alignment circuit 270 can generate first to sixteenth internal data IDs <1:16> from at least one of the first group IN_D<1:8> and the second group IN_D<9:16> of the aligned input data, synchronized with the latch clock WL and based on the logic level of the burst enable signal BCEN. The data alignment circuit 270 can perform cross-domain operations: aligning the first group IN_D<1:8> and the second group IN_D<9:16> of the input data with the first internal strobe signal DDQS1, the second internal strobe signal DDQS2, and the third internal strobe signal DDQS3 generated from the strobe signal DQS, and subsequently synchronizing with the latch clock WL generated from the clock CLK to generate first to sixteenth internal data IDs <1:16> from at least one of the first group IN_D<1:8> and the second group IN_D<9:16> of the aligned input data.

[0047] The core circuit 280 can store the first to sixteenth internal data IDs <1:16> in memory cells (not shown) selected by the write signal WT and the first to Nth internal addresses IADD <1:N>. The core circuit 280 can be implemented as a general-purpose memory circuit including multiple word lines (not shown), multiple bit lines (not shown), and multiple memory cells (not shown). The memory cells can be located at the intersection of multiple word lines and multiple bit lines. The core circuit 280 has been implemented to perform write operations, but it can also be implemented to perform operations such as activation operations, read operations, precharge operations, and refresh operations.

[0048] The semiconductor device 20 of this disclosure can perform a cross-domain operation in a first operating mode, aligning a first set of DATA<1:8> and a second set of DATA<9:16> of data synchronized with a strobe signal DQS, and subsequently generating first to sixteenth internal data IDs<1:16> from the aligned first set of DATA<1:8> and the aligned second set of DATA<9:16> of data synchronized with a clock CLK. The semiconductor device 20 can also perform a cross-domain operation in a second operating mode, aligning a first set of DATA<1:8> of data synchronized with a strobe signal DQS, and generating first to sixteenth internal data IDs<1:16> from the aligned first set of DATA<1:8> of data synchronized with a clock CLK.

[0049] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram of an example clock control circuit is shown. (See diagram for example.) Figure 3 As shown, the clock control circuit 240 may include a shift circuit 241, a latch clock generation circuit 242, and a data pulse signal generation circuit 243.

[0050] The shift circuit 241 can be implemented as multiple flip-flops (F / F) 241_1, 241_2, 241_3, 241_4, and 241_5. Flip-flop 241_1 can latch the write signal WT in sync with the input clock IN_CLK. Flip-flop 241_2 can latch the output signal of flip-flop 241_1 in sync with the input clock IN_CLK. Flip-flop 241_3 can latch the output signal of flip-flop 241_2 in sync with the input clock IN_CLK, and can output the latched output signal as the first shift signal SFC1. Flip-flop 241_4 can latch the first shift signal SFC1 in sync with the input clock IN_CLK. Flip-flop 241_5 can latch the output signal of flip-flop 241_4 in sync with the input clock IN_CLK, and can output the latched output signal as the second shift signal SFC2. The number of flip-flops included in the shift circuit 241 can be set differently in different embodiments.

[0051] The latch clock generation circuit 242 can be implemented by connecting inverters 242_1 and 242_2 in series. The latch clock generation circuit 242 can generate the latch clock WL by buffering the first shift signal SFC1. The latch clock WL can be generated by shifting the write signal WT by a write delay. The shift amount used to shift the write signal WT to generate the latch clock WL can be set differently in different embodiments.

[0052] The data pulse signal generation circuit 243 can be implemented by connecting inverters 243_1 and 243_2 in series. The data pulse signal generation circuit 243 can generate the data pulse signal DSP by buffering the second shift signal SFC2. The data pulse signal DSP can be generated by shifting the first shift signal SFC1 by two cycles of the input clock IN_CLK, wherein the first shift signal SFC1 is buffered into a latch clock WL by the latch clock generation circuit 242. The shift amount used to shift the latch clock WL to generate the data pulse signal DSP can be set differently in different embodiments.

[0053] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2 The example block diagram of the gating control circuit is shown below. Figure 4 As shown, the gating control circuit 250 may include a frequency divider gating signal generation circuit (IDQS GEN) 251 and an internal gating signal generation circuit (DDQS GEN) 252.

[0054] The frequency divider strobe signal generation circuit 251 can generate a first frequency divider strobe signal IDQS, a second frequency divider strobe signal QDQS, a third frequency divider strobe signal IBDQS, and a fourth frequency divider strobe signal QBDQS by dividing the frequency of the input strobe signal IN_DQS. The frequency divider strobe signal generation circuit 251 can also generate the first frequency divider strobe signal IDQS, the second frequency divider strobe signal QDQS, the third frequency divider strobe signal IBDQS, and the fourth frequency divider strobe signal QBDQS with a 90° phase difference between them by dividing the frequency of the input strobe signal IN_DQS.

[0055] The internal gating signal generation circuit 252 can generate a first internal gating signal DDQS1, a second internal gating signal DDQS2, and a third internal gating signal DDQS3 based on the second frequency division gating signal QDQS and the fourth frequency division gating signal QBDQS for aligning the first to sixteenth data DATA<1:16> in the first operating mode and the second operating mode.

[0056] The following will refer to Figure 5 Detailed description Figure 4 The operation of the gating control circuit 250 shown in the figure.

[0057] Figure 5 It is used to describe embodiments according to this disclosure. Figure 4 The timing diagram shows the operation of the example gating control circuit.

[0058] The gating control circuit 250 can be configured to generate a first frequency division gating signal IDQS, a second frequency division gating signal QDQS, a third frequency division gating signal IBDQS, and a fourth frequency division gating signal QBDQS, as well as a first internal gating signal DDQS1, a second internal gating signal DDQS2, and a third internal gating signal DDQS3.

[0059] The input strobe signal IN_DQS can initially be at a logic low level, and then periodically toggled between the first operating mode (BL16) and the second operating mode (BL8). At the end of the second operating mode (BL8), the input strobe signal IN_DQS can remain inactive at a logic low level until the next operation begins.

[0060] At time T11, the frequency division gating signal generation circuit 251 can generate the first frequency division gating signal IDQS by dividing the frequency of the periodically switching input gating signal IN_DQS.

[0061] At time T12, the frequency divider strobe signal generation circuit 251 can generate a second frequency divider strobe signal QDQS by dividing the frequency of the input strobe signal IN_DQS. The second frequency divider strobe signal QDQS can have a phase that lags behind the phase of the first frequency divider strobe signal IDQS by 90°.

[0062] At time T13, the frequency divider strobe signal generation circuit 251 can generate a third frequency divider strobe signal IBDQS by dividing the frequency of the input strobe signal IN_DQS. The third frequency divider strobe signal IBDQS can have a phase that lags behind the second frequency divider strobe signal QDQS by 90°.

[0063] At time T14, the frequency divider strobe signal generation circuit 251 can generate a fourth frequency divider strobe signal QBDQS by dividing the frequency of the input strobe signal IN_DQS. The fourth frequency divider strobe signal QBDQS can be generated with a phase that lags behind the phase of the third frequency divider strobe signal IBDQS by 90°.

[0064] At time T14, the internal gating signal generation circuit 252 can generate a first internal gating signal DDQS1 having the same pulse as the first pulse of the fourth frequency-divided gating signal QBDQS. Thereafter, the internal gating signal generation circuit 252 can generate the first internal gating signal DDQS1 with every other pulse of the fourth frequency-divided gating signal QBDQS.

[0065] At time T15, the internal gating signal generation circuit 252 can generate a second internal gating signal DDQS2 with the same pulse as the second pulse of the fourth frequency division gating signal QBDQS.

[0066] At time T16, the internal gating signal generation circuit 252 can generate a third internal gating signal DDQS3 with the same pulse as the fourth pulse of the fourth frequency division gating signal QBDQS.

[0067] At time T17, the internal strobe signal generation circuit 252 can generate an extended pulse for each of the second internal strobe signal DDQS2 and the third internal strobe signal DDQS3. The extended pulse can have a logic high level. The duration of the extended pulse is approximately the same as the period during which the input strobe signal IN_DQS remains low until the start of the next operation. However, the extended pulse can remain high for a longer period because they can be synchronized with the falling edge of the input strobe signal IN_DQS.

[0068] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram of the example mode control circuit is shown. (See diagram for example.) Figure 6As shown, the mode control circuit 260 may include an operation mode signal generation circuit 261 and a burst enable signal generation circuit (F / F) 262.

[0069] The operation mode signal generation circuit 261 can be implemented by connecting inverter 261_1, NOR gate 261_2, NAND gate 261_3 and inverter 261_4 in series. When receiving the mode register signal MR with a logic low level, the burst control signal BC with a logic high level and the mode setting signal OTF with a logic high level, the operation mode signal generation circuit 261 can generate an operation mode signal BC8 with a logic high level to indicate the second operation mode.

[0070] The mode register signal MR can be at a logic low level to execute the first operating mode and the second operating mode. The burst control signal BC can be at a logic high level to execute the second operating mode. The mode setting signal OTF can be at a logic high level to execute the second operating mode consecutively after executing the first operating mode.

[0071] The burst enable signal generation circuit 262 can be implemented as a flip-flop. The burst enable signal generation circuit 262 can latch the operation mode signal BC8 synchronously with the latch clock WL and can output a burst enable signal BCEN. When a latch clock WL with a logic high level is received, the burst enable signal generation circuit 262 can latch the operation mode signal BC8 and output the latched operation mode signal BC8 as the burst enable signal BCEN. The burst enable signal generation circuit 262 can generate a burst enable signal BCEN with a logic low level in the first operation mode. The burst enable signal generation circuit 262 can generate a burst enable signal BCEN with a logic high level in the second operation mode.

[0072] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 2 A block diagram of an example data alignment circuit is shown. Figure 7 As shown, the data alignment circuit 270 may include a latch data generation circuit (LD GEN) 271, a write alignment circuit (WT ALIGN) 272, and an internal data generation circuit (ID GEN) 273.

[0073] The latch data generation circuit 271 can receive the first to sixteenth input data IN_D<1:16> synchronously with the first frequency divider strobe signal IDQS, the second frequency divider strobe signal QDQS, the third frequency divider strobe signal IBDQS, and the fourth frequency divider strobe signal QBDQS. The latch data generation circuit 271 can also generate first latch data LD1, second latch data LD2, third latch data LD3, and fourth latch data LD4 from the first to sixteenth input data IN_D<1:16> synchronously with the first frequency divider strobe signal IDQS, the second frequency divider strobe signal QDQS, the third frequency divider strobe signal IBDQS, and the fourth frequency divider strobe signal QBDQS.

[0074] The first latched data LD1 can be generated by serially latching the first, fifth, ninth, and thirteenth input data IN_D<1, 5, 9, 13>. The second latched data LD2 can be generated by serially latching the second, sixth, tenth, and fourteenth input data IN_D<2, 6, 10, 14>. The third latched data LD3 can be generated by serially latching the third, seventh, eleventh, and fifteenth input data IN_D<3, 7, 11, 15>. The fourth latched data LD4 can be generated by serially latching the fourth, eighth, twelfth, and sixteenth input data IN_D<4, 8, 12, 16>.

[0075] The write alignment circuit 272 can synchronize with the first internal strobe signal DDQS1, the second internal strobe signal DDQS2, and the third internal strobe signal DDQS3 to align the bits included in the first latched data LD1, the second latched data LD2, the third latched data LD3, and the fourth latched data LD4. The write alignment circuit 272 can also synchronize with the latch clock WL and generate the first write data WD1<1:8> and the second write data WD2<1:8> from the aligned bits included in the first latched data LD1, the second latched data LD2, the third latched data LD3, and the fourth latched data LD4 based on the logic level of the burst enable signal BCEN.

[0076] The internal data generation circuit 273 can generate first to sixteenth internal data IDs <1:16> from the first written data WD1<1:8> and the second written data WD2<1:8> in sync with the data pulse signal DSP. The internal data generation circuit 273 can also generate first to eighth internal data IDs <1:8> from the first written data WD1<1:8> in sync with the data pulse signal DSP. Furthermore, the internal data generation circuit 273 can generate ninth to sixteenth internal data IDs <9:16> from the second written data WD2<1:8> in sync with the data pulse signal DSP.

[0077] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 7The block diagram of the example latch data generation circuit is shown in the image. Figure 8 As shown, the latch data generation circuit 271 may include a pre-latch data generation circuit 310 and a latch data output circuit 320.

[0078] The pre-latch data generation circuit 310 can be implemented as flip-flops (F / F) 311, 312, 313, and 314. Flip-flop 311 can generate first pre-latch data PLD1 by serially latching the first, fifth, ninth, and thirteenth input data IN_D<1,5,9,13> received on the rising edge of the first frequency divider strobe signal IDQS. Flip-flop 312 can generate second pre-latch data PLD2 by serially latching the second, sixth, tenth, and fourteenth input data IN_D<2,6,10,14> received on the rising edge of the second frequency divider strobe signal QDQS. Flip-flop 313 can generate third pre-latch data PLD3 by serially latching the third, seventh, eleventh, and fifteenth input data IN_D<3,7,11,15> received on the rising edge of the third frequency divider strobe signal IBDQS. The trigger 314 can generate the fourth pre-latch data PLD4 by serially latching the fourth, eighth, twelfth, and sixteenth input data IN_D<4,8,12,16> received on the rising edge of the fourth divider strobe signal QBDQS.

[0079] The latched data output circuit 320 can be implemented as flip-flops (F / F) 321, 322, 323, and 324. Flip-flop 321 latches the received first pre-latched data PLD1 on the rising edge of the second frequency divider strobe signal QDQS and outputs the latched first pre-latched data PLD1 as the first latched data LD1. Flip-flop 322 latches the received second pre-latched data PLD2 on the rising edge of the second frequency divider strobe signal QDQS and outputs the latched second pre-latched data PLD2 as the second latched data LD2. Flip-flop 323 latches the received third pre-latched data PLD3 on the rising edge of the fourth frequency divider strobe signal QBDQS and outputs the latched third pre-latched data PLD3 as the third latched data LD3. Flip-flop 324 latches the received fourth pre-latched data PLD4 on the rising edge of the fourth frequency divider strobe signal QBDQS and outputs the latched fourth pre-latched data PLD4 as the fourth latched data LD4.

[0080] Figure 9 This illustrates an embodiment according to the present disclosure. Figure 7 The example in the diagram is written into the block diagram of the alignment circuit. For example... Figure 9 As shown, the write alignment circuit 272 may include an alignment data generation circuit (AD GEN) 410 and a write data generation circuit (WD GEN) 420.

[0081] The alignment data generation circuit 410 can synchronize with the first internal strobe signal DDQS1, the second internal strobe signal DDQS2, and the third internal strobe signal DDQS3 to align the bits included in the first latched data LD1, the second latched data LD2, the third latched data LD3, and the fourth latched data LD4. The alignment data generation circuit 410 can synchronize with the first internal strobe signal DDQS1, the second internal strobe signal DDQS2, and the third internal strobe signal DDQS3 to generate first aligned data AD1<1:8> and second aligned data AD2<1:8> from the aligned first latched data LD1, the second latched data LD2, the third latched data LD3, and the fourth latched data LD4.

[0082] The write data generation circuit 420 can generate first write data WD1<1:8> and second write data WD2<1:8> from the first aligned data AD1<1:8> and the second aligned data AD2<1:8> based on the logic level of the burst enable signal BCEN, synchronized with the latch clock WL. In a first operating mode, the write data generation circuit 420 can also generate first write data WD1<1:8> and second write data WD2<1:8> from the first aligned data AD1<1:8> and the second aligned data AD2<1:8> based on the logic level of the burst enable signal BCEN. In a second operating mode, the write data generation circuit 420 can also generate first write data WD1<1:8> and second write data WD2<1:8> from the first aligned data AD1<1:8> based on the logic level of the burst enable signal BCEN, synchronized with the latch clock WL.

[0083] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 9 The block diagram of an example aligned data generation circuit is shown below. Figure 10 As shown, the alignment data generation circuit 410 may include a first alignment data generation circuit (first AD GEN) 411 and a second alignment data generation circuit (second AD GEN) 412.

[0084] The first alignment data generation circuit 411 can receive the first latched data LD1 and the second latched data LD2 in synchronization with the first internal strobe signal DDQS1. The first alignment data generation circuit 411 can generate the first to fourth bits AD1<1:4> of the first alignment data and the first to fourth bits AD2<1:4> of the second alignment data from the first latched data LD1 and the second latched data LD2 in synchronization with the second internal strobe signal DDQS2 and the third internal strobe signal DDQS3.

[0085] The second alignment data generation circuit 412 can receive the third latched data LD3 and the fourth latched data LD4 in sync with the first internal strobe signal DDQS1. The second alignment data generation circuit 412 can generate the fifth to eighth bits AD1<5:8> of the first alignment data and the fifth to eighth bits AD2<5:8> of the second alignment data from the third latched data LD3 and the fourth latched data LD4 in sync with the second internal strobe signal DDQS2 and the third internal strobe signal DDQS3.

[0086] Figure 11 This illustrates an embodiment according to the present disclosure. Figure 10 The block diagram of the example first aligned data generation circuit is shown in the figure. Figure 11 As shown, the first alignment data generation circuit 411 may include a first latch (LC) 411_1, a second latch (LC) 411_2, a third latch (LC) 411_3, a fourth latch (LC) 411_4, and a fifth latch (LC) 411_5.

[0087] The first latch 411_1 can generate the first pre-aligned data PAD1 by latching the first latched data LD1 in sync with the first internal strobe signal DDQS1. The first latch 411_1 can generate the second pre-aligned data PAD2 by latching the second latched data LD2 in sync with the first internal strobe signal DDQS1.

[0088] The second latch 411_2 can generate the first bit AD1 of the first alignment data by latching the first pre-aligned data PAD1 in synchronization with the second internal strobe signal DDQS2. <1> The second latch 411_2 can generate the second bit AD1 of the first aligned data by latching the second pre-aligned data PAD2 in sync with the second internal strobe signal DDQS2. <2> .

[0089] The third latch 411_3 can generate the first bit AD2 of the second alignment data by latching the first pre-aligned data PAD1 in sync with the third internal strobe signal DDQS3. <1> The third latch 411_3 can generate the second bit AD2 of the second aligned data by latching the second pre-aligned data PAD2 in sync with the third internal strobe signal DDQS3. <2> .

[0090] The fourth latch 411_4 can generate the third bit AD1 of the first aligned data by latching the first latched data LD1 in sync with the second internal strobe signal DDQS2. <3> The fourth latch 411_4 can generate the fourth bit AD1 of the first aligned data by latching the second latched data LD2 in sync with the second internal strobe signal DDQS2. <4> .

[0091] The fifth latch 411_5 can generate the third bit AD2 of the second aligned data by latching the first latched data LD1 in sync with the third internal strobe signal DDQS3. <3> The fifth latch 411_5 can generate the fourth bit AD2 of the second aligned data by latching the second latched data LD2 in sync with the third internal strobe signal DDQS3. <4> .

[0092] Figure 12 This illustrates an embodiment according to the present disclosure. Figure 10 The block diagram of the example second aligned data generation circuit is shown in the figure. Figure 12 As shown, the second aligned data generation circuit 412 may include a sixth latch (LC) 412_1, a seventh latch (LC) 412_2, an eighth latch (LC) 412_3, a ninth latch (LC) 412_4, and a tenth latch (LC) 412_5.

[0093] The sixth latch 412_1 can generate the third pre-aligned data PAD3 by latching the third latched data LD3 in sync with the first internal strobe signal DDQS1. The sixth latch 412_1 can generate the fourth pre-aligned data PAD4 by latching the fourth latched data LD4 in sync with the first internal strobe signal DDQS1.

[0094] The seventh latch 412_2 can generate the fifth bit AD1 of the first aligned data by latching the third pre-aligned data PAD3 in sync with the second internal strobe signal DDQS2. <5> The seventh latch 412_2 can generate the sixth bit AD1 of the first aligned data by latching the fourth pre-aligned data PAD4 in sync with the second internal strobe signal DDQS2. <6> .

[0095] The eighth latch 412_3 can generate the fifth bit AD2 of the second aligned data by latching the third pre-aligned data PAD3 in sync with the third internal strobe signal DDQS3. <5> The eighth latch 412_3 can generate the sixth bit AD2 of the second aligned data by latching the fourth pre-aligned data PAD4 in sync with the third internal strobe signal DDQS3. <6> .

[0096] The ninth latch 412_4 can generate the seventh bit AD1 of the first aligned data by latching the third latched data LD3 in sync with the second internal strobe signal DDQS2. <7> The ninth latch 412_4 can generate the eighth bit AD1 of the first aligned data by latching the fourth latched data LD4 in sync with the second internal strobe signal DDQS2. <8> .

[0097] The tenth latch 412_5 can generate the seventh bit AD2 of the second aligned data by latching the third latched data LD3 in sync with the third internal strobe signal DDQS3. <7> The tenth latch 412_5 can generate the eighth bit AD2 of the second aligned data by latching the fourth latched data LD4 in sync with the third internal strobe signal DDQS3. <8> .

[0098] Figure 13 This illustrates an embodiment according to the present disclosure. Figure 9 The example block diagram of the write data generation circuit is shown below. Figure 13 As shown, the write data generation circuit 420 may include a first write data generation circuit (first WD GEN) 421 and a second write data generation circuit (second WD GEN) 422.

[0099] The first write data generation circuit 421 can generate the first to fourth bits of the first write data WD1<1:4> and the second write data WD2<1:4> from the first to fourth bits of the first aligned data AD1<1:4> and the second aligned data AD2<1:4>, respectively. These bits can be generated based on the logic level of the burst enable signal BCEN, synchronized with the latch clock WL, in either the first or second operating mode.

[0100] The second write data generation circuit 422 can generate the fifth to eighth bits of the first write data WD1<5:8> and the fifth to eighth bits of the second write data WD2<5:8> from the fifth to eighth bits of the first aligned data AD1<5:8> and the fifth to eighth bits of the second aligned data AD2<5:8>, respectively. These bits can be generated based on the logic level of the burst enable signal BCEN, synchronized with the latch clock WL, in either the first or second operating mode.

[0101] Figure 14 This illustrates an embodiment according to the present disclosure. Figure 13 The example shown is a block diagram of the first write data generation circuit. Figure 14 As shown, the first write data generation circuit 421 may include an eleventh latch (LC) 421_1, a first selection pass circuit (MUX) 421_2, a twelfth latch (LC) 421_3, and a second selection pass circuit (MUX) 421_4.

[0102] The eleventh latch 421_1 can generate the first and second bits of the first write data WD1<1:2> by latching the first and second bits AD1<1:2> of the first aligned data in sync with the latch clock WL. The eleventh latch 421_1 can generate the first and second bits PWD1<1:2> of the first pre-write data by latching the first and second bits AD1<1:2> of the first aligned data in sync with the latch clock WL.

[0103] The first selection pass circuit 421_2 can generate the first and second bits of the second write data WD2<1:2> from the first and second bits AD2<1:2> of the second aligned data in the first operating mode when the level of the burst enable signal BCEN is disabled and is at a logic low level. The first selection pass circuit 421_2 can also generate the first and second bits of the second write data WD2<1:2> from the first and second bits PWD1<1:2> of the first pre-write data in the second operating mode when the level of the burst enable signal BCEN is enabled and is at a logic high level.

[0104] The twelfth latch 421_3 can generate the third and fourth bits of the first write data WD1<3:4> by latching the third and fourth bits of the first aligned data AD1<3:4> in sync with the latch clock WL. The twelfth latch 421_3 can generate the third and fourth bits of the first pre-write data PWD1<3:4> by latching the third and fourth bits of the first aligned data AD1<3:4> in sync with the latch clock WL.

[0105] The second selection pass circuit 421_4 can generate the third and fourth bits of the second write data WD2<3:4> from the third and fourth bits AD2<3:4> of the second aligned data in the first operating mode when the burst enable signal BCEN is disabled and is at a logic low level. The second selection pass circuit 421_4 can also generate the third and fourth bits of the second write data WD2<3:4> from the third and fourth bits PWD1<3:4> of the first pre-write data in the second operating mode when the burst enable signal BCEN is enabled and is at a logic high level.

[0106] Figure 15 This illustrates an embodiment according to the present disclosure. Figure 13 The block diagram of the example second write data generation circuit is shown in the figure. Figure 15 As shown, the second write data generation circuit 422 may include a thirteenth latch (LC) 422_1, a third selection pass circuit (MUX) 422_2, a fourteenth latch (LC) 422_3, and a fourth selection pass circuit (MUX) 422_4.

[0107] The thirteenth latch 422_1 can generate the fifth and sixth bits of the first write data WD1<5:6> by latching the fifth and sixth bits AD1<5:6> of the first aligned data in sync with the latch clock WL. The thirteenth latch 422_1 can also generate the first and second bits PWD2<1:2> of the second pre-write data by latching the fifth and sixth bits AD1<5:6> of the first aligned data in sync with the latch clock WL.

[0108] The third selection pass circuit 422_2 can generate the fifth and sixth bits of the second write data WD2<5:6> from the fifth and sixth bits AD2<5:6> of the second aligned data in the first operating mode when the burst enable signal BCEN is disabled and is at a logic low level. The third selection pass circuit 422_2 can also generate the fifth and sixth bits of the second write data WD2<5:6> from the first and second bits PWD2<1:2> of the second pre-write data in the second operating mode when the burst enable signal BCEN is enabled and is at a logic high level.

[0109] The fourteenth latch 422_3 can generate the seventh and eighth bits of the first write data WD1<7:8> by latching the seventh and eighth bits AD1<7:8> of the first aligned data in sync with the latch clock WL. The fourteenth latch 422_3 can also generate the third and fourth bits PWD2<3:4> of the second pre-write data by latching the seventh and eighth bits AD1<7:8> of the first aligned data in sync with the latch clock WL.

[0110] The fourth selection pass circuit 422_4 can generate the seventh and eighth bits of the second write data WD2<7:8> from the seventh and eighth bits AD2<7:8> of the second aligned data in the first operating mode when the burst enable signal BCEN is disabled and is at a logic low level. The fourth selection pass circuit 422_4 can also generate the seventh and eighth bits of the second write data WD2<7:8> from the third and fourth bits PWD2<3:4> of the second pre-write data in the second operating mode when the burst enable signal BCEN is enabled and is at a logic high level.

[0111] Figure 16 This illustrates an embodiment according to the present disclosure. Figure 7 The block diagram of the example internal data generation circuit is shown below. Figure 16 As shown, the internal data generation circuit 273 may include a fifteenth latch (LC) 273_1 and a sixteenth latch (LC) 273_2.

[0112] The fifteenth latch 273_1 can generate the first to eighth internal data IDs <1:8> by latching the first write data WD1<1:8> in sync with the data pulse signal DSP.

[0113] The sixteenth latch 273_2 can generate the ninth to sixteenth internal data IDs <9:16> by latching the second write data WD2<1:8> in sync with the data pulse signal DSP.

[0114] Reference Figures 17 to 19 The data alignment operation of a semiconductor system according to an embodiment of the present disclosure is described below, taking the case of continuously executing a first operation mode and a second operation mode as an example.

[0115] Figure 17 This is a timing diagram describing an example data alignment operation of a semiconductor system according to an embodiment of the present disclosure.

[0116] When executing the first and second operating modes consecutively, the operation reference for generating the first latch data LD1, the second latch data LD2, the third latch data LD3, and the fourth latch data LD4 from the first to the sixteenth input data IN_D<1:16> is as follows. Figure 17 The description is as follows.

[0117] The input strobe signal IN_DQS is triggered to strobe the input data only within the interval where the data is input. In the first operating mode, the length of the input data can be set to a burst length of 16 (BL16), and the first to sixteenth input data IN_D<1:16> are received serially.

[0118] At time T21, the frequency division strobe signal generation circuit 251 can generate the first frequency division strobe signal IDQS by dividing the frequency of the input strobe signal IN_DQS.

[0119] The pre-latch data generation circuit 310 can latch the received first input data IN_D on the rising edge of the first frequency divider strobe signal IDQS. <1> To generate the first pre-latched data PLD1.

[0120] At time T22, the frequency division gating signal generation circuit 251 can generate a second frequency division gating signal QDQS by dividing the frequency of the input gating signal IN_DQS.

[0121] The pre-latch data generation circuit 310 can latch the received second input data IN_D on the rising edge of the second frequency divider strobe signal QDQS. <2> To generate the second pre-latched data PLD2.

[0122] The latched data output circuit 320 can latch the received first pre-latched data PLD1 on the rising edge of the second frequency divider strobe signal QDQS, and can output the latched first pre-latched data PLD1 as the first latched data LD1. The latched data output circuit 320 can also latch the received second pre-latched data PLD2 on the rising edge of the second frequency divider strobe signal QDQS, and can output the latched second pre-latched data PLD2 as the second latched data LD2.

[0123] At time T23, the frequency division gating signal generation circuit 251 can generate a third frequency division gating signal IBDQS by dividing the frequency of the input gating signal IN_DQS.

[0124] The pre-latch data generation circuit 310 can latch the received third input data IN_D on the rising edge of the third-order frequency strobe signal IBDQS. <3> To generate the third pre-latched data PLD3.

[0125] At time T24, the frequency division gating signal generation circuit 251 can generate a fourth frequency division gating signal QBDQS by dividing the frequency of the input gating signal IN_DQS.

[0126] The pre-latch data generation circuit 310 can latch the received fourth input data IN_D on the rising edge of the fourth frequency divider strobe signal QBDQS. <4> To generate the fourth pre-latched data PLD4.

[0127] The latched data output circuit 320 can latch the received third pre-latched data PLD3 on the rising edge of the fourth frequency divider strobe signal QBDQS, and can output the latched third pre-latched data PLD3 as the third latched data LD3. The latched data output circuit 320 can also latch the received fourth pre-latched data PLD4 on the rising edge of the fourth frequency divider strobe signal QBDQS, and can output the latched fourth pre-latched data PLD4 as the fourth latched data LD4.

[0128] Subsequently, the operation of generating the first latched data LD1, the second latched data LD2, the third latched data LD3, and the fourth latched data LD4 from the fifth to the sixteenth input data IN_D<5:16> is the same as the operation of generating the first latched data LD1, the second latched data LD2, the third latched data LD3, and the fourth latched data LD4 from the first to the fourth input data IN_D<1:4>, therefore its detailed description is omitted.

[0129] In the second operating mode, the length of the input data can be set to a burst length of 8 (BL8), and the sixteenth input data IN_D <16> After being received in the first operating mode, the first to eighth input data IN_D<1:8> are received serially.

[0130] At time T25, the frequency division strobe signal generation circuit 251 can generate the first frequency division strobe signal IDQS by dividing the frequency of the input strobe signal IN_DQS.

[0131] The pre-latch data generation circuit 310 can latch the received first input data IN_D on the rising edge of the first frequency divider strobe signal IDQS. <1> To generate the first pre-latched data PLD1.

[0132] At time T26, the frequency division gating signal generation circuit 251 can generate a second frequency division gating signal QDQS by dividing the frequency of the input gating signal IN_DQS.

[0133] The pre-latch data generation circuit 310 can latch the received second input data IN_D on the rising edge of the second frequency divider strobe signal QDQS. <2> To generate the second pre-latched data PLD2.

[0134] The latched data output circuit 320 can latch the received first pre-latched data PLD1 on the rising edge of the second frequency divider strobe signal QDQS, and can output the latched first pre-latched data PLD1 as the first latched data LD1. The latched data output circuit 320 can also latch the received second pre-latched data PLD2 on the rising edge of the second frequency divider strobe signal QDQS, and can output the latched second pre-latched data PLD2 as the second latched data LD2.

[0135] At time T27, the frequency division strobe signal generation circuit 251 can generate a third frequency division strobe signal IBDQS by dividing the frequency of the input strobe signal IN_DQS.

[0136] The pre-latch data generation circuit 310 can latch the received third input data IN_D on the rising edge of the third-order frequency strobe signal IBDQS. <3> To generate the third pre-latched data PLD3.

[0137] At time T28, the frequency division gating signal generation circuit 251 can generate a fourth frequency division gating signal QBDQS by dividing the frequency of the input gating signal IN_DQS.

[0138] The pre-latch data generation circuit 310 can latch the received fourth input data IN_D on the rising edge of the fourth frequency divider strobe signal QBDQS. <4> To generate the fourth pre-latched data PLD4.

[0139] The latched data output circuit 320 can latch the received third pre-latched data PLD3 on the rising edge of the fourth frequency divider strobe signal QBDQS, and can output the latched third pre-latched data PLD3 as the third latched data LD3. The latched data output circuit 320 can also latch the received fourth pre-latched data PLD4 on the rising edge of the fourth frequency divider strobe signal QBDQS, and can output the latched fourth pre-latched data PLD4 as the fourth latched data LD4.

[0140] Subsequently, the operation of generating the first latched data LD1, the second latched data LD2, the third latched data LD3, and the fourth latched data LD4 from the fifth to the eighth input data IN_D<5:8> is the same as the operation of generating the first latched data LD1, the second latched data LD2, the third latched data LD3, and the fourth latched data LD4 from the first to the fourth input data IN_D<1:4>, therefore its detailed description is omitted.

[0141] Figure 18 This is a timing diagram describing an example data alignment operation of a semiconductor system according to an embodiment of the present disclosure.

[0142] When the first and second operating modes are executed consecutively, the operation reference for generating the first alignment data AD1<1:8> and the second alignment data AD2<1:8> from the first latched data LD1, the second latched data LD2, the third latched data LD3, and the fourth latched data LD4 is as follows. Figure 18 As described below.

[0143] At time T31, the internal gating signal generation circuit 252 can generate a first internal gating signal DDQS1 based on the second frequency-divided gating signal QDQS and the fourth frequency-divided gating signal QBDQS. Time T31 can be compared with a reference. Figure 17 The time T24 described is the same time.

[0144] The first latch 411_1 of the first alignment data generation circuit 411 can generate first pre-aligned data PAD1 by latching first latched data LD1 in sync with the first internal strobe signal DDQS1. The first latch 411_1 can generate second pre-aligned data PAD2 by latching second latched data LD2 in sync with the first internal strobe signal DDQS1.

[0145] The sixth latch 412_1 of the second alignment data generation circuit 412 can generate the third pre-aligned data PAD3 by latching the third latched data LD3 in sync with the first internal strobe signal DDQS1. The sixth latch 412_1 can generate the fourth pre-aligned data PAD4 by latching the fourth latched data LD4 in sync with the first internal strobe signal DDQS1.

[0146] At time T32, the internal gating signal generation circuit 252 can generate a second internal gating signal DDQS2 based on the second frequency-divided gating signal QDQS and the fourth frequency-divided gating signal QBDQS. Time T32 can be the time for generating the second pulse of the fourth frequency-divided gating signal QBDQS.

[0147] The second latch 411_2 of the first alignment data generation circuit 411 can generate the first bit AD1 of the first alignment data by latching the first pre-aligned data PAD1 in sync with the second internal strobe signal DDQS2. <1> The second latch 411_2 can generate the second bit AD1 of the first aligned data by latching the second pre-aligned data PAD2 in sync with the second internal strobe signal DDQS2. <2> The fourth latch 411_4 can generate the third bit AD1 of the first aligned data by latching the first latched data LD1 in sync with the second internal strobe signal DDQS2. <3> The fourth latch 411_4 can generate the fourth bit AD1 of the first aligned data by latching the second latched data LD2 in sync with the second internal strobe signal DDQS2. <4> .

[0148] The seventh latch 412_2 of the second alignment data generation circuit 412 can generate the fifth bit AD1 of the first alignment data by latching the third pre-alignment data PAD3 in sync with the second internal strobe signal DDQS2. <5> The seventh latch 412_2 can generate the sixth bit AD1 of the first aligned data by latching the fourth pre-aligned data PAD4 in sync with the second internal strobe signal DDQS2. <6> The ninth latch 412_4 can generate the seventh bit AD1 of the first aligned data by latching the third latched data LD3 in sync with the second internal strobe signal DDQS2. <7> The ninth latch 412_4 can generate the eighth bit AD1 of the first aligned data by latching the fourth latched data LD4 in sync with the second internal strobe signal DDQS2. <8> .

[0149] The first alignment data AD1<1:8> generated at time T32 can be generated from the first to eighth input data IN_D<1:8> received serially in the first operating mode.

[0150] At time T33, the internal gating signal generation circuit 252 can generate a first internal gating signal DDQS1 based on the second frequency-divided gating signal QDQS and the fourth frequency-divided gating signal QBDQS. Time T33 can be the time when the third pulse of the fourth frequency-divided gating signal QBDQS is generated.

[0151] The first latch 411_1 of the first alignment data generation circuit 411 can generate first pre-aligned data PAD1 by latching first latched data LD1 in sync with the first internal strobe signal DDQS1. The first latch 411_1 can generate second pre-aligned data PAD2 by latching second latched data LD2 in sync with the first internal strobe signal DDQS1.

[0152] The sixth latch 412_1 of the second alignment data generation circuit 412 can generate the third pre-aligned data PAD3 by latching the third latched data LD3 in sync with the first internal strobe signal DDQS1. The sixth latch 412_1 can generate the fourth pre-aligned data PAD4 by latching the fourth latched data LD4 in sync with the first internal strobe signal DDQS1.

[0153] At time T34, the internal gating signal generation circuit 252 can generate a third internal gating signal DDQS3 based on the second frequency-divided gating signal QDQS and the fourth frequency-divided gating signal QBDQS. Time T34 can be set to the time for generating the fourth pulse of the fourth frequency-divided gating signal QBDQS.

[0154] The third latch 411_3 of the first alignment data generation circuit 411 can generate the first bit AD2 of the second alignment data by latching the first pre-aligned data PAD1 in sync with the third internal strobe signal DDQS3. <1> The third latch 411_3 can generate the second bit AD2 of the second aligned data by latching the second pre-aligned data PAD2 in sync with the third internal strobe signal DDQS3. <2> The fifth latch 411_5 can generate the third bit AD2 of the second aligned data by latching the first latched data LD1 in sync with the third internal strobe signal DDQS3. <3> The fifth latch 411_5 can generate the fourth bit AD2 of the second aligned data by latching the second latched data LD2 in sync with the third internal strobe signal DDQS3. <4> .

[0155] The eighth latch 412_3 of the second alignment data generation circuit 412 can generate the fifth bit AD2 of the second alignment data by latching the third pre-aligned data PAD3 in sync with the third internal strobe signal DDQS3. <5> The eighth latch 412_3 can generate the sixth bit AD2 of the second aligned data by latching the fourth pre-aligned data PAD4 in sync with the third internal strobe signal DDQS3. <6> The tenth latch 412_5 can generate the seventh bit AD2 of the second aligned data by latching the third latched data LD3 in sync with the third internal strobe signal DDQS3. <7> The tenth latch 412_5 can generate the eighth bit AD2 of the second aligned data by latching the fourth latched data LD4 in sync with the third internal strobe signal DDQS3. <8> .

[0156] The second alignment data AD2<1:8> generated at time T34 can be generated from the ninth to sixteenth input data IN_D<9:16> received serially in the first operating mode.

[0157] At time T35, the internal gating signal generation circuit 252 can generate a first internal gating signal DDQS1 based on the second frequency-divided gating signal QDQS and the fourth frequency-divided gating signal QBDQS. Time T35 can be the time for generating the fifth pulse of the fourth frequency-divided gating signal QBDQS.

[0158] The first latch 411_1 of the first alignment data generation circuit 411 can generate first pre-aligned data PAD1 by latching first latched data LD1 in sync with the first internal strobe signal DDQS1. The first latch 411_1 can generate second pre-aligned data PAD2 by latching second latched data LD2 in sync with the first internal strobe signal DDQS1.

[0159] The sixth latch 412_1 of the second alignment data generation circuit 412 can generate the third pre-aligned data PAD3 by latching the third latched data LD3 in sync with the first internal strobe signal DDQS1. The sixth latch 412_1 can generate the fourth pre-aligned data PAD4 by latching the fourth latched data LD4 in sync with the first internal strobe signal DDQS1.

[0160] At time T36, the internal gating signal generation circuit 252 can simultaneously generate the second internal gating signal DDQS2 and the third internal gating signal DDQS3 based on the unswitched second frequency division gating signal QDQS and fourth frequency division gating signal QBDQS.

[0161] The second latch 411_2 of the first alignment data generation circuit 411 can generate the first bit AD1 of the first alignment data by latching the first pre-aligned data PAD1 in sync with the second internal strobe signal DDQS2. <1> The second latch 411_2 can generate the second bit AD1 of the first aligned data by latching the second pre-aligned data PAD2 in sync with the second internal strobe signal DDQS2. <2> .

[0162] In T36, the third latch 411_3 can generate the first bit AD2 of the second alignment data by latching the first pre-aligned data PAD1 in sync with the third internal strobe signal DDQS3. <1> In T36, the third latch 411_3 can generate the second bit AD2 of the second aligned data by latching the second pre-aligned data PAD2 in sync with the third internal strobe signal DDQS3. <2> .

[0163] The fourth latch 411_4 can generate the third bit AD1 of the first aligned data by latching the first latched data LD1 in sync with the second internal strobe signal DDQS2. <3> The fourth latch 411_4 can generate the fourth bit AD1 of the first aligned data by latching the second latched data LD2 in sync with the second internal strobe signal DDQS2. <4> .

[0164] The fifth latch 411_5 can generate the third bit AD2 of the second aligned data by latching the first latched data LD1 in sync with the third internal strobe signal DDQS3. <3> The fifth latch 411_5 can generate the fourth bit AD2 of the second aligned data by latching the second latched data LD2 in sync with the third internal strobe signal DDQS3. <4> .

[0165] The seventh latch 412_2 of the second alignment data generation circuit 412 can generate the fifth bit AD1 of the first alignment data by latching the third pre-alignment data PAD3 in sync with the second internal strobe signal DDQS2. <5> The seventh latch 412_2 can generate the sixth bit AD1 of the first aligned data by latching the fourth pre-aligned data PAD4 in sync with the second internal strobe signal DDQS2. <6> .

[0166] The eighth latch 412_3 can generate the fifth bit AD2 of the second aligned data by latching the third pre-aligned data PAD3 in sync with the third internal strobe signal DDQS3. <5> The eighth latch 412_3 can generate the sixth bit AD2 of the second aligned data by latching the fourth pre-aligned data PAD4 in sync with the third internal strobe signal DDQS3. <6> .

[0167] The ninth latch 412_4 can generate the seventh bit AD1 of the first aligned data by latching the third latched data LD3 in sync with the second internal strobe signal DDQS2. <7> The ninth latch 412_4 can generate the eighth bit AD1 of the first aligned data by latching the fourth latched data LD4 in sync with the second internal strobe signal DDQS2. <8> .

[0168] The tenth latch 412_5 can generate the seventh bit AD2 of the second aligned data by latching the third latched data LD3 in sync with the third internal strobe signal DDQS3. <7> The tenth latch 412_5 can generate the eighth bit AD2 of the second aligned data by latching the fourth latched data LD4 in sync with the third internal strobe signal DDQS3. <8> .

[0169] The first alignment data AD1<1:8> and the second alignment data AD2<1:8> generated at time T36 can be generated from the first to eighth input data IN_D<1:8> received serially in the second operating mode.

[0170] Figure 19 This is a timing diagram describing an example data alignment operation according to an embodiment of the present disclosure.

[0171] Figure 19 The timing diagram shows the latch clock WL, the data pulse signal DSP, the burst enable signal BCEN, the eight bits of the first write data WD1, the eight bits of the second write data WD2, and the sixteen bits of the internal data ID.

[0172] Before time T41, the latch clock WL is in a logic low state, the data pulse signal DSP is in a logic low state, and the burst enable signal BCEN is in a logic low state to indicate a 16-bit burst operation.

[0173] At time T41, the latch clock WL switches to logic high. The first and second write data WD1 and WD2, initially received serially as 16-bit DATA, are aligned as first and second write data WD1 and WD2 by the write alignment circuit 272 and latched. The first and second write data WD1 and WD2 are latched by the latch clock WL and output to the internal data generation circuit 273.

[0174] At time T42, the latch clock WL switches to logic low.

[0175] At time T43, the data pulse signal DSP is asserted to a logic high state. This allows the internal data generation circuit 273 to latch eight bits of WD1 and eight bits of WD2 from the write alignment circuit 272 to output a 16-bit internal data ID<1:16>. The 16-bit internal data ID<1:16> can now be written to a memory device, such as the core circuit 280.

[0176] At time T44, the data pulse signal DSP is deasserted and enters a logic low state.

[0177] At time T45, the burst enable signal BCEN goes high to indicate an 8-bit burst operation, and the latch clock WL switches to high. Therefore, the next set of first and second write data WD1 and WD2 is latched by the alignment circuit 272 and provided to the internal data generation circuit 273.

[0178] At time T46, the latch clock WL switches to logic low.

[0179] At time T47, the data pulse signal DSP is activated in a logic high state. This enables the internal data generation circuit 273 to latch eight bits of WD1<1:8> and eight bits of WD2<1:8> to output 16 bits of internal data ID<1:16>.

[0180] At time T48, the data pulse signal DSP fails and enters a logic low state.

[0181] Therefore, the example operation Figure 19 The timing diagram shows that the write data generated by the data alignment circuit performing the data alignment operation ensures that the write data has the same data window when executing the first and second operating modes consecutively. This allows for ensuring time margins for cross-domain operations by generating write data with the same data window when executing the first and second operating modes consecutively.

[0182] Figure 20 This is a block diagram illustrating an example electronic system according to an embodiment of the present disclosure. (e.g.) Figure 20 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200.

[0183] The host 1100 and the semiconductor system 1200 can transmit signals using interface protocols such as Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect-Fast (PCI-E), Advanced Technology Accessories (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), and Universal Serial Bus (USB).

[0184] Semiconductor system 1200 may include controller 1300 and one or more semiconductor devices 1400. Controller 1300 may control the operation of semiconductor devices 1400. Each semiconductor device 1400 may generate write data generated by a data alignment circuit performing a data alignment operation, such that the write data has the same data window when consecutively executing a first operating mode and a second operating mode. Each semiconductor device 1400 can ensure time margin for cross-domain operations by generating write data generated in the data alignment circuit performing the data alignment operation, such that the write data has the same data window when consecutively executing a first operating mode and a second operating mode.

[0185] Controller 1300 can be implemented as Figure 1 The controller 10 is shown. One or more semiconductor devices 1400 can be implemented as follows: Figure 1 The semiconductor device 20 is shown. According to an embodiment, the semiconductor device 20 can be implemented using one or more of the following: dynamic random access memory (DRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM).

Claims

1. A semiconductor device, comprising: Alignment data generation circuit, which: Synchronized with the first internal strobe signal to align the first latched data and the second latched data generated from the first set of input data; Output the first latched data and the second latched data that are aligned as the first aligned data; The first latched data and the second latched data generated from the second set of the input data are synchronized with the second internal strobe signal; The first and second latched data are output as the second aligned data; and Write to the data generation circuit, which: After the first operating mode begins, first write data and second write data are generated from the first aligned data and the second aligned data in synchronization with the latch clock; and After the second operating mode begins, the first write data and the second write data are generated from the first aligned data in sync with the latch clock. The first written data and the second written data have the same data window in consecutive operations of the first operation mode and the second operation mode.

2. The semiconductor device according to claim 1, wherein: The first internal gating signal and the second internal gating signal are generated synchronously with the gating signal, and The latch clock is generated in sync with the clock.

3. The semiconductor device according to claim 2, wherein, The strobe signal is triggered only within the range where the input data is input in the first operating mode and the second operating mode.

4. The semiconductor device according to claim 1, wherein: The input data used to generate the first latched data and the second latched data in the first operating mode is input as 2N bits, and The input data used to generate the first latched data and the second latched data in the second operating mode is input as N bits. Where N is a positive integer.

5. The semiconductor device according to claim 1, wherein, The alignment data generation circuit includes: The first latch generates bits of the first aligned data by latching first pre-aligned data and second pre-aligned data generated from the first latched data and the second latched data in sync with the first internal strobe signal; The second latch generates the bits of the second aligned data by latching the first pre-aligned data and the second pre-aligned data in sync with the second internal strobe signal; A third latch generates bits of the first aligned data by latching the first latched data and the second latched data in synchronization with the first internal strobe signal; and The fourth latch generates the bits of the second aligned data by latching the first latched data and the second latched data in sync with the second internal strobe signal.

6. The semiconductor device according to claim 1, wherein, The write data generation circuit includes: The fifth latch generates the bits of the first written data and the bits of the first pre-written data by latching the bits of the first aligned data in sync with the latch clock. A first selection pass circuit generates the bits of the second write data from either the bits of the first pre-written data or the bits of the second aligned data based on the logic level of the burst enable signal. A sixth latch generates the bits of the first write data and the bits of the first pre-write data by latching the bits of the first aligned data in sync with the latch clock; and The second selection transmission circuit generates the bits of the second write data from either the bits of the first pre-written data or the bits of the second aligned data based on the logic level of the burst enable signal.

7. The semiconductor device according to claim 6, wherein, First selection transmission circuit: When the burst enable signal is disabled in the first operating mode, the bits of the second write data are generated from the bits of the second aligned data; as well as When the burst enable signal is enabled in the second operation mode, the bits of the second write data are generated from the bits of the first pre-written data.

8. The semiconductor device according to claim 6, wherein, Second selection transmission circuit: When the burst enable signal is disabled in the first operating mode, the bits of the second write data are generated from the bits of the second aligned data; as well as When the burst enable signal is enabled in the second operation mode, the bits of the second write data are generated from the bits of the first pre-written data.

9. A semiconductor device, comprising: The mode control circuit generates a burst enable signal that is enabled in the second operating mode, which is synchronized with a latch clock generated from a clock and based on a mode register signal, a burst control signal, and a mode setting signal for setting a first operating mode and a second operating mode. as well as The data alignment circuit, which is: The first and second groups of input data are synchronized with the first to the third internal gating signals generated from the gating signals; Synchronized with the latch clock and based on the logic level of the burst enable signal, first write data and second write data are generated from at least one of the first and second groups of aligned input data; and Internal data is generated from the first written data and the second written data.

10. The semiconductor device according to claim 9, wherein, The mode control circuit includes: An operation mode signal generation circuit generates an operation mode signal enabled in the second operation mode based on a logic level combination of the mode register signal, the burst control signal, and the mode setting signal; and A burst enable signal generation circuit generates the burst enable signal by latching the operation mode signal in sync with the latch clock.

11. The semiconductor device according to claim 9, wherein, The data alignment circuit performs cross-domain operations: aligning the first and second groups of the input data in sync with the first internal strobe signal to the third internal strobe signal, and generating the internal data from at least one of the aligned first and second groups of the input data in sync with the latch clock.

12. The semiconductor device according to claim 9, wherein, The data alignment circuit: after the first operation mode begins, aligns the first and second groups of the input data, and generates the internal data from the aligned first and second groups of the input data.

13. The semiconductor device according to claim 9, wherein, The data alignment circuit: after the second operation mode begins, aligns the first set of input data and generates the internal data from the aligned first set of input data.

14. The semiconductor device according to claim 9, wherein, In consecutive operations of the first operation mode and the second operation mode, the first written data and the second written data have the same data window.

15. The semiconductor device according to claim 9, wherein, The data alignment circuit includes: A latched data generation circuit generates first latched data to fourth latched data by latching the first and second groups of serially received input data in sync with the first to fourth frequency divider gating signals. The first to fourth frequency divider gating signals are generated by dividing the input gating signals by frequency. Write the alignment circuit, which: Synchronize the first internal strobe signal to the third internal strobe signal to align the first latched data to the fourth latched data; and Synchronized with the latch clock, the first write data and the second write data are generated from the latched first latch data to the fourth latch data; and An internal data generation circuit generates the internal data from the first written data and the second written data in synchronization with a data pulse signal, the data pulse signal being generated by delaying the latch clock.

16. The semiconductor device according to claim 15, wherein, The latched data generation circuit includes: A pre-latched data generation circuit generates first to fourth pre-latched data by latching a first group and a second group of the input data synchronously with the first to the fourth frequency divider strobe signals; and The latched data output circuit has the following characteristics: Synchronized with the second frequency divider strobe signal, the first latched data and the second latched data are generated from the first pre-latched data and the second pre-latched data; and synchronized with the fourth frequency divider strobe signal, the third latched data and the fourth latched data are generated from the third pre-latched data and the fourth pre-latched data.

17. The semiconductor device according to claim 15, wherein, The write alignment circuit includes: Alignment data generation circuit, which: Synchronize with the first internal strobe signal to receive the first latched data to the fourth latched data; Synchronizing the first latched data to the fourth latched data with the second internal strobe signal and the third internal strobe signal; and Output aligned first to fourth latched data as first aligned data and second aligned data; and Write to the data generation circuit, which: After the first operation mode begins, the first write data and the second write data are generated from the first alignment data and the second alignment data in synchronization with the latch clock; and After the second operating mode begins, the first write data and the second write data are generated from the first alignment data in sync with the latch clock.

18. The semiconductor device according to claim 17, wherein, The alignment data generation circuit includes: A first alignment data generation circuit, synchronized with the first internal strobe signal to the third internal strobe signal, generates bits of the first alignment data and the second alignment data from the first latched data and the second latched data; and The second alignment data generation circuit generates bits of the first alignment data and the second alignment data from the third latched data and the fourth latched data in sync with the first internal strobe signal to the third internal strobe signal.

19. The semiconductor device according to claim 18, wherein, The first alignment data generation circuit includes: The first latch, which is: Synchronized with the first internal strobe signal to receive the first latched data and the second latched data; and Generate the first pre-aligned data and the second pre-aligned data; The second latch generates bits of the first aligned data by latching the first pre-aligned data and the second pre-aligned data in sync with the second internal strobe signal. A third latch generates bits of the second aligned data by latching the first pre-aligned data and the second pre-aligned data in sync with the third internal strobe signal; A fourth latch generates bits of the first aligned data by latching the first latched data and the second latched data in synchronization with the second internal strobe signal; and The fifth latch generates the bits of the second aligned data by latching the first latched data and the second latched data in sync with the third internal strobe signal.

20. The semiconductor device according to claim 18, wherein, The second alignment data generation circuit includes: The sixth latch, which is: The third latched data and the fourth latched data are received synchronously with the first internal strobe signal; and Generate the third and fourth pre-aligned data; The seventh latch generates bits of the first aligned data by latching the third and fourth pre-aligned data in sync with the second internal strobe signal; The eighth latch generates bits of the second aligned data by latching the third pre-aligned data and the fourth pre-aligned data in sync with the third internal strobe signal; A ninth latch generates bits of the first aligned data by latching the third and fourth latched data in synchronization with the second internal strobe signal; and The tenth latch generates the bits of the second aligned data by latching the third latched data and the fourth latched data in sync with the third internal strobe signal.

21. The semiconductor device according to claim 17, wherein, The write data generation circuit includes: The first write data generation circuit, which: After the first operation mode begins, the bits of the first write data and the second write data are generated from the bits of the first aligned data and the second aligned data in synchronization with the latch clock; and After the second operation mode begins, the bits of the first write data and the second write data are generated from the bits of the first aligned data in synchronization with the latch clock; and The second write data generation circuit, which: After the first operation mode begins, the bits of the first write data and the second write data are generated from the bits of the first aligned data and the second aligned data in synchronization with the latch clock; and After the second operation mode begins, the bits of the first write data and the second write data are generated from the bits of the first aligned data in sync with the latch clock.

22. The semiconductor device according to claim 21, wherein, The first write data generation circuit includes: The eleventh latch generates the bits of the first written data and the bits of the first pre-written data by latching the bits of the first aligned data in sync with the latch clock: A first selection pass circuit generates the bit of the second write data from either the bit of the first pre-written data or the bit of the second aligned data by a burst enable signal; A twelfth latch generates the bits of the first write data and the bits of the first pre-write data by latching the bits of the first aligned data in synchronization with the latch clock; and The second selection transmission circuit generates the bit of the second write data from either the bit of the first pre-written data or the bit of the second aligned data via the burst enable signal.

23. The semiconductor device according to claim 21, wherein, The second write data generation circuit includes: The thirteenth latch generates the first write data bit and the second pre-write data bit by latching the first aligned data bit in sync with the latch clock. The third selection pass circuit generates the bit of the second write data from either the bit of the second pre-write data or the bit of the second alignment data by means of a burst enable signal; The fourteenth latch generates the bits of the first write data and the bits of the second pre-write data by latching the bits of the first aligned data in synchronization with the latch clock; and The fourth selection transmission circuit generates the bit of the second write data from either the bit of the second pre-write data or the bit of the second alignment data via the burst enable signal.

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