Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. The method of fabricating the semiconductor device includes forming a III-V compound barrier layer on a III-V compound semiconductor layer, forming a silicon-rich tensile stress layer on the III-V compound barrier layer, and performing an anneal fabrication process after forming the silicon-rich tensile stress layer. A portion of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer through the anneal fabrication process to form the silicon-doped III-V compound barrier layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device comprising a III-V compound semiconductor layer and a method for manufacturing the same. Background Technology

[0002] III-V compound semiconductors, due to their semiconductor properties, can be used to form many types of integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). In HEMTs, two semiconductor materials with different band gaps are combined at a junction to form a heterojunction, providing a channel for charge carriers. In recent years, gallium nitride (GaN) series materials have become suitable for high-power and high-frequency products due to their wide band gap and high saturation velocity. GaN series HEMTs generate a two-dimensional electron gas (2DEG) through the piezoelectric effect of the material itself, which has high electron velocity and density, thus increasing switching speed. However, how to further improve the electrical performance of transistors formed from III-V compound materials through design changes in materials, structures, and / or fabrication methods remains a research direction for researchers in related fields. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method thereof, which utilizes a silicon-rich tensile stress layer to form a silicon-doped III-V compound barrier layer, thereby reducing the impedance of the channel region of the semiconductor device and improving the relevant electrical performance of the semiconductor device.

[0004] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: forming a III-V compound barrier layer on a III-V compound semiconductor layer; forming a silicon-rich tensile stress layer on the III-V compound barrier layer; and performing an annealing process after the silicon-rich tensile stress layer is formed. A portion of the silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer through the annealing process to form a silicon-doped III-V compound barrier layer.

[0005] An embodiment of the present invention provides a semiconductor device including a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0007] Figures 2 to 8 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein...

[0008] Figure 3 for Figure 2 A diagram illustrating the subsequent situation;

[0009] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0010] Figure 5 for Figure 4 A diagram illustrating the subsequent situation;

[0011] Figure 6 for Figure 5 A diagram illustrating the subsequent situation;

[0012] Figure 7 for Figure 6 A diagram illustrating the subsequent situation;

[0013] Figure 8 for Figure 7 A diagram illustrating the subsequent situation.

[0014] Explanation of main component symbols

[0015] 2DEG Two-dimensional electronic gas

[0016] 10 base

[0017] 10B Bottom Surface

[0018] 10T upper surface

[0019] 12 III-V compound semiconductor layers

[0020] 14 III-V compound barrier layer

[0021] 14T silicon-doped III-V compound barrier layer

[0022] 20 Passivation Structure

[0023] 22 Silicon-rich tensile stress layer

[0024] 24 Passivation layer

[0025] 24C passivation layer

[0026] 26. Transparent UV protective layer

[0027] 30 Source / Drain Materials

[0028] 30D drain structure

[0029] 30S source structure

[0030] 40 Gate Structure

[0031] 91 Annealing process

[0032] 92 Annealing process

[0033] 93 Ultraviolet Light Treatment

[0034] 101 Semiconductor Device

[0035] D1 Vertical direction

[0036] D2 Horizontal direction

[0037] RC dent

[0038] TK1 Thickness

[0039] TK2 Thickness Detailed Implementation

[0040] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0041] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0042] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0043] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term to include etching.

[0044] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0045] Please see Figure 1 . Figure 1 The illustration shows a schematic diagram of a semiconductor device 101 according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 101 includes a III-V compound semiconductor layer 12, a silicon-doped III-V compound barrier layer 14T, and a silicon-rich tensile stress layer 22. The silicon-doped III-V compound barrier layer 14T is disposed on the III-V compound semiconductor layer 12, and the silicon-rich tensile stress layer 22 is disposed on the silicon-doped III-V compound barrier layer 14T. The silicon-rich tensile stress layer 22 and the silicon-doped III-V compound barrier layer 14T can be used to increase the tensile stress applied to the channel region in the semiconductor device 101, thereby reducing the impedance of the channel region of the semiconductor device and improving the relevant electrical performance of the semiconductor device.

[0046] For example, in some embodiments, a two-dimensional electron gas (2DEG) can be formed in the III-V compound semiconductor layer 12 near the interface between the III-V compound semiconductor layer 12 and the silicon-doped III-V compound barrier layer 14T. By increasing the tensile stress applied to the channel region, the density of the 2DEG can be increased, thereby reducing the resistance of the region containing the 2DEG and consequently reducing the on-resistance (R) of the semiconductor device 101. on This achieves energy saving. Furthermore, in the accompanying drawings, the positions of two-dimensional electron gases (2DEGs) are indicated by dashed lines, and the width of these dashed lines can represent the concentration of the 2DEGs. For example, a relatively thin dashed line represents a relatively low concentration of 2DEGs, while a relatively thick dashed line represents a relatively high concentration of 2DEGs, but this is not a limitation.

[0047] Further, in some embodiments, the semiconductor device 101 may further include a substrate 10, and the III-V compound semiconductor layer 12 may be disposed on the upper surface 10T of the substrate 10 in a vertical direction D1. The substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a sapphire substrate, or a substrate formed of other suitable materials. In some embodiments, before forming the III-V compound semiconductor layer 12, a buffer layer (not shown) may be formed on the substrate 10, and the buffer layer may include, for example, gallium nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), or other suitable buffer materials, but is not limited thereto. In other words, the buffer layer may be located between the substrate 10 and the III-V compound semiconductor layer 12 in the vertical direction D1.

[0048] In some embodiments, the III-V compound semiconductor layer 12 may include gallium nitride, indium gallium nitride (InGaN), or other suitable III-V compound semiconductor materials, while the silicon-doped III-V compound barrier layer 14T may include silicon-doped aluminum gallium nitride, silicon-doped aluminum indium nitride, silicon-doped aluminum gallium indium nitride, silicon-doped aluminum nitride (AlN), or other silicon-doped III-V compound materials. The silicon-rich tensile stress layer 22 may include silicon nitride, silicon carbide, or other silicon-containing materials with the desired tensile stress characteristics. In some embodiments, the silicon content in the silicon-rich tensile stress layer 22 may be substantially positively correlated with the tensile stress, and the silicon-rich tensile stress layer 22 may be considered as a silicon-containing tensile stress layer with a relatively high silicon content, but is not limited thereto. In some embodiments, the desired tensile stress characteristics can be achieved by adjusting the fabrication process conditions used to form the silicon-rich tensile stress layer 22. For example, the fabrication process power, pressure, temperature, gas flow rate, and gas ratio in the chemical vapor deposition process can be adjusted, but this is not a limitation. In some embodiments, the tensile stress of the silicon-rich tensile stress layer 22 can be greater than or equal to 500 Newtons per square millimeter (N / mm²). 2 This achieves the desired effect, but is not limited thereto. In some embodiments, the tensile stress of the silicon-rich tensile stress layer 22 may be between 200 N / mm² and 600 N / mm² to avoid the negative effects of excessive tensile stress.

[0049] In some embodiments, the vertical direction D1 described above can be considered as the thickness direction of the substrate 10. The substrate 10 may have an upper surface 10T and a bottom surface 10B opposite each other in the vertical direction D1, and the aforementioned III-V compound semiconductor layer 12, silicon-doped III-V compound barrier layer 14T, and silicon-rich tensile stress layer 22 may be formed on one side of the upper surface 10T. Horizontal directions that are substantially orthogonal to the vertical direction D1 (e.g., horizontal direction D2 and other directions orthogonal to the vertical direction D1) may be substantially parallel to the upper surface 10T and / or the bottom surface 10B of the substrate 10, but are not limited thereto. In this document, the distance in the vertical direction D1 between a relatively high position and / or between a component and the bottom surface 10B of the substrate 10 may be greater than the distance in the vertical direction D1 between a relatively low position and / or between a component and the bottom surface 10B of the substrate 10. The lower part or bottom of each component may be closer to the bottom surface 10B of the substrate 10 in the vertical direction D1 than the upper part or top of the component. Another component above a component may be considered to be relatively far from the bottom surface 10B of the substrate 10 in the vertical direction D1, while another component below a component may be considered to be relatively close to the bottom surface 10B of the substrate 10 in the vertical direction D1.

[0050] In some embodiments, the semiconductor device 101 may further include a passivation layer 24 and a UV-transparent protective layer 26. The passivation layer 24 is disposed on the silicon-rich tensile stress layer 22, and the UV-transparent protective layer 26 is disposed on the passivation layer 24. The passivation layer 24 may include silicon oxide, aluminum oxide, or other suitable insulating materials, while the UV-transparent protective layer 26 may include silicon nitride material or other insulating materials that allow UV light to pass through. In some embodiments, the tensile stress of the silicon-rich tensile stress layer 22 may be higher than the tensile stress of the passivation layer 24, and the passivation layer 24 may be relatively thick to adjust the tensile stress of the passivation layer 24 in conjunction with relevant fabrication processes. Therefore, the thickness TK2 of the passivation layer 24 may be greater than the thickness TK1 of the silicon-rich tensile stress layer 22, and the passivation layer 24 may be considered as an embedded stress regulator, but is not limited thereto.

[0051] In some embodiments, the ultraviolet transparent protective layer 26 may also have a relatively low water vapor and / or water oxygen permeability to provide protection for the passivation layer 24 or other material layers and reduce the impact of the external environment. The tensile stress of the passivation layer 24 may be higher than that of the ultraviolet transparent protective layer 26, but this is not a limitation. In some embodiments, the silicon-rich tensile stress layer 22, the passivation layer 24, and the ultraviolet transparent protective layer 26 may be considered together as a passivation structure 20, and the projected patterns and / or projected areas of the silicon-rich tensile stress layer 22, the passivation layer 24, and the ultraviolet transparent protective layer 26 in the vertical direction D1 may be substantially equal to each other, but this is not a limitation. In other words, the semiconductor device 101 may include a passivation structure 20, and the passivation structure 20 may consist of three different material layers to increase and / or adjust the tensile stress applied to the channel region in the semiconductor device 101.

[0052] In some embodiments, the semiconductor device 101 may further include a source structure 30S, a drain structure 30D, and a gate structure 40. The source structure 30S and the drain structure 30D may respectively penetrate the ultraviolet light transparent protective layer 26, the passivation layer 24, and the silicon-rich tensile stress layer 22 in the vertical direction D1. In some embodiments, the source structure 30S and the drain structure 30D may also respectively penetrate the silicon-doped III-V compound barrier layer 14T in the vertical direction D1 to directly contact the III-V compound semiconductor layer 12, but this is not a limitation. In some embodiments, the source structure 30S and the drain structure 30D may not penetrate the silicon-doped III-V compound barrier layer 14T. Therefore, a portion of the silicon-doped III-V compound barrier layer 14T may be located between the source structure 30S and the III-V compound semiconductor layer 12 in the vertical direction D1, while another portion of the silicon-doped III-V compound barrier layer 14T may be located between the drain structure 30D and the III-V compound semiconductor layer 12 in the vertical direction D1, but this is not a limitation.

[0053] In some embodiments, the passivation layer 24 may be surrounded by a silicon-rich tensile stress layer 22, an ultraviolet light transparent protective layer 26, a source structure 30S, and a drain structure 30D in both the vertical direction D1 and the horizontal direction D2. The gate structure 40 may be located between the source structure 30S and the drain structure 30D in the horizontal direction D2, and the gate structure 40 may penetrate the ultraviolet light transparent protective layer 26, the passivation layer 24, and the silicon-rich tensile stress layer 22 in the vertical direction D1, but is not limited thereto. In some embodiments, the gate structure 40 may be partially disposed in the silicon-doped III-V compound barrier layer 14T without penetrating the silicon-doped III-V compound barrier layer 14T. In some embodiments, the gate structure 40 may contact the upper surface of the silicon-doped III-V compound barrier layer 14T without being partially disposed in the silicon-doped III-V compound barrier layer 14T.

[0054] In some embodiments, the gate structure 40, source structure 30S, and drain structure 30D may each comprise a metallic conductive material or other suitable conductive material. The aforementioned metallic conductive materials may include gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), compounds, composite layers, or alloys of the aforementioned materials, but are not limited thereto. In some embodiments, the gate structure 40 may include a gate electrode (not shown) formed of the aforementioned conductive material and a gate dielectric layer (not shown) located beneath this gate electrode. The material of the gate dielectric layer may include aluminum nitride, silicon nitride (e.g., Si3N4), silicon oxide (e.g., SiO2), aluminum oxide (e.g., Al2O3), hafnium oxide (e.g., HfO2), lanthanum oxide (e.g., La2O3), lutetium oxide (e.g., Lu2O3), lanthanum-lutetium oxide (LaLuO3), or other suitable dielectric materials. In some embodiments, the semiconductor device 101 may be considered as a transistor structure, such as a high electron mobility transistor (HEMT), but is not limited thereto.

[0055] Please see Figures 1 to 8 . Figures 2 to 8 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figure 3 It is illustrated Figure 2 A diagram illustrating the subsequent situation. Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustrated Figure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 A diagram illustrating the subsequent situation. Figure 7 It is illustrated Figure 6 The following is a diagram illustrating the situation, and Figure 8 It is illustrated Figure 7 A schematic diagram of the subsequent situation. In some embodiments, Figure 1 It can be regarded as a drawing Figure 8 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 2 and Figure 3As shown, the fabrication method of this embodiment may include the following steps: A III-V compound barrier layer 14 is formed on a III-V compound semiconductor layer 12, and a silicon-rich tensile stress layer 22 is formed on the III-V compound barrier layer 14. After the silicon-rich tensile stress layer 22 is formed, an annealing process 91 is performed, and a portion of the silicon in the silicon-rich tensile stress layer 22 diffuses into the III-V compound barrier layer 14 through the annealing process 91 to form a silicon-doped III-V compound barrier layer 14T. In some embodiments, the III-V compound barrier layer 14 may include aluminum gallium nitride, aluminum indium nitride, aluminum gallium indium nitride, aluminum nitride, or other suitable III-V compound materials. In some embodiments, the tensile stress of the silicon-doped III-V compound barrier layer 14T may be higher than that of the III-V compound barrier layer 14 (i.e., the state before annealing process 91). This can increase the tensile stress applied to the channel region in the semiconductor device through the silicon-rich tensile stress layer 22 and the silicon-doped III-V compound barrier layer 14T, and can increase the density of the two-dimensional electron gas 2DEG, but is not limited thereto. In some embodiments, the annealing process 91 may include rapid thermal processing (RTP) or other suitable thermal processing methods, and the fabrication temperature of the annealing process 91 may be higher than 800 degrees Celsius, but is not limited thereto.

[0056] To further explain, the manufacturing method of this embodiment may include, but is not limited to, the following steps. For example... Figure 3 and Figure 4 As shown, after annealing process 91, a passivation layer 24 can be formed on the silicon-rich tensile stress layer 22, and an ultraviolet-transparent protective layer 26 can be formed on the passivation layer 24. In some embodiments, the passivation layer 24 can also be used to increase the tensile stress applied to the channel region in the semiconductor device and to increase the density of the two-dimensional electron gas 2DEG, but is not limited thereto. Then, as Figure 4 and Figure 5 As shown, a recessed RC can be formed in the regions corresponding to the source and drain structures, and the recessed RC can penetrate the ultraviolet-transparent protective layer 26, the passivation layer 24, and the silicon-rich tensile stress layer 22 in the vertical direction D1. In some embodiments, the recessed RC can also penetrate the silicon-doped III-V compound barrier layer 14T to expose part of the III-V compound semiconductor layer 12, but this is not limited to this. Then, as Figure 6 As shown, a source / drain material 30 can be formed, which may be partially formed in the recess RC and partially formed on the ultraviolet-transparent protective layer 26. In some embodiments, the source / drain material 30 may include a structure composed of multiple layers of material stacked together, such as a silicon layer and one or more metal layers formed on the silicon layer, but is not limited thereto.

[0057] like Figure 6 and Figure 7 As shown, the source / drain material 30 can be patterned to form source structure 30S and drain structure 30D. In some embodiments, an annealing process 92 can be performed after the formation of the source structure 30S and drain structure 30D to react the silicon layer and metal layer in the source / drain material to form a metal silicide layer, thereby enabling the source structure 30S and drain structure 30D to form an ohmic contact with the silicon-doped III-V compound barrier layer 14T and / or the III-V compound semiconductor layer 12, but this is not a limitation. The annealing process 92 may include rapid thermal processing or other suitable thermal processing methods.

[0058] like Figure 7 and Figure 8 As shown, after the annealing process 92 (that is, after the formation of the UV-transparent protective layer 26, the source structure 30S, and the drain structure 30D), a UV light treatment 93 can be performed to allow UV light to pass through the UV-transparent protective layer 26 and cure the passivation layer 24. In other words, the source structure 30S and the drain structure 30D can be formed after the formation of the UV-transparent protective layer 26 and before the UV light treatment 93. In some embodiments, the material in the passivation layer 24 can be reorganized by UV irradiation, thereby increasing the tensile stress of the passivation layer 24, which can further increase the tensile stress applied to the channel region in the semiconductor device and further increase the density of the two-dimensional electron gas 2DEG, but is not limited thereto. In other words, the tensile stress of the passivation layer 24 can be increased by ultraviolet light treatment 93, and the passivation layer 24 can be transformed into a treated passivation layer 24C by ultraviolet light treatment 93. The tensile stress of the treated passivation layer 24C can be higher than that of the passivation layer 24 before ultraviolet light treatment 93. In some embodiments, the tensile stress of the treated passivation layer 24C can be controlled by adjusting the fabrication process conditions of ultraviolet light treatment 93 (e.g., ultraviolet light irradiation time and / or irradiation intensity, etc.). Therefore, the passivation layer 24 can be regarded as an embedded stress regulator, but it is not limited thereto. Figure 8 and Figure 1 As shown, after ultraviolet light treatment 93, the above-mentioned gate structure 40 can be formed, thereby forming a semiconductor device 101.

[0059] In summary, in the semiconductor device and its fabrication method of the present invention, a silicon-doped III-V compound barrier layer can be formed by using a silicon-rich tensile stress layer in conjunction with an annealing process, thereby increasing the tensile stress applied to the channel region in the semiconductor device and increasing the density of the two-dimensional electron gas, thereby reducing the on-resistance of the semiconductor device and improving the related electrical performance.

[0060] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A III-V compound barrier layer is formed on a III-V compound semiconductor layer; A silicon-rich tensile stress layer is formed on the III-V compound barrier layer; as well as After the silicon-rich tensile stress layer is formed, an annealing process is performed, in which a portion of the silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer through the annealing process to form a silicon-doped III-V compound barrier layer.

2. The method for fabricating a semiconductor device as claimed in claim 1, wherein the silicon-rich tensile stress layer comprises silicon nitride or silicon carbide.

3. The method for manufacturing a semiconductor device as described in claim 1, further comprising: Following the annealing process, a passivation layer is formed on the silicon-rich tensile stress layer.

4. The method for fabricating a semiconductor device as claimed in claim 3, wherein the tensile stress of the silicon-rich tensile stress layer is higher than the tensile stress of the passivation layer.

5. The method for fabricating a semiconductor device as claimed in claim 3, wherein the thickness of the passivation layer is greater than the thickness of the silicon-rich tensile stress layer.

6. The method for manufacturing a semiconductor device as described in claim 3, further comprising: An ultraviolet-transparent protective layer is formed on the passivation layer.

7. The method for fabricating a semiconductor device as claimed in claim 6, wherein the tensile stress of the passivation layer is higher than the tensile stress of the ultraviolet-transparent protective layer.

8. The method for manufacturing a semiconductor device as described in claim 6, further comprising: After the ultraviolet transparent protective layer is formed, ultraviolet light treatment is performed, during which the tensile stress of the passivation layer increases.

9. The method for manufacturing a semiconductor device as claimed in claim 8, further comprising: A source structure and a drain structure are formed, wherein the source structure and the drain structure respectively penetrate the ultraviolet light transparent protective layer, the passivation layer and the silicon-rich tensile stress layer in the vertical direction.

10. The method of fabricating a semiconductor device as claimed in claim 9, wherein the source structure and the drain structure are formed after the formation of the ultraviolet light transparent protective layer and before the ultraviolet light treatment.

11. The method of manufacturing a semiconductor device as claimed in claim 8, further comprising: After the ultraviolet light treatment, a gate structure is formed, which penetrates the ultraviolet light transparent protective layer, the passivation layer, and the silicon-rich tensile stress layer.

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