Test structures and methods of forming the same

Abstract

A test structure and its formation method are disclosed. The test structure includes: a dielectric layer located on a substrate; a test interconnect structure located within the dielectric layer, comprising a metal layer and a first via interconnect structure connecting adjacent metal layers, the metal layer including a first test metal layer and a second test metal layer located above it, wherein the layer through which the current flows last between the first and second test metal layers is designated as the metal layer under test; a capping layer located between the top of the metal layer and the dielectric layer; and a floating circuit structure located within the dielectric layer, penetrating the capping layer at the top of the metal layer under test and connected to the top of the metal layer under test, wherein the bonding force between the floating circuit structure and the metal layer under test is greater than the bonding force between the capping layer and the metal layer under test. The stronger bonding force between the floating circuit structure and the metal layer under test reduces the probability of voids being generated at the top surface of the metal layer under test due to directional movement with an electric field, thereby improving electromigration reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a test structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, the electromigration (EM) reliability of metal interconnects is an important indicator for evaluating semiconductor interconnect manufacturing processes, one of the bottlenecks limiting process miniaturization technology, and a major factor affecting the reliability performance of semiconductor devices.

[0003] When the device is working, a certain current flows through the metal interconnect and generates an electric field. Electrons move in the direction of the electric field and exchange momentum with metal atoms, forming the migration of metal ions. The migration of metal ions can easily create voids in local areas of the metal interconnect. When the voids reach a certain extent, the resistance of the metal interconnect increases significantly, which leads to a decrease in electromigration reliability or failure.

[0004] In order to determine the reliability of the formed metal interconnects, electromigration testing has become an important test item for evaluating the reliability of semiconductor devices, and thus verifying the performance of semiconductor devices.

[0005] However, the electromigration reliability of current electromigration test structures needs to be improved. Summary of the Invention

[0006] The problem addressed by the embodiments of the present invention is to provide a test structure and a method for forming the same, thereby improving the electromigration reliability of the test structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a test structure, comprising: a substrate; a dielectric layer located on the substrate; a test interconnect structure located in the dielectric layer, the test interconnect structure including a metal layer and a first via interconnect structure connecting adjacent metal layers, the metal layer including a first test metal layer and a second test metal layer that are vertically adjacent, the second test metal layer being located above the first test metal layer, and the layer through which the current flows last between the first and second test metal layers serving as the metal layer under test; a capping layer located between the top of the metal layer and the dielectric layer; and a floating circuit structure located in the dielectric layer at the top of the metal layer under test, the floating circuit structure penetrating the capping layer at the top of the metal layer under test and being connected to the top of the metal layer under test, and the bonding force between the floating circuit structure and the metal layer under test being greater than the bonding force between the capping layer and the metal layer under test.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a test structure, comprising: providing a substrate, on which a first sub-dielectric layer and a first test metal layer located within the first sub-dielectric layer are formed; performing an interconnect stacking process over the first sub-dielectric layer and the first test metal layer, the interconnect stacking process comprising: forming a capping layer over the first sub-dielectric layer and the first test metal layer; forming a second sub-dielectric layer on the capping layer; forming a metal interconnect structure in the second sub-dielectric layer, the metal interconnect structure further penetrating the bottom capping layer; wherein the interconnect stacking process includes a first interconnect stacking process performed sequentially after the formation of the first sub-dielectric layer and the first test metal layer, the first interconnect stacking process forming... The metal interconnect structure includes a second test metal layer and a first via interconnect structure located between the second test metal layer and the first test metal layer. The first test metal layer, the second test metal layer, and the first via interconnect structure located between them are used to form the test interconnect structure. According to the current flow direction, the layer through which the current flows last between the first test metal layer and the second test metal layer is used as the metal layer under test. A floating circuit structure is formed in the second sub-dielectric layer on top of the metal layer under test. The floating circuit structure penetrates the capping layer on top of the metal layer under test and is connected to the top of the metal layer under test. The bonding force between the floating circuit structure and the metal layer under test is greater than the bonding force between the capping layer and the metal layer under test.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the test structure provided by this invention, a floating circuit structure is formed in the dielectric layer on top of the metal layer under test. The floating circuit structure penetrates the capping layer on top of the metal layer under test and is connected to the top of the metal layer under test. The bonding force between the floating circuit structure and the metal layer under test is greater than the bonding force between the capping layer and the metal layer under test. By adding a floating circuit structure to the test structure, and having a stronger bonding force between the floating circuit structure and the metal layer under test, it is beneficial to suppress the diffusion ability of the material of the metal layer under test at the interface between the floating circuit structure and the metal layer under test. Correspondingly, the effective length at the interface between the metal layer under test and the capping layer is shortened, thereby reducing the probability of metal voids being generated at the top surface of the metal layer under test due to directional movement with the electric field. This improves the electromigration reliability of the test structure. At the same time, the floating circuit structure does not change the original circuit current direction and function, thereby improving the electromigration reliability of the test structure while reducing the impact on the layout design of the test structure.

[0011] In the method for forming a test structure provided in this embodiment of the invention, an interconnect stacking process is performed above a first sub-dielectric layer and a first test metal layer to form a second test metal layer and a first via interconnect structure located between the second test metal layer and the first test metal layer. The first test metal layer, the second test metal layer, and the first via interconnect structure located between them are used to constitute a test interconnect structure. According to the current flow direction, the layer through which the current flows last between the first and second test metal layers is used as the metal layer to be tested. A floating circuit structure is formed in the second sub-dielectric layer on top of the metal layer to be tested. The floating circuit structure penetrates the cap layer on top of the metal layer to be tested and is connected to the top of the metal layer to be tested. The bonding force between the floating circuit structure and the metal layer to be tested is greater than that between the cap layer and the cap layer. The bonding force between the layer and the metal layer under test; among them, the bonding force between the levitation circuit structure and the metal layer under test is stronger, which helps to suppress the diffusion ability of the material of the metal layer under test at the interface between the levitation circuit structure and the metal layer under test, and correspondingly helps to reduce the migration rate of metal atoms of the metal layer under test along the interface between the levitation circuit structure and the metal layer under test, so as to shorten the effective length of the metal layer under test at the interface between the metal layer under test and the capping layer, thereby reducing the probability of voids being generated at the top surface of the metal layer under test due to directional movement with the electric field, and thus improving the electromigration reliability of the test structure. At the same time, the levitation circuit structure does not change the original circuit current direction and function, thereby improving the electromigration reliability of the test structure while reducing the impact on the layout design of the test structure. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a test structure used to test the reliability of electromigration in downlink conditions;

[0013] Figure 2 This is a schematic diagram of a test structure used to test electromigration reliability in uplink scenarios;

[0014] Figure 3 This is a top view of an embodiment of the test structure of the present invention;

[0015] Figure 4 It is a sectional view along the secant line a1a2;

[0016] Figure 5 This is a cross-sectional view of another embodiment of the test structure of the present invention;

[0017] Figures 6 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the test structure of the present invention;

[0018] Figures 11 to 13 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the test structure of the present invention. Detailed Implementation

[0019] Currently, the electromigration reliability of existing electromigration test structures needs improvement. This paper analyzes the reasons why the electromigration reliability needs to be improved using one test structure as an example.

[0020] Figure 1 This is a schematic diagram of a test structure used to test downstream electromigration reliability. (Reference) Figure 1 The test structure includes: a substrate (not shown); a dielectric layer 10 located on the substrate; a test interconnect structure 20 located in the dielectric layer 10, the test interconnect structure 20 including a metal layer (not shown) and a through-hole interconnect structure 22 connecting adjacent metal layers in the longitudinal direction, the metal layer including a first test metal layer 21 and a second test metal layer 23 located above the first test metal layer 21; and a capping layer 30 located on top of the metal layer and between the dielectric layer 10.

[0021] Figure 1 The dashed arrows indicate the direction of current flow. Taking the test structure used to test the electromigration reliability under downlink conditions as an example, the two ends of the first test metal layer 21 are electrically connected to different second test metal layers 23. One of the second test metal layers 23 serves as the first application (Force) end, and the other second test metal layer 23 serves as the second application end. Current flows from the first application end through the first test metal layer 21 to the second application end. Figure 1 Only one of the second test metal layers 23 is shown in the diagram.

[0022] Research revealed that the interface between the metal layer and the capping layer 30 on top of it is the primary diffusion path for electromigration failure. Specifically, due to the weak bonding force between the first test metal layer 21 and the capping layer 30, the material of the first test metal layer 21 easily diffuses at this interface, leading to voids and ultimately electromigration failure. For example, as... Figure 1 As shown, when testing the electromigration reliability in the downlink scenario, location A is a location where voids are prone to occur.

[0023] Accordingly, refer to Figure 2 , Figure 2 This is a schematic diagram of a test structure used to test upstream electromigration reliability. Figure 2 The dashed arrows in the diagram indicate the direction of current flow. Therefore, when testing the electromigration reliability in the upward scenario, voids can easily form at the interface between the second test metal layer 23 and the capping layer 30 on top of it, leading to electromigration failure. For example, Figure 2 Position B in the middle is a location where voids are likely to occur.

[0024] To address the technical problem, embodiments of the present invention provide a test structure, comprising: a substrate; a dielectric layer located on the substrate; a test interconnect structure located in the dielectric layer, the test interconnect structure including a metal layer and a first via interconnect structure connecting adjacent metal layers, the metal layer including a first test metal layer and a second test metal layer adjacent in the longitudinal direction, the second test metal layer being located above the first test metal layer, and the layer through which the current flows last in the first and second test metal layers serving as the metal layer under test; a capping layer located between the top of the metal layer and the dielectric layer; and a floating circuit structure located in the dielectric layer at the top of the metal layer under test, the floating circuit structure penetrating the capping layer at the top of the metal layer under test and being connected to the top of the metal layer under test, wherein the bonding force between the floating circuit structure and the metal layer under test is greater than the bonding force between the capping layer and the metal layer under test.

[0025] This invention employs a suspended circuit structure with a stronger bond between it and the metal layer under test (MTBT). This effectively suppresses the diffusion of the TMBT material at the interface between the suspended circuit structure and the TMBT, thereby reducing the migration rate of metal atoms along the interface. This shortens the effective length of the TMBT at the interface with the capping layer, reducing the probability of voids forming on the top surface of the TMBT due to directional movement with the electric field. Consequently, this improves the electromigration reliability of the test structure. Furthermore, the suspended circuit structure does not alter the original circuit current flow and function, thus minimizing the impact on the layout design of the test structure while improving its electromigration reliability.

[0026] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figure 3 This is a top view of an embodiment of the test structure of the present invention. Figure 4 It is a sectional view along the secant line a1a2.

[0028] The test structure includes: a substrate (not shown); a dielectric layer 100 located on the substrate; and a test interconnect structure 110 located within the dielectric layer 100. The test interconnect structure 110 includes a metal layer (not shown) and a first via interconnect structure 113 connecting adjacent metal layers. The metal layers include a first test metal layer 111 and a second test metal layer 112 that are longitudinally adjacent. The second test metal layer 112 is located above the first test metal layer 111. According to the current flow direction, the first test metal layer 111 and the second test metal layer... The layer through which the current flows in 112 is the metal layer under test 115; the capping layer 120 is located between the top of the metal layer and the dielectric layer 100; the floating circuit structure 200 is located in the dielectric layer 100 on top of the metal layer under test 115. The floating circuit structure 200 penetrates the capping layer 120 on top of the metal layer under test 115 and is connected to the top of the metal layer under test 115. The bonding force between the floating circuit structure 200 and the metal layer under test 115 is greater than the bonding force between the capping layer 120 and the metal layer under test 115.

[0029] The substrate serves as a platform for forming test structures. Depending on the specific process, the substrate includes the substrate itself and the functional structures formed on it. For example, semiconductor devices such as MOS field-effect transistors can be formed within the substrate, as can resistive structures.

[0030] It should be noted that a front-layer interconnect structure can also be formed within the substrate. For example, the front-layer interconnect structure can be a contact hole plug (CT), which can be a first metal interconnect line (i.e., M1 layer) formed on the contact hole plug, or a second metal interconnect line (i.e., M2 layer).

[0031] The dielectric layer 100 is used to provide electrical isolation between the test interconnect structures 110. The material of the dielectric layer 100 includes one or more of silicon hydroxide (SiOCH), silicon oxycarbonate (SiOC), silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), aluminum nitride (AlN), aluminum oxide (Al2O3), hafnium oxide (HfO2), and hafnium nitride (HfN).

[0032] In this embodiment, the dielectric layer 100 includes multiple stacked sub-dielectric layers (not shown). Specifically, the first test metal layer 111 is located in one of the sub-dielectric layers, and the second test metal layer 112 and the first via interconnect structure 113 are located in another sub-dielectric layer.

[0033] During electromigration testing, a test current is applied to the application terminal of the test interconnect structure 110, thereby establishing an electrical path between the first test metal layer 111 and the second test metal layer 112.

[0034] like Figure 3 As shown, in this embodiment, the test structure is used to test the electromigration reliability under downlink conditions. Therefore, the first test metal layer 111 is used as the metal layer under test 115.

[0035] Specifically, the two ends of the first test metal layer 111 are electrically connected to different second test metal layers 112. The second test metal layer 112 located at one end of the first test metal layer 111 serves as a first application terminal, and the second test metal layer 112 located at the other end of the first test metal layer 111 serves as a second application terminal. After a test current is applied to the application terminal, the current flows from one of the second test metal layers 112 to the first test metal layer 111. Figure 4 The dashed arrows in the diagram indicate the direction of current flow. Therefore, in this embodiment, the first test metal layer 111 is a metal layer through which the current flows. That is, the metal layer to be tested 115 is another metal layer connected to the metal layer corresponding to the application terminal.

[0036] In this embodiment, the first via interconnect structure 113 connects adjacent metal layers in the longitudinal direction, where longitudinal direction refers to the normal direction of the top surface of the substrate. The first test metal layer 111 and the second test metal layer 112 are electrically connected through the first via interconnect structure 113. Therefore, after a test current is applied at the application end, the current flows from the second test metal layer 112 corresponding to the first application end through the first via interconnect structure 113 to the first test metal layer 111. After the current flows through the first test metal layer 111, it flows again through the first via interconnect structure 113 to the second test metal layer 112 corresponding to the second application end.

[0037] It should be noted that the test structure also includes a first detection terminal 114 connected to the first application terminal and a second detection terminal 116 connected to the second application terminal. After applying a test current to the application terminal, the electromigration of the metal layer 115 under test is measured by detecting the resistance between the first detection terminal and the second detection terminal.

[0038] In this embodiment, the second test metal layer 112 and the first through-hole interconnect structure 113 located at its bottom constitute a dual damascene structure.

[0039] In this embodiment, both the metal layer and the first via interconnect structure 113 include: a conductive layer 131 and an adhesion barrier layer 132 covering the bottom and sidewalls of the conductive layer 131.

[0040] The conductive layer 131 is made of copper or aluminum. In this embodiment, the conductive layer 131 is made of copper to reduce the RC delay of the device and improve its electromigration resistance.

[0041] The adhesion barrier layer 132 serves to isolate the conductive layer 131 from the dielectric layer 100, blocking the conductive material atoms of the conductive layer 131 from diffusing into the dielectric layer 100. Furthermore, the adhesion barrier layer 132 also improves the adhesion of the conductive layer 131 to its surface. Therefore, the material of the adhesion barrier layer 132 includes one or more of titanium, titanium nitride, tantalum, and tantalum nitride. These materials have high density, effectively blocking diffusion, and exhibit good adhesion to metallic materials.

[0042] The capping layer 120 is used to reduce the probability of the underlying metal layer material diffusing into the upper dielectric layer 100.

[0043] In this embodiment, the capping layer 120 is a dielectric material, thereby serving an insulating function. Specifically, the material of the capping layer 120 includes one or more of silicon nitride and nitrogen-doped silicon carbide. Silicon nitride and nitrogen-doped silicon carbide also have high density, which helps the capping layer 120 to better suppress the diffusion of the underlying metal layer material into the upper dielectric layer 100.

[0044] Since surface migration is the dominant mechanism in electromigration reliability failure, and the floating circuit structure 200 has a stronger bond with the metal layer under test 115 compared to the capping layer 120, this helps to suppress the diffusion of the material of the metal layer under test 115 at the interface between the floating circuit structure 200 and the metal layer under test 115. Correspondingly, it helps to reduce the migration rate of metal atoms of the metal layer under test 115 along the interface between the floating circuit structure 200 and the metal layer under test 115. The effective length of the metal layer under test 115 at the interface between the metal layer under test 115 and the capping layer 120 is shortened accordingly, thereby reducing the probability of voids being generated at the top surface of the metal layer under test 115 due to directional movement with the electric field, and thus improving the electromigration reliability of the test structure.

[0045] According to the Blech length effect, for metal electromigration, under a fixed operating current density J, if the length L of the metal line through which the current flows is less than a certain length, the mean time to failure (MTTF) can be significantly increased. In other words, there exists a J*L threshold; when the product of the operating current density J and the metal strip length L exceeds this threshold to a certain extent, metal electromigration failure can occur significantly. Therefore, specifically in this embodiment, the addition of the floating circuit structure 200 is equivalent to replacing part of the capping layer 120 on top of the metal layer 115 under test. The effective length of the metal layer 115 at the interface between the metal layer 115 under test and the capping layer 120 is shortened, thereby reducing the length L of the metal strip and thus increasing the mean time to failure, i.e., improving the electromigration reliability of the test structure.

[0046] Furthermore, by adding a floating circuit structure 200 to the test structure, the floating circuit structure 200 does not form an additional shunt loop, thus not changing the original current flow and function of the circuit. This improves the electromigration reliability of the test structure while reducing the impact on the layout design of the test structure.

[0047] In this embodiment, the material of the levitation circuit structure 200 includes one or both of metals and metal compounds, and the levitation circuit structure 200 is configured with an open circuit. Since the material of the metal layer 115 under test includes metal, the bonding force between metals is higher than that between dielectric materials, and the bonding force between metals and metal compounds is also higher, thus facilitating a stronger bonding force between the levitation circuit structure 200 and the metal layer 115 under test. Furthermore, metals and metal compounds have high process compatibility with subsequent manufacturing processes.

[0048] Accordingly, in order to prevent the floating circuit structure 200 from forming an additional shunt loop, the floating circuit structure 200 is set to be open-circuited.

[0049] Specifically, the metal includes one or more of copper, aluminum, titanium, and tantalum, and the metal compound includes one or more of titanium nitride and tantalum nitride. In other embodiments, other materials that are compatible with back-end processes and have stronger bonding with the metal layer under test may also be selected.

[0050] In this embodiment, to reduce the probability of the suspended circuit structure 200 interacting with other metal layers, the suspended circuit structure 200 is staggered from the remaining metal layers. For example, when the material of the suspended circuit structure 200 includes one or both of metals and metal compounds, it is beneficial to significantly reduce the probability of the suspended circuit structure 200 short-circuiting with other metal layers.

[0051] Specifically, the floating circuit structure 200 is a second via interconnect structure, and the second via interconnect structure is made of the same material as the first via interconnect structure 113. Therefore, during the formation of the test structure, the second via interconnect structure (i.e., the floating circuit structure 200) and the first via interconnect structure 113 can be formed in the same step, thus eliminating the need for an additional photomask, thereby simplifying the process steps and reducing process costs. Moreover, using the second via interconnect structure as the floating circuit structure 200 improves the compatibility of the floating circuit structure 200 with subsequent processes.

[0052] As an example, the second via interconnect structure (i.e., the floating circuit structure 200) and the first via interconnect structure 113 have the same linewidth along the direction parallel to the top surface of the substrate 50.

[0053] In this embodiment, taking the test structure for testing the electromigration reliability under downlink conditions as an example, the first test metal layer 111 is the metal layer to be tested 115, and the floating circuit structure 200 is located in the dielectric layer 100 on the side of the second test metal layer 112, and the top of the floating circuit structure 200 is flush with the top of the second test metal layer 112.

[0054] When the floating circuit structure 200 contacts the metal layer 115 under test, it can shorten the effective length of the metal layer 115 under test at the interface between the metal layer 115 under test and the capping layer 120. Therefore, by making the top of the floating circuit structure 200 flush with the top of the second test metal layer 112, unnecessary cost waste can be avoided, and it is also beneficial to reduce the impact on the process carried out above the second test metal layer 112.

[0055] In this embodiment, there are multiple floating circuit structures 200 on the same metal layer 115 under test, and these multiple floating circuit structures 200 are separately disposed on the top of the metal layer 115 under test along the extension direction of the metal layer 115 under test. Because there are multiple floating circuit structures 200, the linewidth of a single floating circuit structure 200 along the direction parallel to the top surface of the substrate will not be too large, thereby improving compatibility with subsequent processes. At the same time, increasing the number of floating circuit structures 200 shortens the effective length of the metal layer 115 under test at the interface between the metal layer 115 under test and the capping layer 120, thereby reducing the overall probability of voids being generated at the top surface of the metal layer 115 under test due to directional movement with the electric field.

[0056] It should be noted that even if multiple floating circuit structures 200 are separately disposed on top of the metal layer 115 under test along the extension direction of the metal layer 115 under test, there is still a capping layer 120 in contact with the metal layer 115 under test between adjacent floating circuit structures 200. However, based on the existence of the Blech length effect, the migration rate of metal atoms of the metal layer 115 under test along the interface between the metal layer 115 under test and the capping layer 120 can still be effectively reduced.

[0057] Correspondingly, the smaller the spacing between adjacent levitated circuit structures 200, the more significant the effect on improving the electromigration reliability of the test structure. Therefore, in this embodiment, the spacing S between adjacent levitated circuit structures 200 along the extension direction of the metal layer 115 under test is less than or equal to 60 micrometers. As an example, the spacing S between adjacent levitated circuit structures 200 is less than or equal to 40 micrometers.

[0058] Similarly, the more floating circuit structures 200 there are, the shorter the effective length of the metal layer 115 under test at the interface between the metal layer 115 under test and the capping layer 120, and the more significant the effect of improving the electromigration reliability of the test structure. Therefore, the number of floating circuit structures 200 on the top of the same metal layer 115 under test is the maximum allowable number that meets the minimum spacing design rule.

[0059] Specifically, the number of floating circuit structures 200 on the top of the same metal layer 115 under test is determined by the length of the metal layer 115 under test and the spacing S between adjacent floating circuit structures 200.

[0060] In this embodiment, multiple floating circuit structures 200 on the same metal layer 115 under test are equally spaced on the top of the metal layer 115 under test. On the one hand, this helps to reduce the difficulty of the layout design of the floating circuit structures 200. On the other hand, the equal spacing makes the floating circuit structures 200 evenly distributed on the top of the metal layer 115 under test, which helps to make the failure probability of the area between each floating circuit structure 200 similar, thereby reducing the possibility that the failure probability of the area will increase due to the excessive spacing between some floating circuit structures 200.

[0061] It should be noted that, as an example, a capping layer 120 and a sub-dielectric layer covering the capping layer 120 can also be formed on the top of the floating circuit structure 200 and the top of the second test metal layer 112. The sub-dielectric layer above the top of the floating circuit structure 200 and the top of the second test metal layer 112 can be used to form the remaining metal interconnect structures in the subsequent interconnect structure.

[0062] Figure 5 This is a cross-sectional view of another embodiment of the test structure of the present invention. The similarities between this embodiment and the foregoing embodiments will not be repeated.

[0063] The difference between this embodiment and the previous embodiment is that the second test metal layer 312 is the metal layer to be tested 315, and the position of the floating circuit structure 400 in the dielectric layer (not shown) is different accordingly.

[0064] In this embodiment, the test interconnect structure 310 includes a first test metal layer 311, a second test metal layer 312, and a first via interconnect structure 313 connecting the first test metal layer 311 and the second test metal layer 312. Specifically, the second test metal layer 312 is buried in the dielectric layer, thereby providing space for the formation of the floating circuit structure.

[0065] In this embodiment, the test structure is used to test the electromigration reliability in the uplink situation. Therefore, the second test metal layer 312 is the metal layer 315 under test.

[0066] Specifically, the two ends of the second test metal layer 312 are electrically connected to different first test metal layers 311. The first test metal layer 311 located at one end of the second test metal layer 312 serves as a first application terminal, and the first test metal layer 311 located at the other end of the second test metal layer 312 serves as a second application terminal. After a test current is applied to the application terminal, the current flows from the first test metal layer 311 to the second test metal layer 312. Figure 5 (The dashed arrow in the figure indicates the direction of current flow). Therefore, in this embodiment, the second test metal layer 312 is a metal layer through which the current flows, and the second test metal layer 312 is correspondingly used as the metal layer to be tested 315.

[0067] In this embodiment, the first test metal layer 311 and the second test metal layer 312 are electrically connected through the first through-hole interconnection structure 313. Therefore, after a test current is applied at the application end, the current flows from the first test metal layer 311 corresponding to the first application end to the second test metal layer 312 through the first through-hole interconnection structure 313. After the current flows through the second test metal layer 312, it flows back to the first test metal layer 311 corresponding to the second application end through the first through-hole interconnection structure 313.

[0068] In this embodiment, the levitation circuit structure 400 is located in the dielectric layer (not shown) on top of the metal layer 315 under test. The levitation circuit structure 400 penetrates the capping layer 320 on top of the metal layer 315 under test and is connected to the top of the metal layer 315 under test. Based on the foregoing analysis, it is known that the electromigration reliability failure mechanism is dominated by surface migration, that is, the metal atoms of the metal layer 315 under test usually migrate along the interface between the metal layer 315 under test and the capping layer 320. Therefore, the levitation circuit structure 400 is located on top of the metal layer 315 under test and penetrates the capping layer 320 to replace part of the capping layer 320 on the top surface of the metal layer 315 under test.

[0069] For a detailed description of the test structure, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0070] Accordingly, the present invention also provides a method for forming a test structure. Figures 6 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the test structure of the present invention.

[0071] refer to Figure 6 A substrate (not shown) is provided, on which a first sub-dielectric layer 510 and a first test metal layer 550 located in the first sub-dielectric layer 510 are formed.

[0072] The substrate serves as a platform for forming test structures. Depending on the specific process, the substrate includes a substrate and functional structures formed on it. For example, semiconductor devices such as MOS field-effect transistors and resistive structures can be formed within the substrate. It should be noted that front-layer interconnect structures can also be formed within the substrate. For instance, the front-layer interconnect structure can be a contact hole plug, or it can be a first metal interconnect line (i.e., M1 layer) formed on the contact hole plug, or it can be a second metal interconnect line (i.e., M2 layer).

[0073] The first test metal layer 550 serves as part of the test interconnect structure. In this embodiment, taking the test structure for testing the electromigration reliability under downlink conditions as an example, the first test metal layer 550 serves as the metal layer under test 551 in the test interconnect structure.

[0074] The first sub-dielectric layer 510 provides a process basis for forming the first test metal layer 550 and also provides electrical isolation between the first test metal layers 550. The material of the first sub-dielectric layer 510 includes one or more of silicon hydroxide, silicon oxide, silicon oxide, silicon nitride, silicon oxynitride, titanium nitride, aluminum nitride, aluminum oxide, hafnium oxide, and hafnium nitride.

[0075] Specifically, the step of forming the first test metal layer 550 in the first sub-dielectric layer 510 includes: forming a first trench (not shown) in the first sub-dielectric layer 510; and forming the first test metal layer 550 in the first trench.

[0076] The first test metal layer 550 includes a conductive layer 540 and an adhesion barrier layer 530 covering the bottom and sidewalls of the conductive layer 540.

[0077] In this embodiment, the step of forming a first test metal layer 550 in a first trench includes: forming an adhesion barrier layer 530 at the bottom and sidewalls of the first trench; and filling a conductive layer 540 in the first trench where the adhesion barrier layer 530 is formed.

[0078] The conductive layer 540 is made of copper or aluminum. In this embodiment, the conductive layer 540 is made of copper to reduce the RC delay of the device and improve its electromigration resistance.

[0079] The adhesion barrier layer 530 is used to isolate the conductive layer 540 and the first sub-dielectric layer 510, blocking the conductive material atoms of the conductive layer 540 and preventing them from diffusing into the first sub-dielectric layer 510. Furthermore, the adhesion barrier layer 530 also improves the adhesion of the conductive layer 540 to its surface. Therefore, the material of the adhesion barrier layer 530 includes one or more of titanium, titanium nitride, tantalum, and tantalum nitride. These materials have high density, effectively blocking diffusion, and good adhesion to metallic materials.

[0080] As an example, an adhesion barrier layer 530 is formed using a physical vapor deposition (PVD) process, and a conductive layer 540 is formed using an electrochemical plating (ECP) process.

[0081] Specifically, in the step of forming the adhesion barrier layer 530 at the bottom and sidewall of the first trench, the adhesion barrier layer 530 also covers the top of the first sub-dielectric layer 510 outside the first trench, and the conductive layer 540 correspondingly covers the adhesion barrier layer 530 outside the first trench. Therefore, after filling the conductive layer 540 in the first trench where the adhesion barrier layer 530 is formed, the step of forming the first test metal layer 550 further includes: performing a planarization treatment (e.g., chemical mechanical polishing) on ​​the conductive layer 540 and the adhesion barrier layer 530 to remove the conductive layer 540 and the adhesion barrier layer 530 above the first sub-dielectric layer 510.

[0082] Reference Figures 7 to 10 An interconnect stacking process is performed above the first sub-dielectric layer 510 and the first test metal layer 550. The interconnect stacking process includes: forming a capping layer above the first sub-dielectric layer 510 and the first test metal layer 550; forming a second sub-dielectric layer on the capping layer; and forming a metal interconnect structure 560 in the second sub-dielectric layer, the metal interconnect structure 560 also penetrating the bottom capping layer. The interconnect stacking process includes a first interconnect stacking process performed sequentially after the formation of the first sub-dielectric layer 510 and the first test metal layer 550. The metal interconnect structure 560 formed by the first interconnect stacking process includes a second test metal layer 580 and a first via interconnect structure 590 located between the second test metal layer 580 and the first test metal layer 550. The first test metal layer 550, the second test metal layer 580, and the first via interconnect structure 590 located between them are used to form a test interconnect structure (not shown). According to the current flow direction, the layer through which the current flows in the first test metal layer 550 and the second test metal layer 580 is used as the metal layer under test 551.

[0083] The first test metal layer 550, the second test metal layer 580, and the first via interconnect structure 590 serve as a test interconnect structure for electromigration reliability testing. Specifically, during electromigration reliability testing, a test current is applied to the application end of the test interconnect structure, thereby establishing an electrical path between the first test metal layer 550 and the second test metal layer 580.

[0084] The steps of the first interconnect stacking process are described in detail below with reference to the accompanying drawings.

[0085] refer to Figure 7 A capping layer 610 is formed over the first sub-dielectric layer 510 and the first test metal layer 550.

[0086] The capping layer 610 is used to reduce the probability of the underlying metal layer material diffusing into the upper second sub-dielectric layer 570.

[0087] In this embodiment, the capping layer 610 is a dielectric material, thereby serving as an insulator. Specifically, the material of the capping layer 610 includes one or more of silicon nitride and nitrogen-doped silicon carbide. Silicon nitride and nitrogen-doped silicon carbide also have high density, which helps the capping layer 610 to better suppress the diffusion of the underlying metal layer material into the upper second sub-dielectric layer 570.

[0088] Continue to refer to Figure 7 A second sub-dielectric layer 570 is formed on the capping layer 610.

[0089] The second sub-dielectric layer 570 provides a process basis for the subsequent formation of the second test metal layer 580 and the first via interconnect structure 590, and also isolates the second test metal layer 580 and the first via interconnect structure 590. For a description of the material of the second sub-dielectric layer 570, please refer to the relevant description of the first sub-dielectric layer 510, which will not be repeated here.

[0090] Reference Figures 8 to 10 A metal interconnect structure 560 is formed in the second sub-dielectric layer 570. The metal interconnect structure 560 also extends through the bottom cap layer 610. The metal interconnect structure 560 includes a second test metal layer 580 and a first via interconnect structure 590 located between the second test metal layer 580 and the first test metal layer 550.

[0091] Specifically, such as Figure 8 As shown, a second trench 573T and a second through hole 571V connected to the bottom of the second trench 573T are formed in the second sub-dielectric layer 570. The second through hole 571V penetrates the cap layer 610 and exposes the top of the first test metal layer 550. The linewidth of the second through hole 571V is smaller than the linewidth of the second trench 573T.

[0092] The second trench 573T is used to provide space for the subsequent formation of the second test metal layer, and the second via 571V is used to provide space for the subsequent formation of the first via interconnect structure.

[0093] As an example, the second trench 573T and the second via 571V can be formed using an all-in-one-etch (AIO etch) method. Specifically, a dry etching process is used to etch the second sub-dielectric layer 570 to form the second trench 573T and the second via 571V. The dry etching process has anisotropic etching characteristics, which is beneficial for improving the morphology quality of the second trench 573T and the second via 571V.

[0094] like Figure 9 and Figure 10 As shown, Figure 9 It is a top view. Figure 10 for Figure 9 A cross-sectional view along line a1a2 shows a second test metal layer 580 formed in the second trench 573T and a first via interconnect structure 590 formed in the second via 571V.

[0095] Both the second test metal layer 580 and the first via interconnect structure 590 include: a conductive layer (not shown) and an adhesion barrier layer (not shown) covering the bottom and sidewalls of the conductive layer.

[0096] Specifically, the materials of the second test metal layer 580 and the first via interconnect structure 590 are the same as those of the first test metal layer 550. For the materials of the second test metal layer 580 and the first via interconnect structure 590 and their formation methods, please refer to the corresponding description of the first test metal layer 550, which will not be repeated here.

[0097] In this embodiment, the second test metal layer 580 is formed at both ends of the first test metal layer 550. The second test metal layer 580 located at one end of the first test metal layer 550 is used as the first application end, and the second test metal layer 580 located at the other end of the first test metal layer 550 is used as the second application end.

[0098] After a test current is applied at the application end, the current flows from one of the second test metal layers 580 to the first test metal layer 550. Figure 10 (The dashed arrow in the figure indicates the direction of current flow). Therefore, in this embodiment, the first test metal layer 550 is a metal layer through which the current flows. Accordingly, the first test metal layer 550 is used as the metal layer to be tested 551.

[0099] In this embodiment, the first test metal layer 550 and the second test metal layer 580 are electrically connected through the first through-hole interconnect structure 590. Therefore, after a test current is applied to the application end, the current flows from the second test metal layer 580 corresponding to the first application end to the first test metal layer 550 through the first through-hole interconnect structure 590. After the current flows through the first test metal layer 550, it flows through the first through-hole interconnect structure 590 to the second test metal layer 580 corresponding to the second application end.

[0100] It should be noted that, while forming the second test metal layer 580 in the second sub-dielectric layer 570, a first detection terminal 514 connected to the second test metal layer 580 corresponding to the first application terminal and a second detection terminal 515 connected to the second test metal layer 580 corresponding to the second application terminal are also formed in the second sub-dielectric layer 570. After applying a test current to the application terminal, the electromigration of the metal layer 551 under test is measured by detecting the resistance between the first detection terminal and the second detection terminal.

[0101] Continue to refer to Figures 8 to 10 A floating circuit structure 600 is formed in the second sub-dielectric layer 570 on top of the metal layer 551 under test. The floating circuit structure 600 penetrates the capping layer 610 on top of the metal layer 551 under test and is connected to the top of the metal layer 551 under test. The bonding force between the floating circuit structure 600 and the metal layer 551 under test is greater than the bonding force between the capping layer 610 and the metal layer 551 under test.

[0102] Since surface migration is the dominant mechanism in electromigration reliability failure, and the levitation circuit structure 600 has a stronger bond with the metal layer 551 under test compared to the capping layer 610, this helps to suppress the diffusion of the material of the metal layer 551 under test at the interface between the levitation circuit structure 600 and the metal layer 551 under test. Correspondingly, this helps to reduce the migration rate of metal atoms of the metal layer 551 under test along the interface between the levitation circuit structure 600 and the metal layer 551 under test. The effective length of the metal layer 551 under test at the interface between the metal layer 551 and the capping layer 610 is shortened accordingly, thereby reducing the probability of voids being generated at the top surface of the metal layer 551 under test due to directional movement with the electric field, and thus improving the electromigration reliability of the test structure.

[0103] According to the Blech length effect, for metal electromigration, under a fixed operating current density J, if the length L of the metal line through which the current flows is less than a certain length, the mean time to failure (MTTF) can be significantly increased. In other words, there exists a J*L threshold; when the product of the operating current density J and the metal strip length L exceeds this threshold to a certain extent, metal electromigration failure can occur significantly. Therefore, specifically in this embodiment, the addition of the floating circuit structure 600 is equivalent to replacing part of the capping layer 610 on top of the metal layer 551 under test. The effective length of the metal layer 551 under test at the interface between the metal layer 551 under test and the capping layer 610 is shortened, thereby reducing the length L of the metal strip and thus increasing the mean time to failure, i.e., improving the electromigration reliability of the test structure.

[0104] Furthermore, by adding a floating circuit structure 600 to the test structure, the floating circuit structure 600 does not form an additional shunt loop, and can maintain the original current flow and function of the circuit, thereby improving the electromigration reliability of the test structure while reducing the impact on the layout design of the test structure.

[0105] In this embodiment, the material of the floating circuit structure 600 includes one or both of metals and metal compounds, and the floating circuit structure 600 is configured with an open circuit. Since the material of the metal layer 551 under test includes metal, the bonding force between metals is higher than that between dielectric materials, and the bonding force between metals and metal compounds is also higher, thus facilitating a stronger bonding force between the floating circuit structure 600 and the metal layer 551 under test. Furthermore, metals and metal compounds also have high process compatibility with subsequent manufacturing processes.

[0106] Specifically, the metal includes one or more of copper, aluminum, titanium, and tantalum, and the metal compound includes one or more of titanium nitride and tantalum nitride. In other embodiments, other materials that are compatible with the back-end process and have stronger bonding with the metal layer under test can also be selected. Accordingly, in order to prevent the floating circuit structure 600 from forming an additional shunt loop, the floating circuit structure 600 is configured to be open-circuited.

[0107] In this embodiment, to reduce the probability of the floating circuit structure 600 interfering with other metal interconnect structures, the floating circuit structure 600 is staggered from the remaining metal interconnect structures. For example, when the material of the floating circuit structure 600 includes one or both of metals and metal compounds, it is beneficial to significantly reduce the probability of short circuits occurring between the floating circuit structure 600 and other metal interconnect structures. It is understood that the remaining metal interconnect structures here refer to the remaining metal interconnect structures other than the metal layer 551 under test.

[0108] In this embodiment, a floating circuit structure 600 is formed in the second sub-dielectric layer 570 corresponding to the first interconnect stacking process. The floating circuit 600 contacts the metal layer under test 551, thereby shortening the effective length of the metal layer under test 551 at the interface between the metal layer under test 551 and the capping layer 610. Therefore, by forming the floating circuit structure 600 in the second sub-dielectric layer 570 corresponding to the first interconnect stacking process, unnecessary cost waste is avoided, and the impact on the process flow above the second test metal layer 580 is also reduced.

[0109] Specifically, such as Figure 8 As shown, forming the floating circuit structure 600 includes: forming a third via 572V in the second sub-dielectric layer 570, penetrating the second sub-dielectric layer 570 and the capping layer 610, with the third via 572V exposing the top of the first test metal layer 550 located on the side of the second via 571V; and forming the floating circuit 600 in the third via 572V. As an example, the second sub-dielectric layer 570 is etched using a dry etching process to form the third via 572V. The dry etching process has anisotropic etching characteristics, which is beneficial for improving the morphology quality of the third via 572V.

[0110] Specifically, in the first interconnect stacking process, while forming the metal interconnect structure, a second via interconnect structure (not shown) is formed in the second sub-dielectric layer 570 of the current layer, penetrating both the second sub-dielectric layer 570 and the cap layer 610. This second via interconnect structure serves as a floating circuit structure 600. By forming the second via interconnect structure (i.e., the floating circuit structure 600) and the metal interconnect structure in the same step, an additional photomask is unnecessary, thereby simplifying the process steps and reducing process costs. For example, the same photomask can be used to form both the second via interconnect structure and the first via interconnect structure 590 in the second sub-dielectric layer 570. Furthermore, forming the second via interconnect structure as the floating circuit structure 600 improves the compatibility of the floating circuit structure 600 with subsequent processes.

[0111] Correspondingly, during the formation of the second via 571V, a third via 572V is also formed in the second sub-dielectric layer 570, penetrating the second sub-dielectric layer 570 and the capping layer 610. The third via 572V exposes the top of the first test metal layer 550 located on the side of the second via 571V. During the formation of the second test metal layer 580 in the second trench 573T and the formation of the first via interconnect structure 590 in the second via 571V, a second via interconnect structure is also formed in the third via 572V.

[0112] As an example, the second via interconnect structure (i.e., the floating circuit structure 600) and the first via interconnect structure 590 have the same linewidth along the direction parallel to the top surface of the substrate.

[0113] It should be noted that, in other embodiments, depending on process requirements, a floating circuit structure can also be formed separately in the second sub-dielectric layer.

[0114] like Figure 9 As shown, in this embodiment, there are multiple floating circuit structures 600 on the same metal layer 551 under test, and these multiple floating circuit structures 600 are separately disposed on the top of the metal layer 551 under test along the extension direction of the metal layer 551 under test. Because there are multiple floating circuit structures 600, the linewidth of a single floating circuit structure 600 along the direction parallel to the top surface of the substrate will not be too large, thereby improving compatibility with subsequent processes. At the same time, increasing the number of floating circuit structures 600 means that the effective length of the metal layer 551 under test at the interface between the metal layer 551 under test and the capping layer 610 is shortened, thereby reducing the overall probability of voids being generated at the top surface of the metal layer 551 under test due to directional movement with the electric field.

[0115] It should be noted that even if multiple floating circuit structures 600 are disposed separately on top of the metal layer 551 under test along the extension direction of the metal layer 551 under test, there is still contact between the metal layer 551 under test and the capping layer 610 between adjacent floating circuit structures 600. However, based on the existence of the Blech length effect, the migration rate of metal atoms of the metal layer 551 under test along the interface between the metal layer 551 under test and the capping layer 610 can still be effectively reduced.

[0116] Correspondingly, the smaller the spacing between adjacent levitated circuit structures 600, the more significant the effect on improving the electromigration reliability of the test structure. Therefore, in this embodiment, the spacing S between adjacent levitated circuit structures 600 along the extension direction of the metal layer 551 under test is less than or equal to 60 micrometers. As an example, the spacing S between adjacent levitated circuit structures 600 is less than or equal to 40 micrometers.

[0117] Similarly, the more floating circuit structures 600 there are, the shorter the effective length of the metal layer 551 under test at the interface between the metal layer 551 under test and the capping layer 610, and the more significant the effect of improving the electromigration reliability of the test structure. Therefore, the number of floating circuit structures 600 on the top of the same metal layer 551 under test is the maximum allowable number to meet the minimum spacing design rule.

[0118] Specifically, the number of floating circuit structures 600 on the top of the same metal layer 551 under test is determined by the length of the metal layer 551 under test and the spacing S between adjacent floating circuit structures 600.

[0119] In this embodiment, multiple floating circuit structures 600 on the same metal layer 551 under test are equally spaced on the top of the metal layer 551 under test. On the one hand, this helps to reduce the difficulty of the layout design of the floating circuit structures 600. On the other hand, the equal spacing makes the floating circuit structures 600 evenly distributed on the top of the metal layer 551 under test, which helps to make the failure probability of the area between each floating circuit structure 600 similar, thereby reducing the possibility that the failure probability of the area will increase due to the excessive spacing between some floating circuit structures 600.

[0120] Figures 11 to 13 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the test structure of the present invention. The similarities between this embodiment and the previous embodiment will not be repeated here. The difference between this embodiment and the previous embodiment is that the second test metal layer 710 is the metal layer 715 to be tested.

[0121] refer to Figure 11 After the first interconnect stacking process, the first test metal layer 700, the second test metal layer 710, and the first through-hole interconnect structure 720 located between them are used to form the test interconnect structure.

[0122] In this embodiment, the test structure is used to test the electromigration reliability under uplink conditions; therefore, the second test metal layer 710 is the metal layer under test 715. Specifically, the two ends of the second test metal layer 710 are electrically connected to different first test metal layers 700, with the first test metal layer 700 located at one end of the second test metal layer 710 serving as the first application end, and the first test metal layer 700 located at the other end of the second test metal layer 710 serving as the second application end. It should be noted that... Figure 11 Only one of the first test metal layers 700 is shown in the diagram.

[0123] In this embodiment, the first test metal layer 700 and the second test metal layer 710 are electrically connected through a first through-hole interconnect structure 720. Therefore, after a test current is applied to the application end, the current flows from the first test metal layer 700 corresponding to the first application end to the second test metal layer 710 through the first through-hole interconnect structure 720. Figure 11 (The dashed arrow in the diagram indicates the direction of current flow). After the current flows through the second test metal layer 710, it flows through the first via interconnect structure 720 to the first test metal layer 700 corresponding to the second application end. Therefore, in this embodiment, the second test metal layer 710 is a metal layer through which the current flows, and the second test metal layer 710 is correspondingly used as the metal layer to be tested 715.

[0124] Therefore, in conjunction with the reference Figures 11 to 13In this embodiment, the interconnect stacking process also includes a second interconnect stacking process that is performed after the first interconnect stacking process and sequentially with the first interconnect stacking process. A floating circuit structure 800 is formed in the second sub-dielectric layer 740 corresponding to the second interconnect stacking process. The floating circuit structure 800 is connected to the top of the metal layer 715 under test.

[0125] Correspondingly, a capping layer 810 is also formed between the second test metal layer 710 and the second sub-dielectric layer 740 corresponding to the second interconnect stacking process. Based on the foregoing analysis, it can be seen that the electromigration reliability failure mechanism is dominated by surface migration, that is, the metal atoms of the test metal layer 715 usually migrate along the interface between the test metal layer 715 and the capping layer 810. Therefore, the floating circuit structure 800 is located on top of the test metal layer 715 and penetrates through the capping layer 810 to replace part of the capping layer 810 on the top surface of the test metal layer 715.

[0126] In this embodiment, forming the floating circuit structure 800 includes: in the second interconnect stacking process, after forming a capping layer 810 and a second sub-dielectric layer 740 covering the capping layer 810, forming a fourth via 745V penetrating the second sub-dielectric layer 740 and the capping layer 810 in the second sub-dielectric layer 740 at the top of the metal layer 715 under test, the fourth via 745V exposing the top of the metal layer 715 under test; and forming the floating circuit structure 800 in the fourth via 745V. Specifically, in the second interconnect stacking process, while forming a metal interconnect structure (not shown), a second via interconnect structure penetrating the second sub-dielectric layer 740 and the capping layer 810 is formed in the second sub-dielectric layer 740 of the current layer, the second via interconnect structure serving as the floating circuit structure 800.

[0127] It should be noted that in the second interconnect stacking process, the metal interconnect structure formed in the second sub-dielectric layer 740 is not shown in this embodiment. The metal interconnect structure may be formed in other areas of the second sub-dielectric layer 740.

[0128] It should also be noted that the metal interconnect structure formed in the second sub-dielectric layer 740 typically includes a third via interconnect structure (not shown). Therefore, by forming the second via interconnect structure (i.e., the floating circuit structure 800) and the metal interconnect structure in the second sub-dielectric layer 740 in the same step, an additional photomask is unnecessary. That is, the photomask corresponding to the metal interconnect structure in the second interconnect stacking process can be used to form the second via interconnect structure, thereby simplifying the process steps and reducing process costs. Furthermore, forming the second via interconnect structure as the floating circuit structure 800 improves the compatibility of the floating circuit structure 800 with subsequent processes. As an example, the second via interconnect structure (i.e., the floating circuit structure 800) and the third via interconnect structure have the same linewidth along the direction parallel to the top surface of the substrate.

[0129] For a detailed description of the method for forming this embodiment, please refer to the corresponding descriptions of the foregoing embodiments, which will not be repeated here.

[0130] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A test structure, characterized in that, include: Base; A dielectric layer is located on the substrate; A test interconnect structure is located in the dielectric layer. The test interconnect structure includes a metal layer and a first via interconnect structure connecting adjacent metal layers. The metal layer includes a first test metal layer and a second test metal layer that are adjacent in the longitudinal direction. The second test metal layer is located above the first test metal layer. According to the current flow direction, the layer through which the current flows from the first metal layer and the second metal layer is used as the metal layer to be tested. A capping layer is located on top of the metal layer and between the dielectric layer; A floating circuit structure is located in the dielectric layer on top of the metal layer under test. The floating circuit structure penetrates the capping layer on top of the metal layer under test and is connected to the top of the metal layer under test. The bonding force between the floating circuit structure and the metal layer under test is greater than the bonding force between the capping layer and the metal layer under test.

2. The test structure as described in claim 1, characterized in that, The material of the suspended circuit structure includes one or two of metals and metal compounds, and the suspended circuit structure is provided with an open circuit.

3. The test structure as described in claim 2, characterized in that, The metal includes one or more of copper, aluminum, titanium, and tantalum, and the metal compound includes one or more of titanium nitride and tantalum nitride.

4. The test structure as described in claim 2, characterized in that, The suspended circuit structure is staggered from the remaining metal layer.

5. The test structure as described in claim 2, characterized in that, The suspended circuit structure is a second through-hole interconnect structure, and the second through-hole interconnect structure is made of the same material as the first through-hole interconnect structure.

6. The test structure as described in claim 1, characterized in that, The first test metal layer is the metal layer to be tested, the floating circuit structure is located in the dielectric layer on the side of the second test metal layer, and the top of the floating circuit structure is flush with the top of the second test metal layer.

7. The test structure as described in claim 1, characterized in that, The number of the floating circuit structures on the same metal layer under test is multiple, and the multiple floating circuit structures are separately arranged on the top of the metal layer under test along the extension direction of the metal layer under test.

8. The test structure as described in claim 7, characterized in that, The number of floating circuit structures on top of the same metal layer under test is the maximum allowable number that satisfies the minimum spacing design rule.

9. The test structure as described in claim 7, characterized in that, Along the extension direction of the metal layer under test, the spacing between adjacent floating circuit structures is less than or equal to 60 micrometers.

10. The test structure as described in claim 7, characterized in that, Multiple floating circuit structures on the same metal layer under test are equally spaced on the top of the metal layer under test.

11. The test structure as described in any one of claims 1 to 10, characterized in that, Both the metal layer and the first via interconnect structure include: a conductive layer, and an adhesion barrier layer covering the bottom and sidewalls of the conductive layer; The material of the adhesion barrier layer includes one or more of titanium, titanium nitride, tantalum, and tantalum nitride; the material of the conductive layer includes copper or aluminum.

12. The test structure as described in any one of claims 1 to 10, characterized in that, The capping layer is made of one or more of silicon nitride and nitrogen-doped silicon carbide.

13. A method for forming a test structure, characterized in that, include: A substrate is provided on which a first sub-dielectric layer and a first test metal layer located in the first sub-dielectric layer are formed; An interconnect stacking process is performed above the first sub-dielectric layer and the first test metal layer. The interconnect stacking process includes: forming a capping layer above the first sub-dielectric layer and the first test metal layer; forming a second sub-dielectric layer on the capping layer; and forming a metal interconnect structure in the second sub-dielectric layer, the metal interconnect structure extending through the bottom capping layer. The interconnect stacking process includes a first interconnect stacking process performed sequentially after the formation of the first sub-dielectric layer and the first test metal layer. The metal interconnect structure formed by the first interconnect stacking process includes a second test metal layer and a first via interconnect structure located between the second test metal layer and the first test metal layer. The first test metal layer, the second test metal layer, and the first via interconnect structure located between them constitute a test interconnect structure. According to the current flow direction, the layer through which the current flows last in the first and second test metal layers is used as the metal layer under test. A floating circuit structure is formed in the second sub-dielectric layer on top of the metal layer under test. The floating circuit structure penetrates the capping layer on top of the metal layer under test and is connected to the top of the metal layer under test. The bonding force between the floating circuit structure and the metal layer under test is greater than the bonding force between the capping layer and the metal layer under test.

14. The method for forming the test structure as described in claim 13, characterized in that, The material of the suspended circuit structure includes one or two of metals and metal compounds, and the suspended circuit structure is provided with an open circuit.

15. The method for forming the test structure as described in claim 14, characterized in that, The metal includes one or more of copper, aluminum, titanium, and tantalum, and the metal compound includes one or more of titanium nitride and tantalum nitride.

16. The method for forming the test structure as described in claim 13, characterized in that, The suspended circuit structure is staggered from the remaining metal interconnect structure.

17. The method for forming the test structure as described in claim 13, characterized in that, The first test metal layer is the metal layer to be tested; The floating circuit structure is formed in the second sub-dielectric layer corresponding to the first interconnect stacking process; or, The second test metal layer is the metal layer to be tested; The interconnect stacking process further includes a second interconnect stacking process performed after and sequentially with the first interconnect stacking process, wherein the floating circuit structure is formed in the second sub-dielectric layer corresponding to the second interconnect stacking process.

18. The method for forming the test structure as described in claim 17, characterized in that, The first test metal layer is the metal layer to be tested; In the first interconnect stacking process, while forming the metal interconnect structure, a second via interconnect structure is formed in the second sub-dielectric layer of the current layer, penetrating the second sub-dielectric layer and the capping layer. The second via interconnect structure is used as a floating circuit structure. or, The second test metal layer is the metal layer to be tested; In the second interconnect stacking process, while forming the metal interconnect structure, a second via interconnect structure is formed in the second sub-dielectric layer of the current layer, penetrating the second sub-dielectric layer and the capping layer. The second via interconnect structure is used as a floating circuit structure.

19. The method for forming the test structure as described in claim 13, characterized in that, The number of the floating circuit structures on the same metal layer under test is multiple, and the multiple floating circuit structures are separately arranged on the top of the metal layer under test along the extension direction of the metal layer under test.

20. The method for forming the test structure as described in claim 16, characterized in that, The number of floating circuit structures on top of the same metal layer under test is the maximum allowable number that satisfies the minimum spacing design rule.

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