Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a first gate structure and a first contact structure arranged on the substrate, the first contact structure comprising a first contact part and a second contact part, the first contact part being connected with the second contact part, the first contact part being located between the second contact part and the substrate, the first contact structure being electrically connected with the first gate structure and the substrate, and the cross-sectional area of the first contact part being larger than that of the second contact part. Compared with the prior art, the application can ensure the contact area between the first contact structure and the substrate, thereby reducing the contact resistance, improving the signal transmission efficiency and stability, and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology

[0002] Electronic devices such as memory and controllers typically incorporate semiconductor structures, including MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). MOSFETs are used to perform functions such as switching and amplification. A MOSFET includes a substrate and a gate formed on the substrate. The substrate has source and drain regions spaced apart, and the gate is located between the source and drain regions.

[0003] In related technologies, the gate and source / drain regions of a MOSFET are electrically connected via conductive plugs to achieve a single conductive function. However, the contact resistance between the conductive plugs and the source / drain regions is relatively high, affecting the performance of the semiconductor structure. Summary of the Invention

[0004] In a first aspect, embodiments of this application provide a semiconductor structure including a substrate. A first gate structure and a first contact structure are disposed on the substrate. The first contact structure includes a first contact portion and a second contact portion. The first contact portion is connected to the second contact portion, and the first contact portion is located between the second contact portion and the substrate.

[0005] The first contact structure is electrically connected to the first gate structure and the substrate, and the cross-sectional area of ​​the first contact portion is greater than the cross-sectional area of ​​the second contact portion.

[0006] In one possible implementation, the first gate structure includes a gate conductive layer, and a conductive structure is disposed at one end of the gate structure away from the substrate. The conductive structure is in contact with the gate conductive layer and is electrically connected to the second contact portion. The conductive structure and the second contact portion are located in the same plane.

[0007] In one possible implementation, the conductive structure and the second contact portion further include an isolation layer on the bottom and sidewalls of the conductive structure and the second contact portion.

[0008] In one possible implementation, the first gate structure includes a gate conductive layer, the first contact portion contacts the sidewall of the gate conductive layer, and the first contact portion is flush with the top surface of the gate conductive layer.

[0009] In one possible implementation, the sidewall portion of the gate conductive layer covers a conductive contact pad, and the first contact portion contacts the upper surface of the conductive contact pad.

[0010] In one possible implementation, the bottom and sidewalls of the second contact portion have an isolation layer.

[0011] In one possible implementation, the bottom and sidewalls of the first contact portion have the isolation layer.

[0012] In one possible implementation, a first dielectric layer and a second dielectric layer are further disposed on the substrate, the first dielectric layer being located between the second dielectric layer and the substrate, the first dielectric layer being flush with the top surface of the gate conductive layer, and the second dielectric layer being flush with the top surface of the first gate structure.

[0013] In one possible implementation, the substrate is further provided with a second contact structure and a second gate structure, the second gate structure being spaced apart from the first gate structure, the first contact structure being located between the first gate structure and the second gate structure and contacting the sidewalls of the first gate structure and the second gate structure respectively, the second contact structure being located on the side of the first gate structure opposite to the first contact structure, and the second contact structure also being located on the side of the second gate structure opposite to the first contact structure.

[0014] In one possible implementation, the second contact structure includes a third contact portion and a fourth contact portion, the third contact portion being connected to the fourth contact portion and located between the fourth contact portion and the substrate, the third contact portion contacting and being electrically connected to the substrate.

[0015] The cross-sectional area of ​​the third contact portion is greater than that of the fourth contact portion.

[0016] Secondly, embodiments of this application provide a method for fabricating a semiconductor structure, including:

[0017] A substrate is provided, on which a first gate structure is disposed;

[0018] A first contact portion is formed on the substrate;

[0019] A second contact portion is formed on top of the first contact portion; the second contact portion is connected to the first contact portion and together form a first contact structure, the first contact structure is electrically connected to the first gate structure and the substrate, and the cross-sectional area of ​​the first contact portion is greater than the cross-sectional area of ​​the second contact portion.

[0020] In one possible implementation, forming the first contact portion on the substrate includes:

[0021] A first dielectric layer is formed on the substrate. The first dielectric layer has a first groove. The first gate structure is located in the first groove. The first gate structure includes a gate conductive layer. The first dielectric layer is flush with the top surface of the gate conductive layer.

[0022] An isolation layer is formed on the bottom wall and side wall of the first groove;

[0023] The first groove is filled with conductive material to form the first contact portion.

[0024] In one possible implementation, a second contact portion is formed on top of the first contact portion, including:

[0025] A second dielectric layer is formed on the first dielectric layer, the second dielectric layer being flush with the top surface of the first gate structure, the second dielectric layer having a second groove, the bottom of the second groove including the gate conductive layer and the first contact portion;

[0026] A conductive structure and a second contact portion are formed within the second groove to electrically connect the conductive structure and the second contact portion.

[0027] In one possible implementation, a conductive structure and a second contact portion are formed within the second groove, including:

[0028] The isolation layer is formed on the bottom and sidewalls of the second groove;

[0029] The conductive material is filled into the second groove to form the integrally molded conductive structure and the second contact portion.

[0030] In one possible implementation, a substrate is provided, on which a first gate structure is disposed, including:

[0031] The first gate structure includes a gate conductive layer and a gate isolation layer covering the top surface of the gate conductive layer. One side of the gate conductive layer is covered with an insulating sidewall, and the other side of the gate conductive layer away from the insulating sidewall is exposed.

[0032] Conductive contact pads are formed on the sidewalls of a portion of the gate conductive layer and on the substrate.

[0033] In one possible implementation, forming the first contact portion on the substrate includes:

[0034] A first dielectric layer is formed on the substrate, the first dielectric layer having a first groove, the first gate structure being located in the first groove, and the first dielectric layer being flush with the top surface of the gate conductive layer.

[0035] An isolation layer is formed on the bottom wall and side wall of the first groove;

[0036] The conductive material is filled into the first groove to form the first contact portion, which covers part of the sidewall of the gate conductive layer and the upper surface of the conductive contact pad.

[0037] In one possible implementation, a second contact portion is formed on top of the first contact portion, including:

[0038] A second dielectric layer is formed on the first dielectric layer, the second dielectric layer being flush with the top surface of the first gate structure, and the second dielectric layer having a second groove;

[0039] The isolation layer is formed on the bottom wall and side wall of the second groove;

[0040] The conductive material is filled into the second groove to form the second contact portion.

[0041] In one possible implementation, a first gate structure is disposed on the substrate, comprising:

[0042] A second gate structure is also disposed on the substrate, and the second gate structure is disposed at a distance from the first gate structure.

[0043] A second contact portion is formed on top of the first contact portion, including:

[0044] The first contact structure is located between the first gate structure and the second gate structure, and is in contact with the sidewalls of the first gate structure and the second gate structure, respectively.

[0045] In one possible implementation, forming the first contact portion on the substrate includes:

[0046] A third contact portion is formed on the substrate, the third contact portion being in contact with and electrically connected to the substrate;

[0047] A second contact portion is formed on top of the first contact portion, including:

[0048] A fourth contact portion is formed on the top of the third contact portion. The second contact portion is connected to the first contact portion and together forms a second contact structure. The second contact structure is located on the side of the first gate structure opposite to the first contact structure. The second contact structure is also located on the side of the second gate structure opposite to the first contact structure. The cross-sectional area of ​​the first contact portion is larger than the cross-sectional area of ​​the second contact portion.

[0049] The conductive contact pad is a metal silicide.

[0050] This application provides a semiconductor structure and a method for fabricating the semiconductor structure, including: a substrate, on which a first gate structure and a first contact structure are disposed, the first contact structure including a first contact portion and a second contact portion, the first contact portion being connected to the second contact portion and located between the second contact portion and the substrate, the first contact structure being electrically connected to the first gate structure and the substrate, and the cross-sectional area of ​​the first contact portion being larger than the cross-sectional area of ​​the second contact portion. Compared with related technologies, this application, as the integration level of semiconductor structures continues to increase, can ensure the contact area between the first contact structure and the substrate, reduce the contact resistance of the silicon surface, improve signal transmission efficiency and transmission stability, and enhance the performance of the semiconductor structure. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 1 ;

[0053] Figure 2 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 2 ;

[0054] Figure 3 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0055] Figure 4 A schematic diagram of the substrate provided in a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 1 ;

[0056] Figure 5 This application provides a schematic diagram of the structure for forming conductive contact pads in a method for fabricating a semiconductor structure. Figure 1 ;

[0057] Figure 6 for Figure 5 Cross-sectional view of section A1-A1;

[0058] Figure 7 This is a schematic diagram of the structure forming an intermediate dielectric layer in a method for fabricating a semiconductor structure according to an embodiment of this application;

[0059] Figure 8This application provides a schematic diagram of the structure for forming a first dielectric layer in a method for fabricating a semiconductor structure according to an embodiment of the present application. Figure 1 ;

[0060] Figure 9 This application provides a schematic diagram of the structure for forming a first groove in a method for fabricating a semiconductor structure according to an embodiment of the present application. Figure 1 ;

[0061] Figure 10 for Figure 9 Cross-sectional view of section B1-B1;

[0062] Figure 11 for Figure 9 Cross-sectional view of section C1-C1;

[0063] Figure 12 A schematic diagram of the structure for forming the first contact portion in a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 1 ;

[0064] Figure 13 for Figure 12 Cross-sectional view of section D1-D1;

[0065] Figure 14 A schematic diagram of the structure for forming a second dielectric layer in a method for fabricating a semiconductor structure provided in this application embodiment. Figure 1 ;

[0066] Figure 15 This application provides a schematic diagram of the structure for forming a second groove in a method for fabricating a semiconductor structure according to an embodiment of the present application. Figure 1 ;

[0067] Figure 16 A schematic diagram of the structure for forming the second contact portion in a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 1 ;

[0068] Figure 17 for Figure 16 Cross-sectional view of section E1-E1;

[0069] Figure 18 A schematic diagram of the substrate provided in a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 2 ;

[0070] Figure 19 This application provides a schematic diagram of the structure for forming conductive contact pads in a method for fabricating a semiconductor structure. Figure 2 ;

[0071] Figure 20 for Figure 18 Cross-sectional view of section A2-A2;

[0072] Figure 21 This application provides a schematic diagram of the structure for forming a first dielectric layer in a method for fabricating a semiconductor structure according to an embodiment of the present application. Figure 2 ;

[0073] Figure 22 This application provides a schematic diagram of the structure for forming a first groove in a method for fabricating a semiconductor structure according to an embodiment of the present application. Figure 2 ;

[0074] Figure 23 A schematic diagram of the structure for forming the first contact portion in a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 2 ;

[0075] Figure 24 for Figure 23 Cross-sectional view of section B2-B2;

[0076] Figure 25 A schematic diagram of the structure for forming a second dielectric layer in a method for fabricating a semiconductor structure provided in this application embodiment. Figure 2 ;

[0077] Figure 26 This application provides a schematic diagram of the structure for forming a second groove in a method for fabricating a semiconductor structure according to an embodiment of the present application. Figure 1 ;

[0078] Figure 27 A schematic diagram of the structure for forming the second contact portion in a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 2 ;

[0079] Figure 28 for Figure 27 Cross-sectional view of section C2-C2. Detailed Implementation

[0080] The inventors of this application discovered during their research that in related DRAM technologies, signal transmission is achieved by connecting a contact plug to a portion of the substrate. For example, in the transistor structure of a DRAM, the substrate is doped to form an active region, within which a source region and a drain region are formed, with a channel between them. To achieve a single conductive function, the contact plug, while contacting and electrically connecting to the substrate located in the source or drain region, is also electrically connected to the gate structure, realizing a conductive plug with interconnection functionality. The cross-sectional area of ​​the contact plug is approximately equal along its extension direction. However, as the integration density of DRAM continues to increase, the contact area between the contact plug and the substrate in the aforementioned DRAM decreases accordingly, leading to an increase in the contact resistance between the contact plug and the substrate. This affects the signal transmission of the contact plug within the substrate, which in turn impacts the storage performance of the semiconductor memory.

[0081] In view of this, the semiconductor structure and its fabrication method provided in this application include: a substrate, on which a first gate structure and a first contact structure are disposed, the first contact structure including a first contact portion and a second contact portion, the first contact portion being connected to the second contact portion and located between the second contact portion and the substrate, the first contact structure being electrically connected to the first gate structure and the substrate, and the cross-sectional area of ​​the first contact portion being larger than that of the second contact portion. Compared with related technologies, this application, as the integration level of semiconductor structures continues to increase, can ensure the contact area between the first contact structure and the substrate, reduce the contact resistance of the silicon surface, improve signal transmission efficiency and transmission stability, and enhance the performance of the semiconductor structure.

[0082] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0083] like Figure 1 and Figure 2As shown, the semiconductor structure includes a substrate 10, on which a first gate structure 20 and a first contact structure 40 are disposed. The first contact structure 40 includes a first contact portion 401 and a second contact portion 403. The first contact portion 401 is connected to the second contact portion 403, and the first contact portion 401 is located between the second contact portion 403 and the substrate 10. The first contact structure 40 is electrically connected to the first gate structure 20 and the substrate 10. The cross-sectional area of ​​the first contact portion 401 is larger than the cross-sectional area of ​​the second contact portion 403.

[0084] The semiconductor structure provided in this application can be a memory device or a non-memory device. Memory devices may include, for example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). Non-memory devices may be logic devices (e.g., microprocessors, digital signal processors, or microcontrollers) or similar devices. This application uses a DRAM memory device as an example for illustration.

[0085] The substrate 10 provides the structural basis for subsequent structures and processes. The material of the substrate 10 may include silicon, germanium, silicon-germanium, silicon carbide, silicon-on-insulator substrate 10, and germanium-on-insulator substrate 10, or any combination thereof. In this embodiment, the substrate 10 is a silicon substrate 10. Conductive contact regions (not shown in the figure) can be formed in the silicon substrate 10 by doping; for example, phosphorus can be doped into the silicon substrate 10. These conductive contact regions allow the substrate 10 to contact and electrically conduct with the first contact structure 40.

[0086] In this embodiment, a conductive contact pad 12 is also covered on the conductive contact area. The conductive contact pad 12 can be made of metal silicide, thereby further improving the conductivity between the first contact structure 40 and the substrate 10. The material of the conductive contact pad 12 may include, for example, copper silicide, cobalt silicide, and tungsten silicide.

[0087] The substrate 10 may also have a core region and a peripheral region, with the peripheral region surrounding the outer periphery of the core region. Storage elements are disposed on the substrate 10 within the core region, while various electronic components, including control elements, may be disposed on the substrate 10 within the peripheral region; this embodiment does not impose any limitations on this. The storage elements within the core region may include capacitors and transistors. The gate of the transistor is connected to the word line (WL), the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line. The word line is connected to the word line driver through a local interconnect contact (LICON) located in the peripheral region of the storage cell, facilitating the input of voltage signals to the word line by the word line driver. In this embodiment, the conductive contact area may be formed within the core region or within the peripheral region.

[0088] The first gate structure 20 disposed on the substrate 10 can form the gate of a memory element in the core region or be located in the peripheral region. The first gate structure 20 may include a gate conductive layer 21, a gate isolation layer 24, and an insulating sidewall 25. The gate conductive layer 21 is disposed on the substrate 10. In this embodiment, a gate oxide layer 22 and a titanium nitride layer 23 may also be disposed between the gate conductive layer 21 and the substrate 10, wherein the titanium nitride layer 23 covers the substrate 10, and the gate oxide layer 22 covers the side of the titanium nitride layer 23 away from the substrate 10. The gate isolation layer 24 is located on the side of the gate conductive layer 21 away from the substrate 10, and the insulating sidewall 25 covers the sidewalls of the gate conductive layer 21 and the gate isolation layer 24. The gate conductive layer 21 may be made of a metal material, such as tungsten. The gate isolation layer 24 may be made of silicon nitride, for example, and the insulating sidewall 25 may be a composite layer of silicon nitride-silicon oxide-silicon nitride or a composite layer of silicon oxide-silicon nitride-silicon oxide.

[0089] The first contact structure 40 includes a first contact portion 401 and a second contact portion 403. The first contact portion 401 is in contact with and electrically connected to a conductive contact area on the substrate 10 to achieve signal transmission between the first contact structure 40 and the substrate 10. Furthermore, the first contact structure 40 is also in contact with and electrically connected to the gate conductive layer 21 of the first gate structure 20, enabling the first contact structure 40 to form an interconnecting contact between the first gate structure 20 and the substrate 10, achieving a single conductive function.

[0090] In this embodiment, the cross-sectional area of ​​the first contact portion 401 is larger than that of the second contact portion 403, which can effectively increase the contact area between the first contact portion 401 and the substrate 10. Compared with related technologies, this application can ensure the contact area between the first contact structure 40 and the substrate 10 as the integration level of semiconductor structures continues to increase, reduce the contact resistance of the silicon surface, improve signal transmission efficiency and transmission stability, and enhance the performance of the semiconductor structure.

[0091] Reference Figure 1 In one possible implementation, a conductive structure 402 may be provided at the end of the first gate structure 20 facing away from the substrate 10. The conductive structure 402 is in contact with the gate conductive layer 21 and is also electrically connected to the second contact portion 403. The conductive structure 402 and the second contact portion 403 are located in the same plane. By providing the conductive structure 402, the first contact portion 401 is electrically connected to the gate conductive layer 21 through the second contact portion 403 and the conductive structure 402. Having the conductive structure 402 and the second contact portion 403 in the same plane facilitates the co-fabrication of the conductive structure 402 and the second contact portion 403, improving the fabrication efficiency of the semiconductor structure.

[0092] Continue to refer to Figure 1 The conductive structure 402 contacts the second contact portion 403, and the conductive structure 402 and the second contact portion 403 can be integrally formed, which helps to reduce the fabrication difficulty of the conductive structure 402 and the second contact portion 403, and further improves the fabrication efficiency of the semiconductor structure. Furthermore, the conductive structure 402 and the second contact portion 403 can be made of the same material, which helps to avoid the problem of affecting the conductivity of the overall structure due to different materials. It also helps to adjust the cross-sectional area of ​​the integral structure formed by the conductive structure 402 and the second contact portion 403, thereby adjusting the contact area between the integral structure formed by the conductive structure 402 and the second contact portion 403 and the first contact portion 401, thereby improving the conductivity of the first contact structure 40.

[0093] Of course, in some other embodiments, the conductive structure 402 and the second contact portion 403 may also be provided with other conductive components so that the conductive structure 402 and the second contact portion 403 are electrically connected through other conductive components.

[0094] An isolation layer 41 may be provided at the bottom and sidewalls of the conductive structure 402 and the second contact portion 403. A conductive material 42 is covered on the isolation layer 41, and the conductive material 42 and the isolation layer 41 together constitute the integrated structure. The isolation layer 41 may be made of titanium nitride, for example, which has good corrosion resistance, conductivity, and intermetallic adhesion, so that the integrated structure formed by the conductive structure 402 and the second contact portion 403 has good electrical connection performance with the gate conductive layer 21 and the first contact portion 401, respectively. Furthermore, the conductive material 42 may include conductive metals such as titanium or tungsten.

[0095] Reference Figure 2 In another possible implementation, in the first gate structure 20, an insulating sidewall 25 covers one side of the gate conductive layer 21 and the gate isolation layer 24, while the other side of the gate conductive layer 21 and the gate isolation layer 24 is exposed. Here, "exposed" means that the other side of the gate conductive layer 21 and the gate isolation layer 24 is not covered by the insulating sidewall 25. A first contact portion 401 covers the side of the gate conductive layer 21 facing away from the insulating sidewall 25, and the first contact portion 401 contacts the sidewall of the gate conductive layer 21 to achieve electrical conduction between the first contact portion 401 and the gate conductive layer 21. Furthermore, the first contact portion 401 is flush with the top surface of the gate conductive layer 21, which facilitates the formation of a second contact portion 403 on the top surface of the first contact portion 401 and the gate conductive layer 21. This adjusts the contact area between the second contact portion 403 and the first contact portion 401 and the top surface of the gate conductive layer 21, thereby improving the conductivity of the first contact structure 40.

[0096] Continue to refer to Figure 2 The sidewalls of the gate conductive layer 21 may be partially covered by conductive contact pads 12, and the first contact portion 401 contacts the upper surface of the conductive contact pads 12. Similarly, by providing conductive contact pads 12 on the gate conductive layer 21, it is beneficial to further improve the conductivity between the first contact structure 40 and the gate conductive layer 21. The gate conductive layer 21 includes a first conductive layer 212 and a second conductive layer 211. The first conductive layer 212 covers the side of the gate oxide layer 22 away from the substrate 10, and the second conductive layer 211 covers the first conductive layer 212. The material of the second conductive layer 211 may include conductive metals such as titanium or tungsten, and the material of the first conductive layer 212 may include polysilicon. The conductive contact pads 12 may cover the sidewalls of the first conductive layer 212.

[0097] In embodiments where the first contact portion 401 contacts the sidewall of the gate conductive layer 21, the bottom and sidewall of the second contact portion 403 have an isolation layer 41. A conductive material 42 is coated on the isolation layer 41, and the conductive material 42 and the isolation layer 41 together constitute the second contact portion 403. The isolation layer 41 may be made of, for example, titanium nitride, which has good corrosion resistance, conductivity, and intermetallic adhesion, to ensure good electrical connection between the second contact portion 403 and both the gate conductive layer 21 and the first contact portion 401. Furthermore, the conductive material 42 may be made of conductive metals such as titanium or tungsten.

[0098] The following is combined with Figure 1 and Figure 2 Other structures in this embodiment will be described.

[0099] In this embodiment, the bottom and sidewalls of the first contact portion 401 may have an isolation layer 41. A conductive material 42 is coated on the isolation layer 41, and the conductive material 42 and the isolation layer 41 together constitute the first contact portion 401. The isolation layer 41 may be made of, for example, titanium nitride, which has good corrosion resistance, conductivity, and intermetallic adhesion, to ensure good electrical connection between the first contact portion 401 and the substrate 10. Furthermore, the conductive material 42 may be made of conductive metals such as titanium or tungsten.

[0100] In this embodiment, a first dielectric layer 30 and a second dielectric layer 50 are further disposed on the substrate 10. The first dielectric layer 30 is located between the second dielectric layer 50 and the substrate 10. The first dielectric layer 30 is flush with the top surface of the gate conductive layer 21, and the second dielectric layer 50 is flush with the top surface of the first gate structure 20. By providing the first dielectric layer 30 and the second dielectric layer 50, the structural regularity of the semiconductor structure can be improved, and the fabrication difficulty can be reduced. Furthermore, a first contact portion 401 can be fabricated in the first dielectric layer 30 and made flush with the top surface of the gate conductive layer 21; a second contact portion 403 can be fabricated in the second dielectric layer 50 and made flush with the top surface of the first gate structure 20, thereby further reducing the fabrication difficulty and improving the fabrication efficiency of the semiconductor structure.

[0101] In this embodiment, a second gate structure is further disposed on the substrate 10. The second gate structure and the first gate structure 20 are disposed at a distance on the substrate 10, and the first gate structure 20 and the second gate structure are located between adjacent shallow trench isolation structures 11. A first contact structure 40 is located between the first gate structure 20 and the second gate structure, and contacts the sidewalls of the first gate structure 20 and the second gate structure, respectively. The second gate structure may include a gate conductive layer 21, a gate isolation layer 24, and an insulating sidewall 25. The gate conductive layer 21 is disposed on the substrate 10. A gate oxide layer 22 and a titanium nitride layer 23 may also be disposed between the gate conductive layer 21 and the substrate 10, wherein the titanium nitride layer 23 covers the substrate 10, and the gate oxide layer 22 covers the side of the titanium nitride layer 23 away from the substrate 10. The gate isolation layer 24 is located on the side of the gate conductive layer 21 away from the substrate 10, and the insulating sidewall 25 covers the sidewalls of the gate conductive layer 21 and the gate isolation layer 24. The gate conductive layer 21 may be made of a metallic material, such as tungsten. The gate isolation layer 24 can be made of silicon nitride, for example, and the insulating sidewall 25 can be a composite layer of silicon nitride-silicon oxide-silicon nitride, or a composite layer of silicon oxide-silicon nitride-silicon oxide.

[0102] like Figure 1 As shown, in one possible implementation, one side of the first contact portion 401 contacts the insulating sidewall 25 in the first gate structure 20, and the other side of the first contact portion 401 contacts the insulating sidewall 25 of the second gate mechanism. Figure 2 As shown, in another possible embodiment, one side of the first contact portion 401 contacts the sidewall of the gate conductive layer 21 of the first gate structure 20, and the other side of the first contact portion 401 contacts the insulating sidewall 25 of the second gate structure. This arrangement allows the first contact portion 401 to fully utilize the space between the first gate structure 20 and the second gate structure, thus improving the conductivity of the first contact structure 40.

[0103] A second contact structure 60 is also provided on the substrate 10. The second contact structure 60 is located on the side of the first gate structure 20 opposite to the first contact structure 40, and the second contact structure 60 is also located on the side of the second gate structure opposite to the first contact structure 40. Similarly, the second contact portion 403 is in contact with and electrically connected to the conductive contact area on the substrate 10 to realize signal transmission between the second contact structure 60 and the substrate 10.

[0104] In this embodiment, the second contact structure 60 may include a third contact portion 61 and a fourth contact portion 62. The third contact portion 61 is connected to the fourth contact portion 62 and is located between the fourth contact portion 62 and the substrate 10. The third contact portion 61 is in contact with and electrically connected to the substrate 10, and the cross-sectional area of ​​the third contact portion 61 is larger than that of the fourth contact portion 62. Because the cross-sectional area of ​​the third contact portion 61 is larger than that of the fourth contact portion 62, the contact area between the third contact portion 61 and the substrate 10 can be effectively increased. As the integration level of semiconductor structures continues to increase, the contact area between the second contact structure 60 and the substrate 10 can be guaranteed, thereby reducing contact resistance, improving signal transmission efficiency and transmission stability, and enhancing the performance of the semiconductor structure.

[0105] Furthermore, the third contact portion 61 can be flush with the top surface of the gate conductive layer 21, and the fourth contact portion 62 can be flush with the top surface of the first gate structure 20. This arrangement improves the structural regularity of the second contact structure 60 and reduces the difficulty of fabricating the semiconductor structure.

[0106] Based on the above embodiments, referring to Figure 3 As shown, a second aspect of this application provides a method for fabricating a semiconductor structure, comprising:

[0107] S100, Provide a substrate, on which a first gate structure is disposed.

[0108] Reference Figure 4 and Figure 18 The substrate 10 provides the structural basis for the first gate structure 20. In this embodiment, the substrate 10, which has the first gate structure 20, also includes a second gate structure disposed on the substrate 10, the second gate structure being spaced apart from the first gate structure 20. Similar to the above embodiment, the substrate 10 also has multiple conductive contact regions, and the first gate structure 20 and the second gate structure can be located on the substrate 10 in the core region or on the substrate 10 in the peripheral region.

[0109] In this embodiment, refer to Figure 5 , Figure 6 as well as Figure 19 , Figure 20After providing the substrate 10, the process also includes forming conductive contact pads 12. In one specific implementation, a metal material layer needs to be formed on the conductive contact area. During the process, the metal material layer can react with the elemental silicon in the substrate 10 to form a metal silicide. This metal silicide has conductive properties and can form the conductive contact pads 12. Then, the metal material layer that has not reacted with the substrate 10 is removed. This "processing" process may include, but is not limited to, an annealing process. The material of the metal material layer here may include, but is not limited to, copper, cobalt, or tungsten. Correspondingly, the material of the formed conductive contact pads 12 may include copper silicides, cobalt silicides, and tungsten silicides.

[0110] S101, A first contact portion is formed on the substrate.

[0111] Reference Figure 7 To the diagram Figure 12 as well as Figures 21 to 24 In this embodiment, a first contact portion 401 is formed between the first gate structure 20 and the second gate structure, and the first contact portion 401 contacts the sidewalls of the first gate structure 20 and the second gate structure respectively. This is beneficial for the first contact portion 401 to make full use of the space between the first gate structure 20 and the second gate structure, and helps to improve the conductivity of the first contact structure 40.

[0112] Forming a first contact portion 401 on the substrate 10 includes forming a third contact portion 61 on the substrate 10, wherein the third contact portion 61 contacts the substrate 10 and is electrically connected to the substrate 10.

[0113] In this embodiment, the third contact portion 61 is located on the side of the first gate structure 20 opposite to the first contact structure 40, and the third contact portion 61 is also located on the side of the second gate structure opposite to the first contact structure 40, so that the third contact portion 61 can contact and be electrically connected with the conductive contact area on the substrate 10. Furthermore, the third contact portion 61 can be formed simultaneously with the first contact portion 401, and the third contact portion 61 and the first contact portion 401 are made of the same material, which helps to improve the fabrication efficiency of the semiconductor structure and reduce the fabrication difficulty.

[0114] S102, A second contact portion is formed on the top of the first contact portion; the second contact portion is connected to the first contact portion and together forms a first contact structure, and the first contact structure is electrically connected to the first gate structure and the substrate, and the cross-sectional area of ​​the first contact portion is greater than the cross-sectional area of ​​the second contact portion.

[0115] Reference Figures 13 to 17 as well as Figures 25 to 28The first contact structure 40 includes a first contact portion 401 and a second contact portion 403. The first contact portion 401 contacts and is electrically connected to a conductive contact area on the substrate 10 to achieve signal transmission between the first contact structure 40 and the substrate 10. Furthermore, the first contact structure 40 also contacts and is electrically connected to the gate conductive layer 21 of the first gate structure 20, enabling the first contact structure 40 to form an interconnecting contact between the first gate structure 20 and the substrate 10, achieving a single conductive function.

[0116] Since the first contact portion 401 is located between the first gate structure 20 and the second gate structure, the first contact structure 40 formed is also located between the first gate structure 20 and the second gate structure, and contacts the sidewalls of the first gate structure 20 and the second gate structure respectively.

[0117] In this embodiment, the cross-sectional area of ​​the first contact portion 401 is larger than that of the second contact portion 403, which can effectively increase the contact area between the first contact portion 401 and the substrate 10. Compared with related technologies, this application can ensure the contact area between the first contact structure 40 and the substrate 10 as the integration level of semiconductor structures continues to increase, thereby reducing contact resistance, improving signal transmission efficiency and transmission stability, and enhancing the performance of the semiconductor structure.

[0118] A second contact 403 is formed on top of the first contact 401, including: a fourth contact 62 is formed on top of the third contact 61. The third contact 61 and the fourth contact 62 are connected and together form a second contact structure 60, such that the second contact structure 60 is located on the side of the first gate structure 20 opposite to the first contact structure 40, and the second contact structure 60 is also located on the side of the second gate structure opposite to the first contact structure 40. Since the third contact structure is electrically connected to the substrate 10, the second contact structure 60 is in contact with and electrically connected to the conductive contact area on the substrate 10, thereby enabling signal transmission between the second contact structure 60 and the substrate 10. Furthermore, the fourth contact 62 can be formed simultaneously with the second contact 403, and the fourth contact 62 and the second contact 403 are made of the same material, which helps to improve the fabrication efficiency of the semiconductor structure and reduce the fabrication difficulty.

[0119] Furthermore, the cross-sectional area of ​​the first contact portion 401 can be larger than the cross-sectional area of ​​the second contact portion 403. Similar to the first contact structure 40, this can effectively increase the contact area between the third contact portion 61 and the substrate 10. As the integration level of the semiconductor structure continues to increase, the contact area between the second contact structure 60 and the substrate 10 can be guaranteed, thereby reducing contact resistance, improving signal transmission efficiency and transmission stability, and further enhancing the performance of the semiconductor structure.

[0120] The following reference Figures 4 to 17This section briefly introduces one possible implementation method in the fabrication of semiconductor structures:

[0121] like Figure 4 As shown, similar to the above embodiment, the first gate structure 20 may include a gate conductive layer 21, a gate isolation layer 24, and an insulating sidewall 25. The gate conductive layer 21 is disposed on the substrate 10. In this embodiment, a gate oxide layer 22 and a titanium nitride layer 23 may also be disposed between the gate conductive layer 21 and the substrate 10, wherein the titanium nitride layer 23 covers the substrate 10, and the gate oxide layer 22 covers the side of the titanium nitride layer 23 away from the substrate 10. The gate isolation layer 24 is located on the side of the gate conductive layer 21 away from the substrate 10, and the insulating sidewall 25 covers the sidewalls of the gate conductive layer 21 and the gate isolation layer 24. The gate conductive layer 21 may be made of a metal material, such as tungsten. The gate isolation layer 24 may be made of silicon nitride, for example, and the insulating sidewall 25 may be, for example, a composite layer of silicon nitride-silicon oxide-silicon nitride, or a composite layer of silicon oxide-silicon nitride-silicon oxide. The second gate structure is the same as the first gate structure 20, and will not be described again here.

[0122] Reference Figure 7 and Figure 8 After forming the conductive contact pad 12, a first contact portion 401 is formed on the substrate 10, including: forming a first dielectric layer 30 on the substrate 10, the first dielectric layer 30 having a first groove 31, a first gate structure 20 located in the first groove 31, the first gate structure 20 including a gate conductive layer 21, and the first dielectric layer 30 being flush with the top surface of the gate conductive layer 21.

[0123] Forming the first dielectric layer 30 on the substrate 10 includes: forming an intermediate dielectric layer on the substrate 10, the intermediate dielectric layer further covering the first gate structure 20 and the second gate structure. After forming the intermediate dielectric layer, a portion of the intermediate dielectric layer is removed to form the first dielectric layer 30, exposing the top surfaces of the first gate structure 20 and the second gate structure; here, "exposed" means that the top surfaces of the first gate structure 20 and the second gate structure are not covered by the intermediate dielectric layer. The formed first dielectric layer 30 is flush with the top surface of the gate conductive layer 21, which can improve the structural regularity of the semiconductor structure and reduce the fabrication difficulty. (Refer to...) Figure 9 , Figure 10 as well as Figure 11 After the first dielectric layer 30 is formed, a portion of the first dielectric layer 30 is removed to form the first groove 31, and the conductive contact pad 12, the first gate structure 20, and the second gate structure are all located within the first groove 31.

[0124] Reference Figure 12 and Figure 13The step of forming the first contact portion 401 on the substrate 10 after forming the first dielectric layer 30 further includes forming an isolation layer 41 on the bottom wall and sidewalls of the first groove 31. Exemplarily, while forming the isolation layer 41 on the bottom wall and sidewalls of the first groove 31, an isolation layer 41 is also formed on the sidewalls of the first gate structure 20 and the second gate structure. The isolation layer 41 can be made of, for example, titanium nitride, which has good corrosion resistance, conductivity, and intermetallic adhesion, so that the subsequently formed first contact portion 401 has good electrical connection performance with the substrate 10.

[0125] After forming the isolation layer 41, the step of forming the first contact portion 401 on the substrate 10 further includes filling the first groove 31 with conductive material 42 to form the first contact portion 401. Since the first dielectric layer 30 is flush with the top surface of the gate conductive layer 21, the filled conductive material 42 is also flush with the top surface of the gate conductive layer 21. The conductive material 42 located between the first gate structure 20 and the second gate structure, together with the isolation layer 41, constitutes the first contact portion 401. A third contact portion 61 is located in the portion of the first gate structure 20 opposite to the first contact portion 401 formed by the conductive material 42 and the isolation layer 41, and also in the portion of the second gate structure opposite to the first contact portion 401 formed by the conductive material 42 and the isolation layer 41. Through the above implementation steps, the first contact portion 401 and the third contact portion 61 can be formed simultaneously, which is beneficial to improving the fabrication efficiency of the semiconductor structure and reducing the fabrication difficulty.

[0126] In this embodiment, after the first contact portion 401 is formed, a second contact portion 403 is formed on the top of the first contact portion 401.

[0127] Reference Figure 14 The step of forming the second contact portion 403 further includes: forming a second dielectric layer 50 on the first dielectric layer 30, the second dielectric layer 50 being flush with the top surface of the first gate structure 20, the second dielectric layer 50 having a second groove 51, the bottom of the second groove 51 including the gate conductive layer 21 and the first contact portion 401. The fact that the second dielectric layer 50 is flush with the top surface of the first gate structure 20 can improve the structural regularity of the semiconductor structure and reduce the fabrication difficulty. (Refer to...) Figure 15 In one specific embodiment, a portion of the gate isolation layer 24, the insulating sidewall 25, and a portion of the second dielectric layer 50 of the first gate structure 20 are removed, exposing the top surface of the gate conductive layer 21 and the top surface of the first contact portion 401 to form a second groove 51. The material of the second dielectric layer 50 can be the same as that of the gate isolation layer 24, allowing for simultaneous removal of the gate isolation layer 24 and the second dielectric layer 50, further improving the fabrication efficiency of the semiconductor structure.

[0128] It is worth noting that while forming the second groove 51, a portion of the second dielectric layer 50 can be removed to form the third groove 52 and the fourth groove 53. The bottom of the third groove 52 includes the third contact portion 61, and the bottom of the fourth groove 53 includes the gate conductive layer 21 of the second gate structure.

[0129] Reference Figure 16 and Figure 17 After forming the second dielectric layer 50, the step of forming the second contact portion 403 further includes: forming a conductive structure 402 and a second contact portion 403 within the second groove 51, so that the conductive structure 402 and the second contact portion 403 are electrically connected. It is worth noting that the conductive structure 402 contacts the gate conductive layer 21, and the second contact portion 403 contacts the first contact portion 401. Furthermore, since the conductive structure 402 and the second contact portion 403 are electrically connected, the first contact portion 401 can be electrically connected to the gate conductive layer 21 through the second contact portion 403 and the conductive structure 402, thereby achieving an electrical connection between the first contact structure 40 and the first gate structure 20.

[0130] In one specific embodiment, forming a conductive structure 402 and a second contact 403 within the second groove 51 includes forming an isolation layer 41 at the bottom and sidewalls of the second groove 51. Similarly, the isolation layer 41 may be made of titanium nitride, for example, which has good corrosion resistance, conductivity, and intermetallic adhesion, so that the subsequently formed second contact 403 has good electrical connection performance with the first contact 401 and the gate conductive layer 21.

[0131] After forming the isolation layer 41, the step of forming the conductive structure 402 and the second contact portion 403 in the second groove 51 further includes filling the second groove 51 with conductive material 42 to form an integrally formed conductive structure 402 and second contact portion 403. Since the second dielectric layer 50 is flush with the top surface of the first gate structure 20, the filled conductive material 42 is also flush with the top surface of the first gate structure 20. The conductive material 42 located between the first gate structure 20 and the second gate structure, together with the isolation layer 41, constitutes the integrally formed conductive structure 402 and second contact portion 403, which helps to further reduce the manufacturing difficulty and improve the manufacturing efficiency of the semiconductor structure.

[0132] It is worth noting that while the isolation layer 41 is formed in the second groove 51, the bottom and sidewalls of the third groove 52 and the fourth groove 53 are also formed with isolation layers 41. Simultaneously with the filling of the second groove 51 with conductive material 42, conductive material 42 is also filled in the third groove 52 and the fourth groove 53. This results in the fourth contact 62 formed by the conductive material 42 and the isolation layer 41 on the first gate structure 20 away from the first contact 401, the fourth contact 62 formed by the conductive material 42 and the isolation layer 41 on the second gate structure away from the first contact 401, and the fifth contact 70 formed by the conductive material 42 and the isolation layer 41 at the end of the second gate structure away from the substrate 10. Through the above implementation steps, the second contact 403 and the fourth contact 62 can be formed simultaneously, which is beneficial for further improving the fabrication efficiency of the semiconductor structure and reducing the fabrication difficulty.

[0133] The following reference Figures 18 to 28 This section briefly introduces another possible implementation method in the fabrication of semiconductor structures:

[0134] Reference Figure 18 The step of providing a substrate 10, on which a first gate structure 20 is disposed, includes: the first gate structure 20 includes a gate conductive layer 21 and a gate isolation layer 24 covering the top surface of the gate conductive layer 21, one side of the gate conductive layer 21 is covered by an insulating sidewall 25, and the other side of the gate conductive layer 21 facing away from the insulating sidewall 25 is exposed. Here, "exposed" means that the other side of the gate conductive layer 21 and the gate isolation layer 24 is not covered by the insulating sidewall 25.

[0135] Reference Figure 19 and Figure 20 The process includes forming conductive contact pads 12 on the substrate 10, and also forming conductive contact pads 12 on the sidewalls of a portion of the gate conductive layer 21 and on the substrate 10. In the first gate structure 20, the gate conductive layer 21 may include a first conductive layer 212 and a second conductive layer 211. The first conductive layer 212 covers the side of the gate oxide layer 22 away from the substrate 10, and the second conductive layer 211 covers the first conductive layer 212. The material of the second conductive layer 211 may include conductive metals such as titanium or tungsten, and the material of the first conductive layer 212 may include polysilicon, for example. During the processing of the conductive contact pads 12, the metal material layer may react with the elemental silicon in the first conductive layer 212, so that the conductive contact pads 12 can also cover the sidewalls of the first conductive layer 212, thereby further improving the conductivity of the gate conductive layer 21.

[0136] Reference Figure 21 and Figure 22After providing the substrate 10, forming the first contact portion 401 on the substrate 10 includes: forming a first dielectric layer 30 on the substrate 10, the first dielectric layer 30 having a first groove 31, the first gate structure 20 being located within the first groove 31, and the first dielectric layer 30 being flush with the top surface of the gate conductive layer 21. The steps of forming the first dielectric layer 30 and the first groove 31 can be the same as in the above embodiment, and will not be repeated here. The fact that the formed first dielectric layer 30 is flush with the top surface of the gate conductive layer 21 can improve the structural regularity of the semiconductor structure and reduce the fabrication difficulty.

[0137] Reference Figure 23 and Figure 24 After forming the first dielectric layer 30 on the substrate 10, the step of forming the first contact portion 401 on the substrate 10 further includes forming an isolation layer 41 on the bottom wall and side wall of the first groove 31. Similarly, the material of the isolation layer 41 may be, for example, titanium nitride, which has good corrosion resistance, conductivity and intermetallic adhesion, so that the subsequently formed first contact portion 401 has good electrical connection performance with the substrate 10.

[0138] After forming the isolation layer 41 on the bottom and sidewalls of the first groove 31, the step of forming the first contact portion 401 on the substrate 10 further includes: filling the first groove 31 with conductive material 42 to form the first contact portion 401, wherein the first contact portion 401 covers part of the sidewalls of the gate conductive layer 21 and the upper surface of the conductive contact pad 12. Since the first dielectric layer 30 is flush with the top surface of the gate conductive layer 21, the filled conductive material 42 is also flush with the top surface of the gate conductive layer 21. The conductive material 42 covers and contacts the sidewalls of the second conductive layer 211 and the upper surface of the conductive contact pad 12, which helps to further improve the conductivity between the conductive material 42 and the gate conductive layer 21, thereby achieving an electrical connection between the first contact portion 401 and the first gate structure 20.

[0139] Furthermore, the conductive material 42 located between the first gate structure 20 and the second gate structure, together with the isolation layer 41, constitutes the first contact portion 401. A third contact portion 61 is located on the portion of the first gate structure 20 opposite to the first contact portion 401 formed by the conductive material 42 and the isolation layer 41, and also on the portion of the second gate structure opposite to the first contact portion 401 formed by the conductive material 42 and the isolation layer 41. Through the above implementation steps, the first contact portion 401 and the third contact portion 61 can be formed simultaneously, which is beneficial to improving the fabrication efficiency of the semiconductor structure and reducing the fabrication difficulty.

[0140] Reference Figures 25 to 28 After the first contact portion 401 is formed on the substrate 10, the method further includes forming a second contact portion 403 on top of the first contact portion 401.

[0141] like Figure 25 and Figure 26 The step of forming the second contact portion 403 further includes: forming a second dielectric layer 50 on the first dielectric layer 30, the second dielectric layer 50 being flush with the top surface of the first gate structure 20, and the second dielectric layer 50 having a second groove 51. The fact that the second dielectric layer 50 is flush with the top surface of the first gate structure 20 can improve the structural regularity of the semiconductor structure and reduce the fabrication difficulty. The bottom of the second groove 51 includes the gate conductive layer 21 and the top surface of the first contact portion 401.

[0142] It is worth noting that while forming the second groove 51, a portion of the second dielectric layer 50 can be removed to form the third groove 52 and the fourth groove 53. The bottom of the third groove 52 includes the third contact portion 61, and the bottom of the fourth groove 53 includes the gate conductive layer 21 of the second gate structure.

[0143] Reference Figure 27 and Figure 28 After forming the second dielectric layer 50, the step of forming the second contact portion 403 further includes forming an isolation layer 41 on the bottom wall and side wall of the second groove 51. Similarly, the material of the isolation layer 41 can be, for example, titanium nitride, which has good corrosion resistance, conductivity and intermetallic adhesion, so that the subsequently formed second contact portion 403 has good electrical connection performance with the first contact portion 401 and the gate conductive layer 21.

[0144] After forming the isolation layer 41 on the bottom wall and side wall of the second groove 51, the step of forming the second contact portion 403 further includes filling the second groove 51 with conductive material 42 to form the second contact portion 403. The conductive material 42 located between the first gate structure 20 and the second gate structure, together with the isolation layer 41, constitutes the second contact portion 403. Since the second dielectric layer 50 is flush with the top surface of the first gate structure 20, the second contact portion 403 is also flush with the top surface of the first gate structure 20, which is beneficial to further improve the regularity of the semiconductor structure.

[0145] It is worth noting that while the isolation layer 41 is formed in the second groove 51, the bottom and sidewalls of the third groove 52 and the fourth groove 53 are also formed with isolation layers 41. Simultaneously with the filling of the second groove 51 with conductive material 42, conductive material 42 is also filled in the third groove 52 and the fourth groove 53. This results in the fourth contact 62 formed by the conductive material 42 and the isolation layer 41 on the first gate structure 20 away from the first contact 401, the fourth contact 62 formed by the conductive material 42 and the isolation layer 41 on the second gate structure away from the first contact 401, and the fifth contact 70 formed by the conductive material 42 and the isolation layer 41 at the end of the second gate structure away from the substrate 10. Through the above implementation steps, the second contact 403 and the fourth contact 62 can be formed simultaneously, which is beneficial for further improving the fabrication efficiency of the semiconductor structure and reducing the fabrication difficulty.

[0146] In the above description, it should be understood that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "multiple" means two or more, unless otherwise precisely specified.

[0147] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, The device includes a substrate on which a first gate structure and a first contact structure are disposed. The first contact structure includes a first contact portion and a second contact portion. The first contact portion is connected to the second contact portion and is located between the second contact portion and the substrate. The first contact structure is electrically connected to the first gate structure and the substrate, and the cross-sectional area of ​​the first contact portion is larger than the cross-sectional area of ​​the second contact portion; The first gate structure includes a gate conductive layer. A conductive structure is provided at one end of the first gate structure away from the substrate. The conductive structure is in contact with the gate conductive layer and is electrically connected to the second contact portion. The conductive structure and the second contact portion are located in the same plane.

2. The semiconductor structure according to claim 1, characterized in that, The conductive structure has an isolation layer between itself and the bottom and sidewalls of the second contact portion.

3. The semiconductor structure according to claim 1, characterized in that, The first contact portion contacts the sidewall of the gate conductive layer, and the first contact portion is flush with the top surface of the gate conductive layer.

4. The semiconductor structure according to claim 3, characterized in that, The sidewall portion of the gate conductive layer covers the conductive contact pad, and the first contact portion contacts the upper surface of the conductive contact pad.

5. The semiconductor structure according to claim 4, characterized in that, The bottom and sidewalls of the second contact portion have an isolation layer.

6. The semiconductor structure according to any one of claims 2 or 5, characterized in that, The bottom and sidewalls of the first contact portion have the isolation layer.

7. The semiconductor structure according to any one of claims 2 or 5, characterized in that, The substrate is further provided with a first dielectric layer and a second dielectric layer, the first dielectric layer being located between the second dielectric layer and the substrate, the first dielectric layer being flush with the top surface of the gate conductive layer, and the second dielectric layer being flush with the top surface of the first gate structure.

8. The semiconductor structure according to any one of claims 2 or 5, characterized in that, The substrate is further provided with a second contact structure and a second gate structure. The second gate structure is spaced apart from the first gate structure. The first contact structure is located between the first gate structure and the second gate structure and contacts the sidewalls of the first gate structure and the second gate structure, respectively. The second contact structure is located on the side of the first gate structure opposite to the first contact structure. The second contact structure is also located on the side of the second gate structure opposite to the first contact structure.

9. The semiconductor structure according to claim 8, characterized in that, The second contact structure includes a third contact portion and a fourth contact portion. The third contact portion is connected to the fourth contact portion and is located between the fourth contact portion and the substrate. The third contact portion is in contact with and electrically connected to the substrate. The cross-sectional area of ​​the third contact portion is greater than that of the fourth contact portion.

10. The semiconductor structure according to claim 4, characterized in that, The conductive contact pad is a metal silicide.

11. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a first gate structure is disposed; A second gate structure is also disposed on the substrate, the second gate structure being spaced apart from the first gate structure; a first contact portion is formed on the substrate. A second contact portion is formed on top of the first contact portion; The first contact portion is located between the first gate structure and the second gate structure, and contacts the sidewalls of the first gate structure and the second gate structure, respectively. The second contact portion is located on the side of the first gate structure opposite to the first contact portion, and the second contact portion is also located on the side of the second gate structure opposite to the first contact portion; The second contact portion is connected to the first contact portion and together they form a first contact structure. The first contact structure is electrically connected to the first gate structure and the substrate. The cross-sectional area of ​​the first contact portion is larger than the cross-sectional area of ​​the second contact portion.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Forming the first contact portion on the substrate includes: A first dielectric layer is formed on the substrate. The first dielectric layer has a first groove. The first gate structure is located in the first groove. The first gate structure includes a gate conductive layer. The first dielectric layer is flush with the top surface of the gate conductive layer. An isolation layer is formed on the bottom wall and side wall of the first groove; The first groove is filled with conductive material to form the first contact portion.

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, A second contact portion is formed on top of the first contact portion, including: A second dielectric layer is formed on the first dielectric layer, the second dielectric layer being flush with the top surface of the first gate structure, the second dielectric layer having a second groove, the bottom of the second groove including the gate conductive layer and the first contact portion; A conductive structure and a second contact portion are formed within the second groove to electrically connect the conductive structure and the second contact portion.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, A conductive structure and a second contact portion are formed within the second groove, including: The isolation layer is formed on the bottom and sidewalls of the second groove; The second groove is filled with conductive material to form the integrally molded conductive structure and the second contact portion.

15. The method for fabricating a semiconductor structure according to claim 11, characterized in that, A substrate is provided, wherein a first gate structure is disposed on the substrate, comprising: The first gate structure includes a gate conductive layer and a gate isolation layer covering the top surface of the gate conductive layer. One side of the gate conductive layer is covered with an insulating sidewall, and the other side of the gate conductive layer away from the insulating sidewall is exposed. Conductive contact pads are formed on the sidewalls of a portion of the gate conductive layer and on the substrate.

16. The method for fabricating a semiconductor structure according to claim 15, characterized in that, Forming the first contact portion on the substrate includes: A first dielectric layer is formed on the substrate, the first dielectric layer has a first groove, the first gate structure is located in the first groove, and the first dielectric layer is flush with the top surface of the gate conductive layer. An isolation layer is formed on the bottom wall and side wall of the first groove; The first groove is filled with conductive material to form the first contact portion, which covers part of the sidewall of the gate conductive layer and the upper surface of the conductive contact pad.

17. The method for fabricating a semiconductor structure according to claim 16, characterized in that, A second contact portion is formed on top of the first contact portion, including: A second dielectric layer is formed on the first dielectric layer, the second dielectric layer being flush with the top surface of the first gate structure, and the second dielectric layer having a second groove; The isolation layer is formed on the bottom wall and side wall of the second groove; The conductive material is filled into the second groove to form the second contact portion.

18. The method for fabricating a semiconductor structure according to claim 17, characterized in that, The conductive contact pad is a metal silicide.

19. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Forming the first contact portion on the substrate includes: A third contact portion is formed on the substrate, the third contact portion being in contact with and electrically connected to the substrate; A second contact portion is formed on top of the first contact portion, including: A fourth contact portion is formed on top of the third contact portion. The third contact portion and the fourth contact portion are connected and together form a second contact structure. The second contact structure is located on the side of the first gate structure opposite to the first contact structure. The second contact structure is also located on the side of the second gate structure opposite to the first contact structure. The cross-sectional area of ​​the third contact portion is larger than the cross-sectional area of ​​the fourth contact portion.

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