Semiconductor device with reduced source-drain resistance and method of fabrication

Abstract

The present disclosure provides a semiconductor device and a manufacturing method for reducing source-drain resistance, which includes a substrate and a plurality of three-dimensional semiconductor device arrays; the three-dimensional semiconductor device arrays are arranged on the substrate and separated by isolation grooves; each three-dimensional semiconductor device array includes a plurality of device layers in the vertical direction, and each device layer includes a stack of a source / drain layer, a channel layer and the source / drain layer, and the end surface of the source / drain layer adjacent to the isolation groove is metallized; the three-dimensional semiconductor device array further includes a plurality of gate stacks arranged in an array, the gate stacks pass through each device layer in the vertical direction and include a gate conductor and a gate dielectric layer arranged between the gate conductor and the device layer, and a device cell is defined at the intersection of the gate stack and the device layer. By forming a metal silicide on the sidewall of the semiconductor device, the device source-drain resistance can be reduced, the device on-current can be improved, and the consistency of the devices in the array can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and method for reducing source-drain resistance. Background Technology

[0002] With the development of the integrated circuit industry, three-dimensional semiconductor devices have become a popular research direction due to their superior integration. The basic structure of a MOS transistor consists of a source / drain / channel and a gate dielectric and gate above the channel. One method for three-dimensionalizing the device is to vertically stack the source / channel / drain terminals, and create space by drilling holes or forming trenches to form the gate dielectric and gate.

[0003] However, vertically stacking devices also makes it difficult to bring out the central device in a three-dimensional device array (e.g., the patent with publication number CN112909011A). Heavily doped silicon has high resistivity, and connecting the central source and drain of the array through heavily doped silicon connections faces a large source-drain resistance problem, which further leads to a decrease in the consistency of device characteristics in the array, and may even cause errors during use. Summary of the Invention

[0004] In view of the above problems, the present invention provides a semiconductor device and a method for fabricating it to reduce source-drain resistance, so as to solve the above technical problems.

[0005] One aspect of this disclosure provides a semiconductor device for reducing source-drain resistance, comprising: a substrate and a plurality of three-dimensional semiconductor device arrays; the three-dimensional semiconductor device arrays are disposed on the substrate and separated from each of the three-dimensional semiconductor device arrays by isolation trenches; each of the three-dimensional semiconductor device arrays includes a plurality of device layers in a vertical direction, each device layer including a source / drain layer, a channel layer and a stack of source / drain layers, the end face of the source / drain layer adjacent to the isolation trench being metallized to form a metal silicide; the three-dimensional semiconductor device array further includes a plurality of gate stacks arranged in an array, the gate stacks extending vertically through each of the device layers, including gate conductors and gate dielectric layers disposed between the gate conductors and the device layers, defining device cells at the intersections of the gate stacks and the device layers.

[0006] According to embodiments of this disclosure, the source / drain layer and channel layer in each of the device layers extend along the extension direction of the isolation trench, forming a stepped contact area in each of the source / drain layers.

[0007] According to an embodiment of this disclosure, silicon oxide is deposited on the three-dimensional semiconductor device array to form a dielectric isolation layer, covering the contact area and upper surface of each of the three-dimensional semiconductor device arrays and each of the isolation trenches, and the upper surface of the dielectric isolation layer is planarized.

[0008] According to an embodiment of this disclosure, a plurality of contact holes are vertically etched downward on the upper surface of the dielectric isolation layer, each of the contact holes extending to a contact area of ​​a source / drain layer.

[0009] According to embodiments of this disclosure, the lower source / drain layer in the upper device layer is the same source / drain layer as the upper source / drain layer in the adjacent lower device layer.

[0010] According to embodiments of this disclosure, a silicon oxide isolation layer is provided between the two source / drain layers of each device layer in the three-dimensional semiconductor device array and at the bottom of the three-dimensional semiconductor device array; the bottom of the gate stack is located in the silicon oxide isolation layer at the bottom of the three-dimensional semiconductor device array; the channel layer is disposed between the gate dielectric layer and the structure formed by the two source / drain layers and the silicon oxide isolation layer.

[0011] According to embodiments of this disclosure, the source / drain layer and the channel layer are made of doped polycrystalline silicon material.

[0012] According to an embodiment of this disclosure, the upper surface of the substrate is provided with a germanium-silicon doped layer; the bottom of the gate stack is located in the germanium-silicon doped layer; the source / drain layer, the channel layer, and the source / drain layer in the device layer are stacked sequentially from bottom to top; the bottom of the isolation trench is located in the germanium-silicon doped layer; the end faces of the channel layer and the germanium-silicon doped layer adjacent to the isolation trench form a dielectric inner wall.

[0013] According to embodiments of this disclosure, the source / drain layer is an N-doped silicon material, and the channel layer is a P-doped germanium-silicon material.

[0014] This disclosure also provides a fabrication method comprising: growing a plurality of device layers on a substrate, each device layer including a source / drain layer, a channel layer, and a stack of source / drain layers; forming a plurality of gate vias through each device layer in a vertical direction perpendicular to the substrate, forming a gate stack in the gate vias, the gate stack being arranged in an array, including a gate conductor and a gate dielectric layer disposed between the gate conductor and the device layers, defining device cells at the intersection of the gate stack and the device layers; etching the device layers in a vertical direction perpendicular to the substrate to form isolation trenches and three-dimensional semiconductor device arrays separated by the isolation trenches; and metallizing the end faces of the source / drain layers in each of the three-dimensional semiconductor device arrays adjacent to the isolation trenches to form metal silicides.

[0015] The above-described at least one technical solution adopted in the embodiments of this disclosure can achieve the following beneficial effects:

[0016] This disclosure provides a semiconductor device for reducing source-drain resistance by using a sidewall metal silicide method to reduce the device's source-drain resistance, thereby improving the device's on-current and the consistency of device characteristics in the array. Attached Figure Description

[0017] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1A The illustration schematically shows a top view of a semiconductor device for reducing source-drain resistance according to an embodiment of the present disclosure;

[0019] Figure 1B The illustration schematically shows a cross-sectional view along the AA' direction of a semiconductor device for reducing source-drain resistance according to an embodiment of the present disclosure;

[0020] Figure 2A The schematic diagram shows a cross-sectional view of the device layer stack of a semiconductor device for reducing source-drain resistance according to a second embodiment of the present disclosure;

[0021] Figure 2B An arrayed gate stack top view of a semiconductor device for reducing source-drain resistance according to a second embodiment of the present disclosure is shown schematically.

[0022] Figure 2C The illustration schematically shows a cross-sectional view along the BB' direction of an etched gate via in a semiconductor device for reducing source-drain resistance according to a second embodiment of the present disclosure.

[0023] Figure 2D The illustration schematically shows a BB'-direction cross-sectional view of a semiconductor device for reducing source-drain resistance and forming a gate stack according to a second embodiment of the present disclosure.

[0024] Figure 2E The schematic diagram shows a top view of an etched isolation trench in a semiconductor device for reducing source-drain resistance according to a second embodiment of the present disclosure;

[0025] Figure 2F A schematic cross-sectional view along the AA' direction of a semiconductor device for reducing source-drain resistance according to a second embodiment of this disclosure is shown.

[0026] Figure 2G This schematically illustrates a side metallization diagram of a semiconductor device for reducing source-drain resistance according to a second embodiment of the present disclosure;

[0027] Figure 2H The diagram schematically illustrates a cross-sectional view of the filling dielectric of a semiconductor device for reducing source-drain resistance according to a second embodiment of the present disclosure;

[0028] Figure 2I The schematic diagram shows a top view of a semiconductor device for reducing source-drain resistance according to a second embodiment of the present disclosure;

[0029] Figure 2JThe schematic diagram shows a cross-sectional view of the contact region CC' direction of a semiconductor device for reducing source-drain resistance according to a second embodiment of the present disclosure;

[0030] Figure 2K This schematically illustrates a contact hole diagram of a semiconductor device for reducing source-drain resistance according to a second embodiment of the present disclosure;

[0031] Figure 3A The schematic diagram shows a cross-sectional view of the device layer stack of a semiconductor device for reducing source-drain resistance according to a third embodiment of the present disclosure;

[0032] Figure 3B The schematic diagram shows a top view of an arrayed gate stack of a semiconductor device for reducing source-drain resistance according to a third embodiment of the present disclosure;

[0033] Figure 3C The illustration schematically shows a BB'-direction cross-sectional view of an etched gate via in a semiconductor device for reducing source-drain resistance according to a third embodiment of the present disclosure;

[0034] Figure 3D The illustration schematically shows a BB'-direction cross-sectional view of a semiconductor device for reducing source-drain resistance and forming a gate stack according to a third embodiment of the present disclosure.

[0035] Figure 3E The schematic diagram shows a top view of an etched isolation trench in a semiconductor device for reducing source-drain resistance according to a third embodiment of the present disclosure;

[0036] Figure 3F The illustration schematically shows a cross-sectional view along the AA' direction of a semiconductor device for reducing source-drain resistance after etching an isolation trench, according to a third embodiment of this disclosure.

[0037] Figure 3G This schematically illustrates a semiconductor device etching source / drain layer for reducing source / drain resistance according to a third embodiment of this disclosure;

[0038] Figure 3H This schematically illustrates a semiconductor device forming a dielectric inner wall to reduce source-drain resistance according to a third embodiment of the present disclosure.

[0039] Figure 3I This schematically illustrates a side metallization of a semiconductor device for reducing source-drain resistance according to a third embodiment of the present disclosure;

[0040] Figure 3J The diagram schematically illustrates a cross-sectional view of the filling dielectric of a semiconductor device for reducing source-drain resistance according to a third embodiment of the present disclosure;

[0041] Figure 3KThe diagram schematically illustrates a top view of a semiconductor device for reducing source-drain resistance according to a third embodiment of the present disclosure;

[0042] Figure 3L The schematic diagram shows a cross-sectional view of the contact region CC' direction of a semiconductor device for reducing source-drain resistance according to a third embodiment of the present disclosure;

[0043] Figure 3M The diagram illustrates a contact hole of a semiconductor device for reducing source-drain resistance according to a third embodiment of this disclosure.

[0044] Explanation of reference numerals in the attached figures:

[0045] 1-Substrate; 2-Three-dimensional semiconductor device array; 21-Silicon oxide isolation layer; 22-Source / drain layer; 23-Channel layer; 24-Doped germanium-silicon layer; D1-Device layer; 3-Isolation trench; 4-Gate stack; 41-Gate conductor; 42-Gate dielectric layer; 5-Silicide metallization; 6-Dielectric isolation layer; 7-Contact hole; 8-Dielectric inner wall; 81-Dielectric inner wall groove. Detailed Implementation

[0046] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0048] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0049] Figure 1A The illustration shows a top view of a semiconductor device for reducing source-drain resistance according to an embodiment of the present disclosure.

[0050] like Figure 1AAs shown in the embodiments of this disclosure, a semiconductor device for reducing source-drain resistance includes a substrate 1 and multiple three-dimensional semiconductor device arrays 2. The three-dimensional semiconductor device arrays 2 are disposed on the substrate 1, and each three-dimensional semiconductor device array 2 is separated from the others by isolation trenches 3. The isolation trenches 3 separate the devices in the array, which facilitates their extraction and also helps to reduce the influence between the devices.

[0051] Figure 1B The diagram schematically illustrates a cross-sectional view along the AA' direction of a semiconductor device for reducing source-drain resistance according to an embodiment of the present disclosure.

[0052] like Figure 1B As shown in this embodiment, each three-dimensional semiconductor device array 2 includes multiple device layers in the vertical direction. Each device layer includes a stack of a lower source / drain layer, a channel layer, and an upper source / drain layer. The end faces of the source / drain layers adjacent to the isolation trench 3 are metallized to form metal silicide 5. Furthermore, for the sake of simplicity in the manufacturing process, the bottom of the isolation trench 3 is also metallized during the metallization of the end faces of the source / drain layers.

[0053] refer to Figure 1A and Figure 1B The three-dimensional semiconductor device array 2 also includes multiple gate stacks 4 arranged in an array. The gate stacks 4 extend vertically through each device layer and include gate conductors 41 and gate dielectric layers 42 disposed between the gate conductors 41 and the device layers. Device cells are defined where the gate stacks 4 intersect with the device layers. Programming and erasing can be controlled by applying a voltage to the gate stacks 4. At both ends of each three-dimensional semiconductor device array 2, the source / drain layers and channel layers 23 in each device layer extend along the extension direction of the isolation trench 3, forming a stepped contact area in each source / drain layer for forming the lead-out structure of each layer (source / drain layer and body layer).

[0054] Compared with existing vertically stacked semiconductor devices, the semiconductor device provided in this disclosure has a metallized end face adjacent to the source / drain layer and the isolation trench 3. The resistivity of the metallized structure is much lower than that of silicon. Through feasible formation methods, the source-drain resistance problem can be effectively solved.

[0055] A second embodiment of this disclosure provides a semiconductor device for reducing source-drain resistance. Figures 2A-2K The schematic diagram illustrates the specific structure of the semiconductor device and the fabrication process of the semiconductor device.

[0056] like Figure 2AAs shown, in the second embodiment of this disclosure, the substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. Multiple device layers D1 are grown on the substrate 1. In these device layers D1, the source / drain layers 22 are doped polysilicon, and a silicon oxide layer is located between the upper and lower source / drain layers 22. The channel layer 23 will be formed in subsequent processes. The lower source / drain layer 22 of the upper device layer and the upper source / drain layer 22 of the adjacent lower device layer can be the same source / drain layer. By sharing a single source / drain layer, the device size can be reduced and the fabrication process simplified. Silicon oxide isolation layers are provided at the top of the top device layer and at the bottom of the three-dimensional semiconductor device array 2. Figure 2A This illustration only shows a three-layer device stacking pattern. In practice, the stacking can be infinitely increased until the process technology can no longer support it (one layer of device is defined by two adjacent layers of polysilicon). The device fabricated in this example can be an NMOS device; this method can also be used to form PMOS or NOR flash. The thickness of the doped polysilicon can be referenced as 10nm-500nm, and the thickness of the silicon oxide can be referenced as 5nm-500nm.

[0057] like Figure 2B As shown, multiple gate vias are formed through each device layer in a vertical direction perpendicular to the substrate 1. These gate vias can be formed by etching the layers on the substrate 1 using photoresist as an etching mask and anisotropic etching such as reactive ion etching (RIE). Gate stacks 4 are formed within the gate vias. These gate stacks 4 are arranged in an array and include gate conductors 41 and gate dielectric layers 42 disposed between the gate conductors 41 and the device layers. Device cells are defined at the intersections of the gate stacks 4 and the device layers.

[0058] Figure 2C As shown Figure 2B The BB' direction cross-sectional view of the gate stack 4 array shown shows that multiple gate holes are formed in the vertical direction through each device layer, and the etching of the gate holes stops when they reach the bottom layer of silicon oxide.

[0059] like Figure 2D As shown, polysilicon is deposited in the gate via, and in-situ doping or implantation can be used to adjust the channel impurity concentration. A channel layer 23 is formed on the sidewalls and bottom of the gate via, i.e., the channel layer 23 is located between the gate dielectric layer 42 and the structure formed by the upper source / drain layer 22, the silicon oxide isolation layer, and the lower source / drain layer 22. For ease of fabrication, the channel layer 23 is also grown between the bottom of the gate dielectric layer 42 and the silicon oxide isolation layer at the bottom of the three-dimensional semiconductor device array 2 during the growth process. Then, the gate dielectric layer 42 is deposited in the gate via, and finally the gate conductor 41 is deposited, and the top of the device is planarized. The bottom of the gate stack 4 is located in the silicon oxide isolation layer at the bottom of the three-dimensional semiconductor device array 2.

[0060] like Figure 2E As shown, after the gate stack 4 array is fabricated, the device layer is etched in the vertical direction perpendicular to the substrate 1 to form an isolation trench 3 and multiple three-dimensional semiconductor device arrays 2 separated by the isolation trench 3, thus forming multiple three-dimensional semiconductor device arrays 2. Figure 2F The diagram schematically shows a cross-sectional view along the AA' direction after etching the isolation trench 3. It can be seen that the etching of the isolation trench 3 stops immediately upon reaching the substrate 1, separating each three-dimensional semiconductor device array 2, which facilitates extraction and reduces the influence between devices.

[0061] like Figure 2G As shown, metal (such as nickel or platinum) is filled into the trench using methods such as ALD or PVD. After annealing to form metal silicide 5, the metal is removed by etching. In this process, the end faces adjacent to the isolation trench 3 in each three-dimensional semiconductor device array 2 are metallized. Further, as... Figure 2H As shown, silicon oxide is deposited on the wafer to form a dielectric isolation layer 6, which covers the contact area and upper surface of each three-dimensional semiconductor device array 2 and each isolation trench 3. The upper surface of the dielectric isolation layer 6 is planarized. Figure 2I A top view is shown after the dielectric isolation layer 6 is filled, showing the contact areas of the various three-dimensional semiconductor device arrays 2.

[0062] Figure 2H A schematic cross-sectional view along the CC' direction is shown, illustrating the fabrication of the contact areas. Device layers at both ends of each three-dimensional semiconductor device array 2 are etched downwards from the dielectric isolation layer 6, forming a stepped contact area in each source / drain layer 22. (As shown...) Figure 2K As shown, after filling the contact area with silicon oxide and planarizing it, multiple contact holes 7 are etched vertically downwards. Each contact hole 7 extends to the contact area of ​​a source / drain layer 22, thus completing the semiconductor device that reduces source / drain resistance.

[0063] The third embodiment of this disclosure provides another semiconductor device for reducing source-drain resistance. Figures 3A-3M The schematic diagram illustrates the specific structure of the semiconductor device and the fabrication process of the semiconductor device.

[0064] like Figure 3AAs shown, in the third embodiment of this disclosure, multiple device layers are grown on substrate 1. In these device layers, the source / drain layer 22 is made of heavily doped silicon, and the channel layer 23 is made of doped germanium-silicon. The lower source / drain layer 22, the channel layer 23, and the upper source / drain layer 22 are stacked sequentially from bottom to top. The lower source / drain layer 22 of the upper device layer and the upper source / drain layer 22 of the adjacent lower device layer can be the same source / drain layer. By sharing a single source / drain layer, the device size can be reduced and the fabrication process simplified. A silicon oxide isolation layer is provided at the top of the top device layer in the three-dimensional semiconductor device array 2, and a lightly doped germanium-silicon layer 24 is provided on the upper surface of substrate 1. Figure 3A This illustration only shows a three-layer device stacking pattern. In practice, the stacking can be infinitely increased until the process technology can no longer support it (one layer of device is defined by two adjacent layers of polysilicon). The device fabricated in this example can be an NMOS device; this method can also be used to form PMOS or NOR flash. The thickness of the doped polysilicon can be referenced as 10nm-500nm, and the thickness of the silicon oxide can be referenced as 5nm-500nm.

[0065] like Figure 3B As shown, multiple gate holes are formed through each device layer in a vertical direction perpendicular to the substrate 1, and a gate stack 4 is formed in the gate holes. The gate stack 4 is arranged in an array and includes a gate conductor 41 and a gate dielectric layer 42 disposed between the gate conductor 41 and the device layer. The device cell is defined at the intersection of the gate stack 4 and the device layer.

[0066] Figure 3C As shown Figure 3B The BB' direction cross-sectional view of the gate stack 4 array shown shows that multiple gate holes are formed in the vertical direction through each device layer. The etching of the gate holes stops when it reaches the bottommost doped germanium-silicon layer 24.

[0067] like Figure 3D As shown, a gate dielectric layer 42 is deposited in the gate via, followed by a gate conductor 41, and the top of the device is planarized. The bottom of the gate stack 4 is located in a doped germanium-silicon layer 24 at the bottom of the three-dimensional semiconductor device array 2.

[0068] like Figure 3E As shown, after the gate stack 4 array is fabricated, the device layer is etched in the vertical direction perpendicular to the substrate 1 to form an isolation trench 3 and multiple three-dimensional semiconductor device arrays 2 separated by the isolation trench 3, thus forming multiple three-dimensional semiconductor device arrays 2. Figure 3F A schematic cross-sectional view along the AA' direction after etching the isolation trench 3 is shown. It can be seen that the etching of the isolation trench 3 stops at the germanium-silicon doped layer 24.

[0069] like Figure 3G As shown, a certain depth is selectively etched into the inner sidewall groove 81 of the medium on the sidewall adjacent to the channel layer 23 and the isolation groove 3; as Figure 3HAs shown, a dielectric material is deposited on both sides of the channel layer 23, and anisotropic etching is performed to form dielectric inner sidewalls 8. The material of the dielectric inner sidewalls 8 may include silicon nitride, etc.

[0070] like Figure 3I As shown, metal (such as nickel or platinum) is filled into the trench using methods such as ALD or PVD. After annealing to form metal silicide 5, the metal is removed by etching. In this process, the end faces adjacent to the isolation trench 3 in each three-dimensional semiconductor device array 2 are metallized. Further, as... Figure 3J As shown, a dielectric isolation layer 6 is formed by filling silicon oxide on the substrate 1, covering the contact area and upper surface of each three-dimensional semiconductor device array 2 and each isolation trench 3, and the upper surface of the dielectric isolation layer 6 is planarized. Figure 3K A top view is shown after the dielectric isolation layer 6 is filled, showing the contact areas of the various three-dimensional semiconductor device arrays 2.

[0071] Figure 3L A schematic cross-sectional view along the CC' direction is shown, illustrating the fabrication of the contact areas. Device layers at both ends of each three-dimensional semiconductor device array 2 are etched downwards from the dielectric isolation layer 6, forming a stepped contact area in each source / drain layer 22. (As shown...) Figure 3M As shown, after filling the contact area with silicon oxide and planarizing it, multiple contact holes 7 are etched vertically downwards. Each contact hole 7 extends to the contact area of ​​a source / drain layer 22, thus completing the semiconductor device that reduces source / drain resistance.

[0072] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0073] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A semiconductor device for reducing source-drain resistance, characterized in that, include: Substrate (1) and multiple three-dimensional semiconductor device arrays (2); The three-dimensional semiconductor device array (2) is disposed on the substrate (1), and each of the three-dimensional semiconductor device arrays (2) is separated by an isolation trench (3); Each of the three-dimensional semiconductor device arrays (2) includes multiple device layers in the vertical direction. Each device layer includes a stack of source / drain layers (22), channel layers (23), and source / drain layers (22). Metal silicides (5) are formed on the sidewalls of the isolation trench (3). The metal silicides (5) are in contact with the end faces of all the source / drain layers (22). The three-dimensional semiconductor device array (2) further includes a plurality of gate stacks (4) arranged in an array, the gate stacks (4) passing through each of the device layers in a vertical direction, including gate conductors (41) and gate dielectric layers (42) disposed between the gate conductors (41) and the device layers, defining device cells at the intersection of the gate stacks (4) and the device layers.

2. The semiconductor device for reducing source-drain resistance according to claim 1, characterized in that, The source / drain layer (22) and channel layer (23) in each of the device layers extend along the extension direction of the isolation trench (3) to form a stepped contact area in the source / drain layer (22).

3. The semiconductor device for reducing source-drain resistance according to claim 2, characterized in that, Silicon oxide is deposited on the three-dimensional semiconductor device array (2) to form a dielectric isolation layer (6), which covers the contact area and upper surface of the three-dimensional semiconductor device array (2) and each of the isolation trenches (3), and the upper surface of the dielectric isolation layer (6) is planarized.

4. The semiconductor device for reducing source-drain resistance according to claim 3, characterized in that, The upper surface of the dielectric isolation layer (6) is vertically etched with a plurality of contact holes (7), each of the contact holes (7) extending to a contact area of ​​a source / drain layer (22).

5. The semiconductor device for reducing source-drain resistance according to claim 1, characterized in that, The lower source / drain layer (22) in the upper device layer is the same source / drain layer as the upper source / drain layer (22) in the adjacent lower device layer.

6. The semiconductor device for reducing source-drain resistance according to any one of claims 1 to 5, characterized in that, A silicon oxide isolation layer (21) is provided between the two source / drain layers (22) of each device layer and at the bottom of the three-dimensional semiconductor device array (2). The bottom of the gate stack (4) is located in the silicon oxide isolation layer (21) at the bottom of the three-dimensional semiconductor device array (2); The channel layer (23) is disposed between the gate dielectric layer (42) and the structure formed by the two source / drain layers (22) and the silicon oxide isolation layer (21).

7. The semiconductor device for reducing source-drain resistance according to claim 6, characterized in that, The source / drain layer (22) and the channel layer (23) are made of doped polycrystalline silicon.

8. The semiconductor device for reducing source-drain resistance according to any one of claims 1 to 5, characterized in that, The substrate (1) has a germanium-silicon doped layer (24) on its upper surface. The bottom of the gate stack (4) is located in the doped germanium silicon layer (24); The source / drain layer (22), channel layer (23), and source / drain layer (22) in the device layer are stacked sequentially from bottom to top; The bottom of the isolation trench (3) is located in the doped germanium silicon layer (24); The end faces of the channel layer (23) and the doped germanium-silicon layer (24) adjacent to the isolation trench (3) form a dielectric inner wall (8).

9. The semiconductor device for reducing source-drain resistance according to claim 8, characterized in that, The source / drain layer (22) is a heavily doped silicon material, and the channel layer (23) is a germanium-silicon doped material.

10. A manufacturing method, characterized in that, include: Multiple device layers are grown on a substrate (1), each of the device layers comprising a stack of a source / drain layer (22), a channel layer (23), and a source / drain layer (22); Multiple gate holes are formed through each device layer in a vertical direction perpendicular to the substrate (1), and gate stacks (4) are formed in the gate holes. The gate stacks (4) are arranged in an array and include gate conductors (41) and gate dielectric layers (42) disposed between the gate conductors (41) and the device layers. Device cells are defined at the intersection of the gate stacks (4) and the device layers. The device layer is etched in a vertical direction perpendicular to the substrate (1) to form an isolation trench (3) and a plurality of three-dimensional semiconductor device arrays (2) separated by the isolation trench (3). In the isolation trench (3), the end faces of each of the source / drain layers (22) exposed in the three-dimensional semiconductor device array (2) are metallized to form metal silicide (5), which contacts the end faces of all the source / drain layers (22).

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