Light emitting diode epitaxial wafer and preparation method thereof, LED

Abstract

The application discloses a light emitting diode epitaxial wafer and a preparation method thereof and an LED, and the light emitting diode epitaxial wafer comprises a substrate, wherein an N-type semiconductor layer, an active layer, a composite insertion layer and a P-type semiconductor layer are sequentially arranged on the substrate; the active layer comprises periodically and alternately arranged potential well layers and potential barrier layers; the potential barrier layer adjacent to the composite insertion layer comprises a B x Al y In z Ga 1‑x‑y‑z N layer; and the composite insertion layer comprises a P-type doped DInGaN layer and a DInGaN / GaN superlattice layer, wherein D is Al or B, 0<=x<=1, 0<=y<=1 and 0<=z<=1. The light emitting diode epitaxial wafer can enhance the blocking capacity of the LED to electrons, improve the electron binding capacity, solve the problem of electron overflow and improve the injection efficiency of holes.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic technology, and in particular to a light-emitting diode epitaxial wafer and its preparation method, and LEDs. Background Technology

[0002] Currently, to enhance the electron-binding ability of GaN-based LEDs and reduce electron overflow, AlGaN layers, AlN layers, or combinations thereof are typically inserted between the active layer and the P-type semiconductor layer to enhance electron blocking capability. However, the introduction of these electron blocking capabilities also brings some problems. While enhancing electron blocking capability, the composite insertion layer also reduces hole injection efficiency and carrier recombination efficiency in the active layer. Furthermore, there is a significant lattice mismatch between the composite insertion layer, the active layer, and the P-type semiconductor layer, which not only introduces a strong polarization electric field but also degrades the crystal quality of the epitaxial layer, affecting device performance.

[0003] Therefore, reducing electron leakage, increasing hole injection efficiency, weakening strong polarization electric fields, and promoting efficient recombination of charge carriers in the active region are key to improving LED luminous efficiency. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an epitaxial wafer for a light-emitting diode that can enhance the LED's ability to block electrons, improve the ability to bind electrons, improve the problem of electron overflow, and at the same time improve the efficiency of hole injection.

[0005] The technical problem to be solved by the present invention is to provide a method for preparing an epitaxial wafer of a light-emitting diode, which has a simple process and can stably produce an epitaxial wafer of a light-emitting diode with good luminous efficiency.

[0006] To solve the above-mentioned technical problems, the present invention provides a light-emitting diode epitaxial wafer, including a substrate, wherein an N-type semiconductor layer, an active layer, a composite insertion layer and a P-type semiconductor layer are sequentially disposed on the substrate;

[0007] The active layer comprises periodically alternating potential well layers and potential barrier layers, and the potential barrier layer adjacent to the composite insertion layer includes B. x Al y In z Ga 1-x-y-z The N-layer, the composite insertion layer includes a P-type doped DInGaN layer and a DInGaN / GaN superlattice layer, wherein D is Al or B, 0≤x≤1, 0≤y≤1, and 0≤z≤1.

[0008] In one embodiment, the barrier layer adjacent to the composite insertion layer includes a plurality of B... x Al y Inz Ga 1-x-y-z N layers.

[0009] In one implementation, the adjacent B x Al y In z Ga 1-x-y-z In the N-layer, B is located near the N-type semiconductor layer. x Al y In z Ga 1-x-y-z The bandgap of layer N is smaller than that of layer B, which is closer to the composite insertion layer. x Al y In z Ga 1-x-y-z The bandgap width of layer N.

[0010] In one implementation, the adjacent B x Al y In z Ga 1-x-y-z The lattice mismatch of the N-layer is 0.1%–3%.

[0011] In one embodiment, the bandgap of the P-type doped DInGaN layer is smaller than that of the B-type doped DInGaN layer. x Al y In z Ga 1-x-y-z The bandgap width of layer N.

[0012] In one implementation, the B x Al y In z Ga 1-x-y-z The thickness of the N layer ranges from 0.1 nm to 10 nm.

[0013] To address the above problems, the present invention also provides a method for fabricating a light-emitting diode epitaxial wafer, comprising the following steps:

[0014] S1. Prepare the substrate;

[0015] S2. An N-type semiconductor layer, an active layer, a composite insertion layer, and a P-type semiconductor layer are sequentially deposited on the substrate.

[0016] The active layer comprises periodically alternating potential well layers and potential barrier layers, and the potential barrier layer adjacent to the composite insertion layer includes B. x Al y In z Ga 1-x-y-z The N-layer, the composite insertion layer includes a P-type doped DInGaN layer and a DInGaN / GaN superlattice layer, wherein D is Al or B, 0≤x≤1, 0≤y≤1, and 0≤z≤1.

[0017] In one embodiment, the active layer is prepared by the following method:

[0018] Multiple cycles of potential well and barrier layers are grown alternately, with the B layer inserted during the growth of the last barrier layer. x Al y In z Ga 1-x-y-z N layers.

[0019] In one implementation, a plurality of the B layers are inserted during the growth of the final barrier layer. x Al y In z Ga 1-x-y-z N layers, adjacent to the B layers x Al y In z Ga 1-x-y-z In the N-layer, B is located near the N-type semiconductor layer. x Al y In z Ga 1-x-y-z The bandgap of layer N is smaller than that of layer B, which is closer to the composite insertion layer. x Al y In z Ga 1-x-y-z The bandgap width of layer N.

[0020] Accordingly, the present invention also provides an LED, which includes the above-described light-emitting diode epitaxial wafer.

[0021] Implementing this invention has the following beneficial effects:

[0022] The present invention provides a light-emitting diode epitaxial wafer having an active layer and a composite insertion layer with a specific structure. The active layer includes a potential well layer and a potential barrier layer arranged in a periodic alternating pattern. The potential barrier layer adjacent to the composite insertion layer includes B. x Al y In z Ga 1-x-y-z The N-layer, the composite insertion layer includes a P-type doped DInGaN layer and a DInGaN / GaN superlattice layer, wherein D is Al or B.

[0023] This invention inserts B in the last barrier layer x Al y In z Ga 1-x-y-z The N-layer can reduce the defect density caused by lattice mismatch, improve the crystal quality of the last barrier layer, and provide a better growth platform for subsequent composite insertion layers.

[0024] Compared to the last barrier layer, the P-type doped DInGaN layer in the composite insertion layer, with its smaller bandgap and lower barrier height, can accommodate electrons overflowing from the active layer. The highly concentrated doped P-type DInGaN layer prevents electrons from overflowing into the P-type semiconductor layer and provides a large number of holes to the active layer. The DInGaN / GaN superlattice layer in the composite insertion layer further enhances the electron and hole accommodating capacity of the P-type doped DInGaN layer, improving the efficiency of hole injection into the active layer and preventing further electron overflow into the P-type semiconductor layer, thus preventing leakage current. On the other hand, the DInGaN / GaN superlattice layer reduces dislocation propagation, effectively reducing the defect density of the epitaxial layer, providing a good growth platform for the subsequent P-type semiconductor layer, improving the crystal quality of the epitaxial layer, and enhancing device performance. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the light-emitting diode epitaxial wafer provided by the present invention;

[0026] Figure 2 A flowchart illustrating the method for fabricating a light-emitting diode epitaxial wafer provided by the present invention;

[0027] Figure 3 The flowchart shows step S2 of the method for preparing a light-emitting diode epitaxial wafer provided by the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below.

[0029] Unless otherwise stated or in case of contradiction, the terms or phrases used herein shall have the following meanings:

[0030] In this invention, "preferred" is merely a description of a more effective implementation method or embodiment, and should be understood as not constituting a limitation on the scope of protection of this invention.

[0031] In this invention, the technical features described in an open-ended manner include both closed-ended technical solutions composed of the listed features and open-ended technical solutions that include the listed features.

[0032] In this invention, numerical ranges are involved, and unless otherwise specified, they include the two endpoints of the numerical range.

[0033] To address the above problems, the present invention provides a light-emitting diode epitaxial wafer, such as... Figure 1 As shown, it includes a substrate 1, on which an N-type semiconductor layer 2, an active layer 3, a composite insertion layer 4, and a P-type semiconductor layer 5 are sequentially disposed;

[0034] The active layer 3 includes periodically alternating potential well layers and potential barrier layers, and the potential barrier layer adjacent to the composite insertion layer 4 includes B. x Al y In z Ga 1-x-y-z The N-layer, the composite insertion layer 4 includes a P-type doped DInGaN layer 41 and a DInGaN / GaN superlattice layer 42, wherein D is Al or B, 0≤x≤1, 0≤y≤1, and 0≤z≤1.

[0035] The specific structure of the active layer 3 is as follows:

[0036] In one embodiment, the active layer 3 is a periodically alternating arrangement of potential well layers and potential barrier layers, with an active layer growth cycle of 6-12. The potential well layer is an InGaN layer, and the potential barrier layer is a GaN layer and / or an AlGaN layer. The last potential barrier layer is inserted with the InGaN layer. x Al y In z Ga 1-x-y-z N layers, the B x Al y In z Ga 1-x-y-z The thickness of the N layer is 0.1 nm to 10 nm. The B layer... x Al y In z Ga 1-x-y-z Exemplary thicknesses of the N layer are 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, and 9nm, but are not limited thereto. In one embodiment, the barrier layer adjacent to the composite insertion layer 4 includes a plurality of the B layers. x Al y In z Ga 1-x-y-z N layers. Preferably, adjacent layers B x Al y In z Ga 1-x-y-z In the N layer, B is close to the N-type semiconductor layer 2. x Al y In z Ga 1-x-y-z The bandgap of layer N is smaller than that of layer B, which is closer to the composite insertion layer 4. x Al y In z Ga 1-x-y-z The bandgap width of layer N. This allows multiple B... x Al y In z Ga 1-x-y-zThe bandgap between the N layers gradually increases along the growth direction, effectively blocking electron leakage and improving electron blocking capability. This reduces the further migration of electrons from the active layer to the P-type semiconductor layer, reducing non-radiative recombination. Furthermore, the overall upward shift of the bandgap reduces the difficulty of hole injection into the active layer, enhancing electron-hole recombination in the active region and improving the internal quantum efficiency of the active layer. More preferably, the adjacent B layers... x Al y In z Ga 1-x-y-z The lattice mismatch of the N-layer is 0.1%-3%, resulting in a low defect density due to lattice mismatch.

[0037] Ideally, the last barrier layer of the active layer, i.e., the barrier layer adjacent to the composite insertion layer, includes a GaN layer and an Al layer. y1 In 0.353y1 Ga 1-1.353y1 N layer and B x1 Al y2 In z1 N layers, where 0.2 ≤ y1 ≤ 0.7, x1 + y2 + z1 = 1. Under this grouping ratio, the Al y1 In 0.353y1 Ga 1-1.353y1 The near-zero lattice mismatch between the N-layer and the GaN-layer reduces defects caused by lattice mismatch, improves the crystal quality of the barrier layer, and provides a better growth platform for subsequent nitride sublayers. Furthermore, Al... y1 In 0.353y1 Ga 1-1.353y1 Compared to GaN layers, N-layers have a wider bandgap and a higher barrier, which can block electrons from migrating from the active layer to the P-type semiconductor layer, reduce non-radiative recombination, and improve luminescence efficiency.

[0038] Preferably, the B x1 Al y2 In z1 In layer N, x1 = 0.1, y2 = 0.67, z1 = 0.23. Under this distribution ratio, the B... x1 Al y2 In z1 The N layer has a much higher efficiency than Al. y1 In 0.353y1 Ga 1-1.353y1 The band gap and barrier of the N-layer and GaN-layer, and the B x1 Al y2 In z1 N-layer and Al y1 In 0.353y1 Ga 1-1.353y1The lattice mismatch between the N-layer and the GaN-layer is less than 2%, resulting in a low defect density. The introduction of boron atoms, on the one hand, makes the boron... 0.1 Al 0.67 In 0.23 The upward shift of the N-layer band gap enhances the ability to block electrons, reduces the difficulty of injecting holes into the active layer, and strengthens the recombination efficiency of electrons and holes in the active region. On the other hand, the B atom has a smaller atomic mass, which can, to some extent, fill the defects generated during the epitaxial layer growth process and improve the crystal quality of the barrier layer.

[0039] The specific structure of the composite insertion layer 4 is as follows:

[0040] In one embodiment, the bandgap of the P-type doped DInGaN layer 41 is smaller than that of the B-type doped DInGaN layer 41. x Al y In z Ga 1-x-y-z The bandgap of the N-layer. Compared to the last barrier layer, the P-type doped DInGaN layer in the composite insertion layer has a smaller bandgap and a lower barrier height, which can accommodate electrons overflowing from the active layer. The highly concentrated Mg-doped P-type doped DInGaN layer 41 can prevent electrons from overflowing to the P-type semiconductor layer and also provide a large number of holes to the active layer.

[0041] The DInGaN / GaN superlattice layer 42 in the composite insertion layer 4 enhances the electron and hole accommodating capacity of the P-type doped DInGaN layer, improves the efficiency of hole injection into the active layer, and prevents further electron overflow into the P-type semiconductor layer, thus preventing leakage current. On the other hand, the DInGaN / GaN superlattice layer reduces dislocation elongation, effectively reducing the defect density of the epitaxial layer, providing a good growth platform for the subsequent P-type semiconductor layer, improving the crystal quality of the epitaxial layer, and enhancing device performance.

[0042] Preferably, in the composite insertion layer, the P-type doped DInGaN layer 41 is a P-type doped AlInGaN layer, and the P-type dopant is Mg; the DInGaN / GaN superlattice layer 42 is a BinGaN / GaN superlattice structure layer. The P-type doped AlInGaN layer, with a smaller bandgap and lower barrier height compared to the barrier layer, can accommodate electrons overflowing from the active layer, and the highly concentrated Mg-doped P-type doped AlInGaN layer can prevent electrons from overflowing to the P-type semiconductor layer and provide a large number of holes for the active layer. The BinGaN / GaN superlattice structure can enhance the capacity of the P-type doped AlInGaN layer to accommodate electrons and holes, improve the efficiency of hole injection into the active layer, and prevent further leakage of electrons into the P-type semiconductor layer, thus preventing leakage. On the other hand, the BinGaN / GaN superlattice structure can reduce dislocation propagation, and the smaller atomic radius of B atoms is beneficial for filling defects that occur during growth. Combined with GaN, which has relatively higher crystal quality, it can effectively reduce the defect density of the epitaxial layer, provide a good growth platform for the subsequent P-type semiconductor layer, improve the crystal quality of the epitaxial layer, and enhance the performance of the device.

[0043] Accordingly, the present invention provides a method for fabricating a light-emitting diode epitaxial wafer, such as... Figure 2 As shown, it includes the following steps:

[0044] S1. Prepare substrate 1;

[0045] In one embodiment, the substrate may be selected from one of the following: sapphire substrate, SiO2 sapphire composite substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, and zinc oxide substrate. Preferably, the substrate is a sapphire substrate.

[0046] S2. An N-type semiconductor layer 2, an active layer 3, a composite insertion layer 4, and a P-type semiconductor layer 5 are sequentially deposited on the substrate 1.

[0047] like Figure 3 As shown, step S2 includes the following steps:

[0048] S21. Deposit an N-type semiconductor layer 2 on substrate 1.

[0049] In one embodiment, the N-type semiconductor layer includes a buffer layer, an intrinsic GaN layer, and an N-type GaN layer, and the specific fabrication method is as follows:

[0050] The temperature of the reaction chamber was controlled at 750℃~820℃, the pressure was controlled at 100 torr~200 torr, and N source and Al source were introduced to grow an AlN buffer layer with a thickness of 5nm~25nm.

[0051] The temperature of the reaction chamber was controlled at 1000℃~1250℃, the pressure was controlled at 100torr~300torr, and N source and Ga source were introduced to grow GaN intrinsic layer with a thickness of 1μm~1.7μm.

[0052] The temperature of the reaction chamber is controlled at 1000℃~1200℃, and the pressure is controlled at 100torr~600torr. N source, Ga source and Si source are introduced to grow an N-type GaN layer with a thickness of 1μm~3μm.

[0053] S22. Deposit an active layer 3 on the N-type semiconductor layer 2.

[0054] In one embodiment, the active layer is prepared by the following method:

[0055] Multiple cycles of potential well and barrier layers are grown alternately, with the B layer inserted during the growth of the last barrier layer. x Al y In z Ga 1-x-y-z N layers.

[0056] Preferably, a plurality of the B layers are inserted during the growth of the last barrier layer. x Al y In z Ga 1-x-y-z N layers, adjacent to the B layers x Al y In z Ga 1-x-y-z In the N-layer, B is located near the N-type semiconductor layer. x Al y In z Ga 1-x-y-z The bandgap of layer N is smaller than that of layer B, which is closer to the composite insertion layer. x Al y In z Ga 1-x-y-z The bandgap width of layer N.

[0057] More preferably, the fabrication process of the potential well layer is as follows: the reaction chamber temperature is 750℃~850℃, the pressure is 150torr~250torr, the rotation speed of the graphite pedestal supporting the substrate is 600 rpm~1000 rpm, NH3 is used as the N (nitrogen) source, TEGa (triethylgallium) is used as the Ga (gallium) source, and TMIn (trimethylindium) is used as the In (indium) source, and the thickness of the deposited InGaN potential well layer is controlled to be 1nm~5nm.

[0058] Furthermore, the specific process for depositing the barrier layers other than the last barrier layer on the potential well layer is as follows: the reaction chamber temperature is 800℃~900℃, the pressure is 150torr~250torr, the rotation speed of the graphite pedestal supporting the substrate is 600 rpm~1000 rpm, NH3 is used as the N (nitrogen) source, TEGa (triethylgallium) is used as the Ga (gallium) source, and the thickness of the deposited GaN barrier layer is controlled to be 8nm~14nm.

[0059] Ideally, three layers of B should be inserted when depositing the last barrier layer. x Al y In z Ga 1-x-y-z N layers, where the first sub-layer is a GaN layer, the second sub-layer is an Al layer, and so on. y1 In 0.353y1 Ga 1-1.353y1 N, the third sub-layer is B 0.1 Al 0.67 In 0.23 The N-layer fabrication process is as follows:

[0060] The deposition process of the first sublayer GaN layer is as follows: the reaction chamber temperature is 800℃~900℃, the rotation speed of the graphite substrate is 150 torr~250 torr, the rotation speed of the graphite substrate is 600 rpm~1000 rpm, NH3 is used as the N (nitrogen) source, TEGa (triethylgallium) is used as the Ga (gallium) source, and the thickness of the deposited first sublayer GaN layer is controlled to be 2nm~7nm;

[0061] Second sublayer Al y1 In 0.353y1 Ga 1-1.353y1 The deposition process for the N layer is as follows: the reaction chamber temperature is 800℃~900℃, the rotation speed of the graphite substrate is 100 to 200 torr, the rotation speed of the graphite substrate is 700 rpm to 1100 rpm, NH3 is used as the N (nitrogen) source, TEGa (triethylgallium) is used as the Ga (gallium) source, TMAl (trimethylaluminum) is used as the Al source, and TMIn (trimethylindium) is used as the indium source, and the deposition thickness is controlled to be 1nm~4nm;

[0062] Third sublayer B 0.1 Al 0.67 In 0.23 The deposition process for the N layer is as follows: the reaction chamber temperature is 800℃~900℃, the rotation speed of the graphite substrate is 100 torr~150 torr, the rotation speed of the graphite substrate is 700 rpm~1100 rpm, NH3 is used as the N (nitrogen) source, TMAl (trimethylaluminum) is used as the Al source, TMIn (trimethylindium) is used as the indium source, and TEB (triethylboron) is used as the B (boron) source, and the deposition thickness is controlled to be 0.5nm~2nm.

[0063] S23. Deposit a composite insertion layer 4 on the active layer 3.

[0064] In one embodiment, the temperature of the reaction chamber is controlled at 700°C to 1200°C, and the pressure is controlled at 100 torr to 250 torr to grow a P-type doped DInGaN layer and a DInGaN / GaN superlattice layer.

[0065] Preferably, the P-type doped DInGaN layer is a P-type doped AlInGaN layer, and the specific preparation process is as follows: the reaction chamber temperature is 750℃~850℃, the pressure is 150 torr~250 torr, the rotation speed of the graphite pedestal supporting the substrate is 900 rpm~1300 rpm, NH3 is used as the N (nitrogen) source, TEGa (triethylgallium) is used as the Ga (gallium) source, TMIn (trimethylindium) is used as the In (indium) source, TMAl (trimethylaluminum) is used as the Al source, and CP2Mg (magnesium pyrocene) is used as the Mg (magnesium) source. The deposited thickness is controlled to be 3nm~15nm, and the Mg doping concentration is 1×10⁻⁶. 19 atoms / cm 3 ~1×10 21 atoms / cm 3 .

[0066] Preferably, the DInGaN / GaN superlattice layer is a BinGaN / GaN superlattice structure layer. The specific process involves: a reaction chamber temperature of 900℃~1000℃, a pressure of 100 torr~200 torr, a graphite substrate rotation speed of 900 rpm~1100 rpm, NH3 as the N (nitrogen) source, TEGa (triethylgallium) as the Ga (gallium) source, TMIn (trimethylindium) as the In (indium) source, and TEB (triethylboron) as the B (boron) source. Under an N2 atmosphere, the thickness of the deposited monolayer BInGaN is controlled to be 1 nm to 2 nm. Then, the In (indium) source and B (boron) source are stopped, and the reaction chamber temperature is controlled at 1000 °C to 1100 °C and the pressure is controlled at 150 torr to 250 torr. Under an H2 or H2 and N2 mixed atmosphere, the thickness of the deposited monolayer GaN is controlled to be 2 nm to 3 nm. The above steps are repeated so that the BInGaN / GaN superlattice structure layer consists of 3 to 5 periodically stacked BInGaN and GaN layers.

[0067] S24. Deposit a P-type semiconductor layer 5 on the composite insertion layer 4.

[0068] In one embodiment, the P-type semiconductor bulk layer is a P-type low-Mg-doped GaN layer and a P-type high-Mg-doped GaN layer stacked sequentially.

[0069] Preferably, the specific deposition process of the P-type low-Mg-doped GaN layer is as follows: the reaction chamber temperature is 980℃~1050℃, NH3 is used as the N (nitrogen) source, TEGa is used as the Ga (gallium) source, and CP2Mg is used as the P-type dopant. The thickness of the deposited P-type low-Mg-doped GaN filler layer is controlled to be 15nm~20nm under H2 atmosphere, wherein the Mg doping concentration is 1×10⁻⁶. 18 atoms / cm 3 ~1×10 20 atoms / cm 3 .

[0070] Preferably, the specific deposition process of the P-type Mg-doped GaN layer is as follows: the reaction chamber temperature is 930℃~1000℃, NH3 is used as the N (nitrogen) source, TEGa is used as the Ga (gallium) source, and CP2Mg is used as the P-type dopant. The thickness of the deposited P-type Mg-doped GaN layer is controlled to be 5nm~15nm under H2 or a mixed atmosphere of H2 and N2, wherein the Mg doping concentration can be 1×10⁻⁶. 20 atoms / cm 3 ~1×10 22 atoms / cm 3 .

[0071] Accordingly, the present invention also provides an LED comprising the aforementioned light-emitting diode epitaxial wafer. The photoelectric efficiency of the LED is effectively improved, and other electrical properties are also excellent.

[0072] The present invention is further illustrated below with specific embodiments:

[0073] Example 1

[0074] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate, on which an N-type semiconductor layer, an active layer, a composite insertion layer, and a P-type semiconductor layer are sequentially disposed;

[0075] The active layer comprises periodically alternating potential well layers and potential barrier layers, and the potential barrier layer adjacent to the composite insertion layer comprises a GaN layer and an Al layer. 0.2 In 0.0706 Ga 0.7294 N layer and B 0.1 Al 0.67 In 0.23 The N-layer, the composite insertion layer includes a P-type doped AlInGaN layer and a BinGaN / GaN superlattice layer.

[0076] Example 2

[0077] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that: the barrier layer adjacent to the composite insertion layer includes a GaN layer and an Al layer.0.2 In 0.0706 Ga 0.7294 N layers; everything else is the same as in Example 1.

[0078] Example 3

[0079] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that: the barrier layer adjacent to the composite insertion layer includes a GaN layer and a B layer. 0.1 Al 0.67 In 0.23 N layers; everything else is the same as in Example 1.

[0080] Example 4

[0081] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that: the composite insertion layer includes a P-type doped BInGaN layer and a BInGaN / GaN superlattice layer; otherwise, it is the same as Embodiment 1.

[0082] Example 5

[0083] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that: the composite insertion layer includes a P-type doped AlInGaN layer and an AlInGaN / GaN superlattice layer; otherwise, it is the same as Embodiment 1.

[0084] Comparative Example 1

[0085] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that it does not have a composite insertion layer, but otherwise refers to Example 1.

[0086] Comparative Example 2

[0087] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that: the active layer includes a periodically alternating potential well layer and a potential barrier layer, wherein the potential barrier layer is a GaN layer, and the rest is the same as in Example 1.

[0088] The light-emitting diode epitaxial wafers prepared in Examples 1 to 5 and Comparative Examples 1 to 2 were fabricated into 10mil×24mil chips using the same chip process conditions. 300 LED chips were randomly selected from each chip, and the luminous intensity of the chips was tested at a current of 120mA. The antistatic capability of the chips was tested using an electrostatic meter under the HBM (Human Body Model) model. The percentage of chips that could withstand 6000V of static electricity was tested. The specific test results are shown in Table 1.

[0089] Table 1. Performance test results of LEDs prepared in Examples 1-5 and Comparative Examples 1-2

[0090]

[0091] As can be seen from the above results, the LED epitaxial wafer provided by the present invention inserts multiple B atoms in the last barrier layer. x Al y In z Ga 1-x-y-z The N-layer can reduce the defect density caused by lattice mismatch, improve the crystal quality of the last barrier layer, and provide a better growth platform for subsequent composite insertion layers.

[0092] Compared to the last barrier layer, the P-type doped DInGaN layer in the composite insertion layer, with its smaller bandgap and lower barrier height, can accommodate electrons overflowing from the active layer. The highly concentrated doped P-type DInGaN layer prevents electrons from overflowing into the P-type semiconductor layer and provides a large number of holes to the active layer. The DInGaN / GaN superlattice layer in the composite insertion layer further enhances the electron and hole accommodating capacity of the P-type doped DInGaN layer, improving the efficiency of hole injection into the active layer and preventing further electron overflow into the P-type semiconductor layer, thus preventing leakage current. On the other hand, the DInGaN / GaN superlattice layer reduces dislocation propagation, effectively reducing the defect density of the epitaxial layer, providing a good growth platform for the subsequent P-type semiconductor layer, improving the crystal quality of the epitaxial layer, and enhancing device performance.

[0093] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that, Includes a substrate, on which an N-type semiconductor layer, an active layer, a composite insertion layer, and a P-type semiconductor layer are sequentially disposed; The active layer comprises periodically alternating potential well layers and potential barrier layers, and the potential barrier layer adjacent to the composite insertion layer includes multiple B layers. x Al y In z Ga 1-x-y-z N-layer, the composite insertion layer includes a P-type doped DInGaN layer and a DInGaN / GaN superlattice layer, wherein D is B, 0≤x≤1, 0≤y≤1, 0≤z≤1; The adjacent B x Al y In z Ga 1-x-y-z In the N-layer, B is located near the N-type semiconductor layer. x Al y In z Ga 1-x-y-z The bandgap of layer N is smaller than that of layer B, which is closer to the composite insertion layer. x Al y In z Ga 1-x-y-z The bandgap width of layer N; The band gap of the P-type doped DInGaN layer is smaller than that of the B-type doped DInGaN layer x Al y In z Ga 1-x-y-z The bandgap width of layer N.

2. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The adjacent B x Al y In z Ga 1-x-y-z The lattice mismatch of the N-layer is 0.1%-3%.

3. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The B x Al y In z Ga 1-x-y-z The thickness of the N layer ranges from 0.1 nm to 10 nm.

4. A method for fabricating a light-emitting diode epitaxial wafer as described in any one of claims 1 to 3, characterized in that, Includes the following steps: S1. Prepare the substrate; S2. An N-type semiconductor layer, an active layer, a composite insertion layer, and a P-type semiconductor layer are sequentially deposited on the substrate. The active layer comprises periodically alternating potential well layers and potential barrier layers, and the potential barrier layer adjacent to the composite insertion layer includes B. x Al y In z Ga 1-x-y-z The N-layer, the composite insertion layer includes a P-type doped DInGaN layer and a DInGaN / GaN superlattice layer, where D is B, 0≤x≤1, 0≤y≤1, 0≤z≤1.

5. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 4, characterized in that, The active layer is prepared using the following method: Multiple cycles of potential well and barrier layers are grown alternately, with the B layer inserted during the growth of the last barrier layer. x Al y In z Ga 1-x-y-z N layers.

6. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 5, characterized in that, Multiple Bs were inserted during the growth of the last barrier layer. x Al y In z Ga 1-x-y-z N layers, adjacent to the B layers x Al y In z Ga 1-x-y-z In the N-layer, B is located near the N-type semiconductor layer. x Al y In z Ga 1-x-y-z The bandgap of layer N is smaller than that of layer B, which is closer to the composite insertion layer. x Al y In z Ga 1-x-y-z The bandgap width of layer N.

7. An LED, characterized in that, The LED includes a light-emitting diode epitaxial wafer as described in any one of claims 1 to 3.

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