A three-level dc / dc circuit and power supply system

Abstract

The application discloses a three-level DC / DC circuit and a power supply system, which comprise an anti-reverse flow device, a first input capacitor, a second input capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first inductor, a second inductor, a first output capacitor and a second output capacitor; the anti-reverse flow device is connected on a current path between an output positive electrode and an input positive electrode, and the anti-reverse flow device is cut off when the current direction is from the output positive electrode to the input positive electrode. When the input positive electrode is grounded, the anti-reverse flow device is cut off when the current direction is from the output positive electrode to the input positive electrode. When the three-level DC / DC circuit normally works, the anti-reverse flow device is normally conducted, so that the risk of short circuit from the output positive electrode to the input positive electrode of the DC / DC circuit can be avoided, and the devices in the three-level DC / DC circuit are protected.

Description

Technical Field

[0001] This application relates to the field of new energy technology, specifically to a three-level DC / DC circuit and power supply system. Background Technology

[0002] Currently, with the continuous development of new energy sources, DC / DC circuits are increasingly being used as the last stage of a power supply system to provide DC voltage. For example, in the application of electrolytic cells, where DC power is used to power the electrolytic cells, DC / DC circuits provide the DC operating voltage for the electrolytic cells.

[0003] Electrolytic cells, as loads, are generally grounded at the negative terminal or the neutral point. For DC / DC circuits that are not grounded at the positive terminal, if the DC / DC circuit experiences grounding due to broken insulation or foreign objects connecting to the copper busbar during operation, the positive input terminal of the DC / DC circuit will be grounded.

[0004] Because the load negative terminal or load midpoint of the DC / DC circuit is grounded, if an abnormality occurs, the input positive terminal of the DC / DC circuit will be grounded, and there will be a short circuit risk from the output positive terminal to the input positive terminal of the DC / DC circuit, which may damage the components in the DC / DC circuit. Summary of the Invention

[0005] In view of this, this application provides a three-level DC / DC circuit and power supply system that can ground the positive input terminal of the DC / DC circuit to avoid the risk of short circuit from the positive output terminal to the positive input terminal of the DC / DC circuit.

[0006] This application provides a three-level DC / DC circuit, including: an anti-reverse current device, a first input capacitor, a second input capacitor, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first inductor, a second inductor, a first output capacitor, and a second output capacitor;

[0007] The first and second terminals of the first input capacitor are connected to the first node and the midpoint, respectively. The positive input terminal of the DC / DC circuit is connected to the first node. The first and second terminals of the second input capacitor are connected to the midpoint and the sixth node, respectively.

[0008] The first and second ends of the first switch are connected to the first node and the second node respectively; the first and second ends of the second switch are connected to the second node and the midpoint respectively; the first and second ends of the third switch are connected to the midpoint and the fifth node respectively; and the first and second ends of the fourth switch are connected to the fifth node and the sixth node respectively.

[0009] The first and second terminals of the first inductor are connected to the second and third nodes, respectively; the first and second terminals of the first output capacitor are connected to the third node and the midpoint, respectively; the first and second terminals of the second output capacitor are connected to the midpoint and the fourth node, respectively; the first and second terminals of the second inductor are connected to the fifth and fourth nodes, respectively; the positive and negative output terminals of the DC / DC circuit are connected to the third and fourth nodes, respectively.

[0010] The anti-reverse current device is connected in the current path between the output positive terminal and the input positive terminal. The anti-reverse current device is turned off when the current direction is from the output positive terminal to the input positive terminal.

[0011] Preferably, the anti-backflow device is at least one of the following:

[0012] Diodes, semi-controlled semiconductor devices, or fully controlled semiconductor devices;

[0013] When the anti-reverse current device is a semi-controlled semiconductor device or a fully controlled semiconductor device, the DC / DC circuit also includes: a controller;

[0014] The controller is electrically connected to a semi-controlled semiconductor device or a fully controlled semiconductor device;

[0015] A controller is used to control the switching state of semi-controlled or fully controlled semiconductor devices.

[0016] Preferably, the DC / DC circuit further includes: an overvoltage protection device connected in the current path between the output negative terminal and the input negative terminal of the DC / DC circuit, the overvoltage protection device including a fully controllable semiconductor device, the overvoltage protection device being controlled to conduct when the current direction is from the output negative terminal to the input negative terminal during normal operation; the fully controllable semiconductor device being disconnected when the input positive terminal is short-circuited to ground.

[0017] Preferably, when the anti-reverse current device is a semi-controlled semiconductor device or a fully controlled semiconductor device, the DC / DC circuit further includes: a detection device;

[0018] The detection device is used to detect the input positive voltage to ground and send the input positive voltage to ground to the controller;

[0019] The controller is used to report a fault when a ground fault occurs at the input positive terminal based on the voltage between the input positive terminal and ground; the controller is also used to disconnect fully controlled semiconductor devices that allow bidirectional current flow.

[0020] When a ground fault occurs at the positive input terminal, either a semi-controlled semiconductor device or a fully controlled semiconductor device with unidirectional current flow will automatically shut off.

[0021] The controller is also used to control the conduction of semi-controlled or fully controlled semiconductor devices when there is no grounding fault at the positive input terminal.

[0022] Preferably, the detection device is also used to detect the voltage of the first input capacitor and the voltage of the second input capacitor to determine whether a voltage imbalance occurs, the current of the first inductor and the current of the second inductor to determine whether a voltage imbalance occurs, or the current of the positive output terminal and the current of the negative output terminal to determine whether a voltage imbalance occurs.

[0023] Preferably, the anti-reverse current device is connected between the input positive terminal and the first node.

[0024] Preferably, the anti-backflow device is connected between the first node and the second node.

[0025] Preferably, the anti-backflow device is connected between the second node and the third node.

[0026] Preferably, the anti-reverse current device is connected between the third node and the output positive terminal.

[0027] Preferably, the overvoltage protection device is connected between the negative input terminal and the sixth node.

[0028] Preferably, the overvoltage protection device is connected between the sixth node and the midpoint.

[0029] Preferably, the overvoltage protection device is connected between the midpoint and the fifth node.

[0030] Preferably, the overvoltage protection device is connected between the fifth node and the fourth node.

[0031] Preferably, the overvoltage protection device is connected between the fourth node and the output negative terminal.

[0032] This application also provides a power supply system, characterized in that it includes the three-level DC / DC circuit described above, and further includes an electrolytic cell;

[0033] The positive output of the three-level DC / DC circuit is connected to the positive terminal of the electrolytic cell, and the negative output of the three-level DC / DC circuit is connected to the negative terminal of the electrolytic cell. The negative terminal of the electrolytic cell is grounded or the midpoint of the electrolytic cell is grounded.

[0034] Therefore, this application has the following beneficial effects:

[0035] The three-level DC / DC circuit provided in this application embodiment incorporates an anti-reverse current device. This device is connected in the current path between the output positive terminal and the input positive terminal. When the input positive terminal is grounded, the anti-reverse current device is cut off from conduction when the current direction is from the output positive terminal to the input positive terminal. When the three-level DC / DC circuit is operating normally, the anti-reverse current device conducts normally, thereby preventing the risk of a short circuit from the output positive terminal to the input positive terminal of the DC / DC circuit and protecting the components in the three-level DC / DC circuit. Attached Figure Description

[0036] Figure 1 An application scenario diagram of a three-level DC / DC circuit provided in this application embodiment;

[0037] Figure 2 A schematic diagram of a three-level Buck TL circuit provided in an embodiment of this application;

[0038] Figure 3 This is a schematic diagram of the short-circuit current when the input positive terminal is grounded, provided in an embodiment of this application.

[0039] Figure 4 A schematic diagram of another three-level DC / DC circuit provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram showing the anti-reverse current device connected at position P1 in the three-level DC / DC circuit provided in the embodiments of this application;

[0041] Figure 6 This is a schematic diagram showing the anti-reverse current device connected at position P2 in the three-level DC / DC circuit provided in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram showing the anti-reverse current device connected at position P3 in the three-level DC / DC circuit provided in the embodiments of this application;

[0043] Figure 8 This is a schematic diagram showing the anti-reverse current device connected at position P4 in the three-level DC / DC circuit provided in the embodiments of this application;

[0044] Figure 9 A schematic diagram of another three-level DC / DC circuit provided in an embodiment of this application;

[0045] Figure 10 A schematic diagram showing the overvoltage protection device located at P5 according to an embodiment of this application;

[0046] Figure 11 A schematic diagram showing the overvoltage protection device located at P6 according to an embodiment of this application;

[0047] Figure 12 A schematic diagram showing the overvoltage protection device located at P7 according to an embodiment of this application;

[0048] Figure 13 A schematic diagram showing the overvoltage protection device located at P8 according to an embodiment of this application;

[0049] Figure 14 A schematic diagram showing the overvoltage protection device located at P9 according to an embodiment of this application;

[0050] Figure 15 A schematic diagram showing the fully controlled semiconductor device located at P9 in an embodiment of this application;

[0051] Figure 16 This is a schematic diagram of a power supply system provided in an embodiment of this application. Detailed Implementation

[0052] To enable those skilled in the art to better understand and implement the technical solutions provided in the embodiments of this application, the application scenarios are introduced below.

[0053] See Figure 1 The figure shows an application scenario of a three-level DC / DC circuit provided in an embodiment of this application.

[0054] The three-level DC / DC circuit 100 provided in this application embodiment does not specifically limit the specific load. It can be any load that is directly powered and not grounded, such as an alkaline electrolytic cell, with the negative terminal of the alkaline electrolytic cell grounded or the midpoint grounded.

[0055] For ease of understanding, we will take electrolytic cell 200 as the load and the negative terminal of electrolytic cell 200 as the example.

[0056] The three-level DC / DC circuit 100 includes an input positive terminal IN+ and an input negative terminal IN-, as well as an output positive terminal OUT+ and an output negative terminal OUT-, which are respectively connected to the positive and negative terminals of the electrolytic cell 200.

[0057] The following section uses a three-level DC / DC circuit, specifically a three-level Buck TL circuit, as an example for explanation.

[0058] See Figure 2 The figure is a schematic diagram of a three-level Buck TL circuit provided in an embodiment of this application.

[0059] The three-level DC / DC circuit provided in this application embodiment includes: a first input capacitor Ci1, a second input capacitor Ci2, a first switch Sa1, a second switch Sa2, a third switch Sa3, a fourth switch Sa4, a first inductor L1, a second inductor L2, a first output capacitor Co1, and a second output capacitor Co2.

[0060] The first terminal and the second terminal of the first input capacitor Ci1 are connected to the first node A and the midpoint O, respectively. The positive input terminal IN+ of the DC / DC circuit is connected to the first node A. The first terminal and the second terminal of the second input capacitor Ci2 are connected to the midpoint O and the sixth node F, respectively.

[0061] The first and second ends of the first switch Sa1 are connected to the first node A and the second node B, respectively. The first and second ends of the second switch Sa2 are connected to the second node B and the midpoint O, respectively. The first and second ends of the third switch Sa3 are connected to the midpoint O and the fifth node E, respectively. The first and second ends of the fourth switch Sa4 are connected to the fifth node E and the sixth node F, respectively.

[0062] The first and second terminals of the first inductor L1 are connected to the second node B and the third node C, respectively; the first and second terminals of the first output capacitor Co1 are connected to the third node C and the midpoint O, respectively; the first and second terminals of the second output capacitor Co2 are connected to the midpoint O and the fourth node D, respectively; the first and second terminals of the second inductor L2 are connected to the fifth node E and the fourth node D, respectively; the positive output terminal OUT+ and the negative output terminal OUT- of the DC / DC circuit are connected to the third node C and the fourth node D, respectively.

[0063] In a traditional three-level Buck TL circuit, the control strategy involves alternating conduction of Sa1 and Sa2, and Sa3 and Sa4. Therefore, at least two of the four switches (Sa1 to Sa4) bear the total input voltage at any given time, which is the sum of the voltages of Ci1 and Ci2. By alternating conduction of Sa1 and Sa2, the circuit can control the upper half of the output bus voltage, i.e., the voltage of Ci1; by alternating conduction of Sa3 and Sa4, the circuit can control the lower half of the output bus voltage, i.e., the voltage of Ci2. The sum of the voltages of Co1 and Co2 is the total output voltage of the circuit.

[0064] This application uses the negative terminal of the load being grounded as an example for illustration. It is also applicable to the neutral point grounding of the load. Figure 2 The midpoint of a three-level DC / DC circuit is the 0 terminal of the output.

[0065] In applications where the load is grounded at the negative terminal or the neutral point is grounded, when the positive input terminal IN+ of the DC / DC circuit is grounded, such as Figure 3 As shown, there will be a current path from the output positive terminal OUT+ to the input positive terminal IN+, as follows. Figure 3 As shown by the dashed line with arrows, the DC input capacitor Ci1 is grounded through its positive input terminal IN+, its negative output terminal OUT-, and short-circuited by the anti-parallel diodes L2 and Sa3. Similarly, Co1, Co2, and Load are grounded through the anti-parallel diodes L1 and Sa1, their positive input terminal IN+, and their negative output terminal OUT-. Because Ci1 is short-circuited, Ci2 and Sa4 will both bear the DC input voltage, making these two devices susceptible to overvoltage damage. Furthermore, when applied to electrolytic cells, the output capacitor and load may be discharged through an abnormal circuit, causing a momentary reverse discharge to the electrolytic cell, which can irreversibly damage materials such as the diaphragm.

[0066] To address the above technical problems, the solutions provided by embodiments of this application are described below with reference to the accompanying drawings. See also... Figure 4 The figure is a schematic diagram of another three-level DC / DC circuit provided in an embodiment of this application.

[0067] This application provides a three-level DC / DC circuit, including: an anti-reverse current device, a first input capacitor Ci1, a second input capacitor Ci2, a first switch Sa1, a second switch Sa2, a third switch Sa3, a fourth switch Sa4, a first inductor L1, a second inductor L2, a first output capacitor Co1, and a second output capacitor Co2.

[0068] Apart from the anti-backflow device, the connection relationships of other devices are already... Figure 3 The introduction will be provided separately, and will not be repeated here.

[0069] The anti-reverse current device is connected in the current path between the output positive terminal OUT+ and the input positive terminal IN+. The anti-reverse current device is turned off when the current direction is from the output positive terminal OUT+ to the input positive terminal IN+.

[0070] like Figure 4 As shown, the anti-backflow device can be connected to at least one of P1, P2, P3 and P4.

[0071] Figure 4 The above is merely illustrative. For example, if the anti-reverse current device is connected at position P2, it is between the first end of Ci1 and the first end of Sa1. It should be understood that the position of P2 can also be between the second end of Sa1 and the first end of L1. Similarly, if the anti-reverse current device is connected at position P3, it is between the second end of L1 and the first end of Co1. It should be understood that the position of P3 can also be between the first end of Sa2 and the first end of L1.

[0072] When the three-level DC / DC circuit is working normally, the anti-reverse current device conducts in the forward direction. When a ground fault occurs at the positive input terminal of the three-level DC / DC circuit, the anti-reverse current device cuts off in the reverse direction.

[0073] The three-level DC / DC circuit provided in this application embodiment does not specifically limit the specific type of anti-reverse current device. It can be set according to actual needs, as long as it can cut off the current path from the output positive terminal to the input positive terminal. For example, the anti-reverse current device can be at least one of the following:

[0074] Diodes, semi-controlled semiconductor devices, or fully controlled semiconductor devices;

[0075] When the anti-reverse current device is a semi-controlled semiconductor device or a fully controlled semiconductor device, the DC / DC circuit also includes: a controller (not shown in the figure); for example, the controller can be implemented by a microcontroller or MCU, or by other control chips.

[0076] The controller is electrically connected to a semi-controlled semiconductor device or a fully controlled semiconductor device;

[0077] A controller is used to control the switching state of semi-controlled or fully controlled semiconductor devices.

[0078] Fully controllable semiconductor devices can be any of the following: Insulated-Gate Bipolar Transistor (IGBT), Integrated Gate-Commutated Thyristor (IGCT), Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), or Silicon Carbide (SiC). Semi-controllable semiconductor devices can be silicon controlled rectifiers (SCRs), i.e., thyristors.

[0079] The controller is electrically connected to a semi-controlled or fully controlled semiconductor device and controls the switching state of the semi-controlled or fully controlled semiconductor device. That is, when the three-level DC / DC circuit is working normally, the controller controls the semi-controlled or fully controlled semiconductor device to conduct in the forward direction. When the input positive terminal is grounded, the semi-controlled or fully controlled semiconductor device is automatically disconnected.

[0080] For example, a diode can be used as an anti-reverse current device, and the diode can be connected in... Figure 4 At least one of P1-P4, for example, when a diode is connected at P1, the anode of the diode is connected to the positive input terminal IN+, and the cathode of the diode is connected to the first terminal of the first input capacitor Ci1. When the positive input terminal IN+ is grounded, even if current flows from the positive output terminal OUT+ to the positive input terminal IN+, the current path can be blocked due to the reverse cutoff characteristic of the diode, thereby protecting the devices in the three-level DC / DC circuit.

[0081] The advantage of using diodes in reverse current protection devices is that no control is required. Diodes can automatically achieve reverse cutoff and can quickly respond and provide protection when a ground fault occurs at the input positive terminal.

[0082] In one possible implementation, the three-level DC / DC circuit provided in this application, when the anti-reverse current device is a semi-controlled semiconductor device or a fully controlled semiconductor device, further includes: a detection device (not shown in the figure); the detection device is electrically connected to the positive input terminal and the controller, and the detection device is used to detect a ground fault at the positive input terminal, and the controller reports the fault; the controller is used to control the fully controlled semiconductor device with bidirectional current flow to disconnect; for example, the fully controlled semiconductor device with unidirectional current flow can be an IGBT. The fully controlled semiconductor device with bidirectional current flow can be a MOS.

[0083] When a ground fault occurs at the positive input terminal, the semi-controlled or fully controlled semiconductor device with unidirectional current flow will automatically shut off.

[0084] The controller is also used to control the conduction of a semi-controlled semiconductor device or a fully controlled semiconductor device when no ground fault occurs at the positive input terminal. For example, the detection device can detect the voltage at the positive input terminal and send the voltage of the positive input terminal to ground to the controller; when the positive input terminal is grounded, the voltage will drop significantly, even to 0V. The controller is used to control the semi-controlled semiconductor device or the fully controlled semiconductor device to disconnect when it determines that a ground fault has occurred at the positive input terminal based on the voltage of the positive input terminal to ground.

[0085] The following examples illustrate several specific implementation methods for connecting anti-reverse current devices in different locations.

[0086] See Figure 5 The three-level DC / DC circuit provided in this application embodiment has an anti-reverse current device connected between the input positive terminal IN+ and the first node A.

[0087] See Figure 6 The three-level DC / DC circuit provided in this application embodiment has an anti-reverse current device connected between the first node A and the second node B.

[0088] See Figure 7 The three-level DC / DC circuit provided in this application embodiment has an anti-reverse current device connected between the second node B and the third node C.

[0089] See Figure 8 In the three-level DC / DC circuit provided in this application embodiment, the anti-reverse current device is connected between the third node C and the output positive terminal OUT+.

[0090] Furthermore, the three-level DC / DC circuit provided in this application does not specifically limit the types of the first to fourth switching transistors; they can be fully controllable semiconductor devices capable of controlling turn-on and turn-off, and also include anti-parallel diodes. For specific types of fully controllable semiconductor devices, please refer to the above description.

[0091] Furthermore, in the three-level Buck TL circuit provided in this application embodiment, when the voltage of the first input capacitor and the voltage of the second input capacitor are severely uneven, under normal circumstances the voltage of the first input capacitor and the voltage of the second input capacitor are equal, and the voltage borne by the second input capacitor, the third switch, and the fourth switch will be greater than half of the DC input voltage, which may exceed their tolerance range and cause them to be damaged.

[0092] Therefore, the three-level DC / DC circuit provided in this application, in order to solve the technical problem of voltage imbalance between the first input capacitor and the second input capacitor, further includes: an overvoltage protection device connected to the current path between the output negative terminal and the input negative terminal of the DC / DC circuit. The overvoltage protection device includes a fully controllable semiconductor device, the specific type of which can be found in the above description. The fully controllable semiconductor device disconnects when the voltage of the first input capacitor and the voltage of the second input capacitor are unbalanced. A detailed description follows with reference to the accompanying drawings.

[0093] See Figure 9 The figure is a schematic diagram of another three-level DC / DC circuit provided in an embodiment of this application.

[0094] The detection device in the three-level DC / DC circuit provided in this application embodiment is also used to detect the voltage of the first input capacitor and the voltage of the second input capacitor to determine whether a voltage imbalance occurs, the current of the first inductor and the current of the second inductor to determine whether a voltage imbalance occurs, or the current of the positive output terminal and the current of the negative output terminal to determine whether a voltage imbalance occurs.

[0095] Overvoltage protection devices can be connected to Figure 9 At least one of P5-P9 in the circuit. When the voltages of the two input capacitors are balanced, the overvoltage protection device is turned on; when the voltages of the two input capacitors are unbalanced, the overvoltage protection device needs to be turned off to block the overvoltage path.

[0096] The specific locations of several overvoltage protection devices are described below with reference to the attached diagram.

[0097] See Figure 10 The figure is a schematic diagram of the overvoltage protection device provided in the embodiment of this application located at P5.

[0098] The three-level DC / DC circuit provided in this application embodiment has an overvoltage protection device connected between the negative input IN- and the sixth node F, i.e., at position P5.

[0099] See Figure 11 The figure is a schematic diagram of the overvoltage protection device provided in the embodiment of this application located at P6.

[0100] The three-level DC / DC circuit provided in this application embodiment has an overvoltage protection device connected between the sixth node F and the midpoint O, i.e., at position P6; it should be understood that... Figure 11 P6 is above Ci2; alternatively, P6 can also be below Ci2.

[0101] See Figure 12 The figure is a schematic diagram of the overvoltage protection device provided in the embodiment of this application located at P7.

[0102] The three-level DC / DC circuit provided in this application embodiment has the overvoltage protection device connected between the midpoint O and the fifth node E, i.e., at position P7; it should be understood that... Figure 12 P7 is above Sa3; alternatively, P7 can also be below Sa3.

[0103] See Figure 13 The figure is a schematic diagram of the overvoltage protection device provided in the embodiment of this application located at P8.

[0104] The three-level DC / DC circuit provided in this application embodiment has an overvoltage protection device connected between the fifth node E and the fourth node D, i.e., at position P8. It should be understood that... Figure 13 P8 is to the right of L2. Alternatively, P8 can also be to the left of L2.

[0105] See Figure 14 The figure is a schematic diagram of the overvoltage protection device located at P9 according to an embodiment of this application.

[0106] The three-level DC / DC circuit provided in this application embodiment has an overvoltage protection device connected between the fourth node D and the output negative terminal OUT-, i.e., at position P9.

[0107] See Figure 15 The figure is a schematic diagram of the fully controlled semiconductor device located at P9 according to an embodiment of this application. Figure 15 The diagram shows an overvoltage protection device at position P9, using the fully controlled semiconductor device Sa5 as an example.

[0108] Based on the three-level DC / DC circuit provided in the above embodiments, this application also provides a power supply system, which will be described in detail below with reference to the accompanying drawings.

[0109] See Figure 16 The figure is a schematic diagram of a power supply system provided in an embodiment of this application.

[0110] The power supply system provided in this application embodiment includes the three-level DC / DC circuit described in the above embodiments, and also includes: an electrolytic cell 200;

[0111] The positive output of the three-level DC / DC circuit is connected to the positive terminal of the electrolytic cell 200, and the negative output of the three-level DC / DC circuit is connected to the negative terminal of the electrolytic cell 200. The negative terminal or midpoint of the electrolytic cell 200 is grounded.

[0112] Electrolytic cell 200 can be an alkaline electrolytic cell. Taking the negative electrode grounding of electrolytic cell 200 as an example, it can also be grounded at the midpoint.

[0113] Because the three-level DC / DC circuit has anti-reverse current devices at at least one of the P1-P4 positions, when the positive input IN+ is grounded, the current path from the positive terminal of the electrolytic cell to the positive input IN+ of the three-level DC / DC circuit is cut off, thereby protecting the devices in the three-level DC / DC circuit.

[0114] See also Figure 16 The three-level DC / DC circuit provided in this application embodiment can also be equipped with an overvoltage protection device at at least one of the P5-P9 positions. When the voltage of the first input capacitor and the second input capacitor is unbalanced, the overvoltage protection device is controlled to disconnect, blocking the overvoltage path, thereby protecting the devices in the three-level DC / DC circuit.

[0115] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems or apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0116] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A three-level DC / DC circuit, characterized in that, include: Anti-reverse current device, first input capacitor, second input capacitor, first switching transistor, second switching transistor, third switching transistor, fourth switching transistor, first inductor, second inductor, first output capacitor and second output capacitor; The first end and the second end of the first input capacitor are respectively connected to the first node and the midpoint, the positive input of the DC / DC circuit is connected to the first node, and the first end and the second end of the second input capacitor are respectively connected to the midpoint and the sixth node. The first end and the second end of the first switch are respectively connected to the first node and the second node; the first end and the second end of the second switch are respectively connected to the second node and the midpoint; the first end and the second end of the third switch are respectively connected to the midpoint and the fifth node; and the first end and the second end of the fourth switch are respectively connected to the fifth node and the sixth node. The first and second ends of the first inductor are respectively connected to the second node and the third node; the first and second ends of the first output capacitor are respectively connected to the third node and the midpoint; the first and second ends of the second output capacitor are respectively connected to the midpoint and the fourth node; the first and second ends of the second inductor are respectively connected to the fifth node and the fourth node; the positive and negative output terminals of the DC / DC circuit are respectively connected to the third node and the fourth node. The anti-reverse current device is connected in the current path between the output positive terminal and the input positive terminal. The anti-reverse current device is turned off when the current direction is from the output positive terminal to the input positive terminal.

2. The three-level DC / DC circuit according to claim 1, characterized in that, The anti-backflow device is at least one of the following: Diodes, semi-controlled semiconductor devices, or fully controlled semiconductor devices.

3. The three-level DC / DC circuit according to claim 2, characterized in that, When the anti-reverse current device is the semi-controlled semiconductor device or the fully controlled semiconductor device, the DC / DC circuit further includes: a controller; The controller is electrically connected to the semi-controlled semiconductor device or the fully controlled semiconductor device; The controller is used to control the switching state of the semi-controlled semiconductor device or the fully controlled semiconductor device.

4. The three-level DC / DC circuit according to claim 2, characterized in that, The DC / DC circuit further includes: an overvoltage protection device connected in the current path between the output negative terminal and the input negative terminal of the DC / DC circuit, the overvoltage protection device including a fully controllable semiconductor device, the overvoltage protection device being controlled to conduct when the current direction is from the output negative terminal to the input negative terminal during normal operation; the fully controllable semiconductor device being disconnected when the input positive terminal is short-circuited to ground.

5. The three-level DC / DC circuit according to claim 3, characterized in that, When the anti-reverse current device is the semi-controlled semiconductor device or the fully controlled semiconductor device, the DC / DC circuit further includes: a detection device; The detection device is used to detect the input positive terminal to ground voltage and send the input positive terminal to ground voltage to the controller; The controller is used to report a fault when a ground fault occurs at the input positive terminal based on the voltage to ground of the input positive terminal; the controller is also used to control the fully controlled semiconductor device with bidirectional current flow to disconnect. When a ground fault occurs at the positive input terminal, the semi-controlled semiconductor device or the fully controlled semiconductor device with unidirectional current flow will automatically shut off. The controller is also used to control the semi-controlled semiconductor device or the fully controlled semiconductor device to conduct when there is no grounding fault at the positive input terminal.

6. The three-level DC / DC circuit according to claim 5, characterized in that, The detection device is further configured to detect the voltage of the first input capacitor and the voltage of the second input capacitor to determine whether the voltage imbalance occurs, the current of the first inductor and the current of the second inductor to determine whether the voltage imbalance occurs, or the current of the positive output terminal and the current of the negative output terminal to determine whether the voltage imbalance occurs.

7. The three-level DC / DC circuit according to any one of claims 1-6, characterized in that, The anti-reverse current device is connected between the positive input terminal and the first node.

8. The three-level DC / DC circuit according to any one of claims 1-6, characterized in that, The anti-backflow device is connected between the first node and the second node.

9. The three-level DC / DC circuit according to any one of claims 1-6, characterized in that, The anti-backflow device is connected between the second node and the third node.

10. The three-level DC / DC circuit according to any one of claims 1-6, characterized in that, The anti-reverse current device is connected between the third node and the output positive terminal.

11. The three-level DC / DC circuit according to any one of claims 4-6, characterized in that, The overvoltage protection device is connected between the negative input terminal and the sixth node.

12. The three-level DC / DC circuit according to any one of claims 4-6, characterized in that, The overvoltage protection device is connected between the sixth node and the midpoint.

13. The three-level DC / DC circuit according to any one of claims 4-6, characterized in that, The overvoltage protection device is connected between the midpoint and the fifth node.

14. The three-level DC / DC circuit according to any one of claims 4-6, characterized in that, The overvoltage protection device is connected between the fifth node and the fourth node.

15. The three-level DC / DC circuit according to any one of claims 4-6, characterized in that, The overvoltage protection device is connected between the fourth node and the output negative terminal.

16. A power supply system, characterized in that, The circuit includes the three-level DC / DC circuit according to any one of claims 1-15, and further includes: an electrolytic cell; The positive output of the three-level DC / DC circuit is connected to the positive terminal of the electrolytic cell, and the negative output of the three-level DC / DC circuit is connected to the negative terminal of the electrolytic cell. The negative terminal of the electrolytic cell is grounded or the midpoint of the electrolytic cell is grounded.

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