Programmable gain amplifier

Abstract

The application discloses a programmable gain amplifier. It comprises a first differential amplifier circuit, a second differential amplifier circuit, a first group of switches, a second group of switches and an offset calibration circuit. The first group of switches is used for selectively coupling a group of inputs of the first differential amplifier circuit with a bias voltage source during a first stage of offset calibration of the programmable gain amplifier. The second group of switches is used for selectively coupling a group of outputs of the second differential amplifier circuit with the offset calibration circuit during the first stage. The offset calibration circuit is used for obtaining a compensation current by using a successive approximation comparison based on an output signal of the second differential amplifier circuit during the first stage, and performing feedback calibration on an offset voltage of the programmable gain amplifier according to the obtained compensation current. The influence of the offset voltage of an operational amplifier and a gain resistor in a front-stage amplifier circuit on detection precision can be effectively reduced, and the ADC front-end amplifier circuit can be applicable to high-precision detection.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more specifically, to a programmable gain amplifier. Background Technology

[0002] Gain amplifiers are crucial circuit modules widely used in analog / mixed-signal integrated circuit design, such as analog front-ends (AFEs), ADC converters, and DC / DC converters. They often play a key role in the entire analog / mixed-signal integrated circuit, providing gain to amplify the input signal. Because the signals to be amplified in high-precision sensor measurements are generally very weak, the pre-amplified PGA (programmable gain amplifier) ​​must have the lowest possible offset voltage.

[0003] Traditional variable gain amplifiers (PGA) eliminate offset voltage by chopping the operational amplifier within the PGA. However, this method has drawbacks: it only chops the operational amplifier, eliminating its offset voltage, but not the offset voltage of the gain resistor. Furthermore, chopping requires a notch filter to eliminate ripple, increasing circuit complexity. If autozeroing is used to calibrate the amplifier's offset voltage, a large zero-adjustment capacitor is needed, increasing circuit size. Otherwise, after prolonged ADC conversion, capacitor leakage can increase measurement errors. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a programmable gain amplifier that can effectively reduce the impact of offset voltage on detection accuracy in the preamplifier circuit.

[0005] According to an embodiment of the present invention, a programmable gain amplifier is provided for amplifying an input signal via a pair of series-coupled differential amplifier circuits. The programmable gain amplifier includes: a first differential amplifier circuit including a set of inputs and a set of outputs; a second differential amplifier circuit including a set of inputs and a set of outputs; a first set of switches for selectively coupling a set of inputs of the first differential amplifier circuit to a bias voltage source during a first stage of offset calibration of the programmable gain amplifier; and a second set of switches for selectively coupling a set of outputs of the second differential amplifier circuit to an offset calibration circuit during the first stage. The offset calibration circuit is used to obtain a compensation current based on the output signal of the second differential amplifier circuit during the first stage using a successive approximation comparison, and to perform feedback calibration of the offset voltage of the programmable gain amplifier based on the compensation current.

[0006] Optionally, the programmable gain amplifier further includes a first set of gain resistors configured to be coupled between the output side of the first set of switches and the corresponding input of the first differential amplifier circuit.

[0007] Optionally, the programmable gain amplifier further includes a third set of switches for coupling the input side of the first set of gain resistors to the corresponding input signal during the second stage of signal amplification by the programmable gain amplifier.

[0008] Optionally, the programmable gain amplifier further includes: a second set of gain resistors having a first terminal coupled to a corresponding input of the first differential amplifier circuit; a fourth set of switches for selectively coupling a second terminal of the second set of gain resistors to a common-mode voltage source during the first phase; and a fifth set of switches for selectively coupling a second terminal of the second set of gain resistors to a corresponding output side of the second differential amplifier circuit during a second phase of signal amplification by the programmable gain amplifier.

[0009] Optionally, the programmable gain amplifier further includes a set of Miller capacitors configured to be coupled between the respective output and the respective input of the second differential amplifier circuit during the second stage of signal amplification by the programmable gain amplifier.

[0010] Optionally, the programmable gain amplifier further includes a sixth set of switches for selectively coupling the set of outputs of the second differential amplifier circuit to the input side of the ADC during the second stage of signal amplification by the programmable gain amplifier.

[0011] Optionally, the input signal includes an inverted input signal and a non-inverted input signal, and the bias voltage source is an intermediate signal between the inverted input signal and the non-inverted input signal.

[0012] Optionally, the offset calibration circuit includes: a current-mode DAC having an output coupled to a reference node between the first differential amplifier circuit and the second differential amplifier circuit; a comparator having a first input coupled to the non-inverting output signal of the second differential amplifier circuit and a second input coupled to the inverting output signal of the second differential amplifier circuit; and a SAR logic control module for controlling the switching of the current-mode DAC according to the output result of the comparator, adjusting the current value of the compensation current in a successive approximation manner until quantization is completed.

[0013] Optionally, the SAR logic control module is further configured to control the current-mode DAC to draw current from or inject current into the reference node based on the comparison result between the non-inverting output signal and the inverting output signal.

[0014] Optionally, when the comparison result indicates that the non-inverting output signal is less than the inverting output signal, the SAR logic control module outputs a first control signal to control the current-type DAC to inject current into the reference node; when the comparison result indicates that the non-inverting output signal is greater than the inverting output signal, the SAR logic control module outputs a second control signal to control the current-type DAC to draw current from the reference node.

[0015] Optionally, the current-type DAC includes: M first current branches and second current branches, where M is an integer greater than 1. Each first current branch and second current branch is coupled between the power supply voltage and ground, and their center taps are coupled to the reference node.

[0016] Optionally, each of the M first current branches is provided with a first switch, which is controlled to be turned on and off by the first control signal; and each of the M second current branches is provided with a second switch, which is controlled to be turned on and off by the second control signal.

[0017] Optionally, the currents of the M first current branches and the second current branches are increased in a binary weighted manner.

[0018] Optionally, the first control signal and the second control signal include M-bit binary digital signals.

[0019] In summary, the programmable gain amplifier proposed in this embodiment connects the pre-amplifier circuit into an open-loop state via an internal switch before each ADC conversion. A compensation current is obtained through a successive approximation comparison method using an offset calibration circuit. Then, during normal ADC conversion, the obtained compensation current is provided to the PGA, thereby compensating for the offset voltage. This overcomes the shortcomings of traditional chopper offset elimination techniques, which cannot calibrate the offset caused by the gain resistor, and offers advantages such as fast and accurate response. Furthermore, the offset calibration circuit of this invention uses a binary weighted current-type DAC for calibration, featuring a large calibration range and high accuracy. Moreover, the offset calibration circuit used in this invention has the advantages of simple structure, smaller area, and easy integration, making it suitable for high-precision detection ADC front-end amplifier circuits. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic circuit diagram of a programmable gain amplifier according to an embodiment of the present invention is shown;

[0022] Figure 2 The following are signal timing diagrams of different stages of a programmable gain amplifier according to an embodiment of the present invention;

[0023] Figure 3 A schematic circuit diagram of a current-mode DAC in a programmable gain amplifier according to an embodiment of the present invention is shown. Detailed Implementation

[0024] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0025] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "coupled to" another element or "coupled between" two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly coupled to" another element, it means that there are no intermediate elements between them.

[0026] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] Figure 1 A schematic circuit diagram of a programmable gain amplifier 100 according to an embodiment of the present invention is shown. Figure 2 The following diagram illustrates the signal timing of different stages of a programmable gain amplifier 100 according to an embodiment of the present invention. Figure 2 The signals P1 and P2 shown can be generated by the controller in response to an external timing signal (e.g., a clock signal). The controller may include digital circuitry and / or may be implemented by a machine or computer.

[0028] like Figure 1 As shown, the programmable gain amplifier 100 of this embodiment includes a first differential amplifier circuit GM1 110 and a second differential amplifier circuit GM2 120 connected in series, a first set of gain resistors, a second set of gain resistors, a set of Miller capacitors, and an offset calibration circuit 130.

[0029] like Figure 2 As shown, the operation of the programmable gain amplifier 100 in this embodiment has two stages: an offset calibration stage when signal P1 is at a logic high value and a signal amplification stage when signal P2 is at a logic high value.

[0030] The first set of gain resistors includes gain resistors R1 and R2, which are selectively coupled between the bias voltage source VA and the corresponding inputs of the first differential amplifier circuit GM1 110 during the offset calibration phase, and selectively coupled between the input signals (differential input signals VIN / VIP, respectively) and the corresponding inputs of the first differential amplifier circuit GM1 110 during the signal amplification phase. Specifically, switches 101 and 102 are respectively configured according to... Figure 2 The switch control signals P1 and P2 shown dynamically switch the first terminals of gain resistors R1 and R2 between the differential input signal VIN / VIP and the bias voltage source VA. For example, switch 102 can be active during the offset calibration phase to provide electrical connection, and deactivated during the signal amplification phase; simultaneously, switch 101 can be deactivated during the offset calibration phase, and active during the signal amplification phase to provide electrical connection.

[0031] The second set of gain resistors, including gain resistors R3 and R4, are selectively coupled between the common-mode voltage source VCM and the corresponding inputs of the first differential amplifier circuit GM1 110 during the offset calibration phase, and between the corresponding inputs of the first differential amplifier circuit GM1 110 and the corresponding outputs of the second differential amplifier circuit GM2 120 during the signal amplification phase. Specifically, switches 104 and 104' are respectively configured according to... Figure 2 The switch control signals P1 and P2 shown dynamically switch the gain resistors R3 and R4 between the two states mentioned above. For example, switch 104' can be active during the offset calibration phase to provide electrical connection, and active during the signal amplification phase to provide electrical connection; switch 104 can be active during the offset calibration phase to provide electrical connection.

[0032] A set of Miller capacitors, including Miller capacitors C1 and C2, are used as compensation capacitors coupled between the differential outputs (differential outputs OUTP and OUTN, respectively) and differential inputs of the second differential amplifier circuit GM2 120 during the signal amplification phase. Specifically, switch 103 can be activated during the signal amplification phase to provide an electrical connection, thereby coupling Miller capacitors C1 and C2 between the differential outputs and differential inputs of the second differential amplifier circuit GM2 120, respectively.

[0033] A set of switches 105 is used to couple the differential outputs OUTP / OUTN of the second differential amplifier circuit GM2 120 to the input side of the ADC converter (Analog to Digital Converter) 140. For example, switches 105 can be active during the signal amplification phase to provide an electrical connection, thereby coupling the differential outputs of the second differential amplifier circuit GM2 120 to the input side of the ADC converter 140.

[0034] A set of switches 106 is used to connect the differential output of the second differential amplifier circuit GM2 120 to the input of the offset calibration circuit 130 during the offset calibration phase. The offset calibration circuit 130 is used during the offset calibration phase to obtain a compensation current based on the output signal of the second differential amplifier circuit GM2 120 using successive approximation comparison, and to perform feedback calibration on the offset voltage of the programmable gain amplifier 100 according to the compensation current, thereby improving the accuracy of the programmable gain amplifier 100.

[0035] like Figure 1 As shown, the offset calibration circuit 130 includes a comparator 131, a SAR (Successive Approximation Register) logic control module 132, and a current-mode DAC (Digital to Analog Converter) 133. The inverting input of comparator 131 is coupled to the output OUTN of the second differential amplifier circuit GM2 120 via one of the switches 106, and the non-inverting input of comparator 131 is coupled to the output OUTP of the second differential amplifier circuit GM2 120 via the other of the switches 106. The output of comparator 131 is coupled to the input of the SAR logic control module 132. The output of the SAR logic control module 132 is coupled to the input of the current-mode DAC 133, and the output of the current-mode DAC 133 is coupled to the reference node 108 between the first differential amplifier circuit GM1 110 and the second differential amplifier circuit GM2 120. The SAR logic control module 132 is used to control the switching of the current-type DAC 133 according to the output of the comparator 131, and adjust the current value of the compensation current in a successive approximation manner until the quantization ends. Then, during the signal amplification stage, the current-type DAC 133 sends the obtained compensation current Is to the programmable gain amplifier 100 to achieve compensation for the offset voltage.

[0036] In some embodiments, the SAR logic control module 132 is further configured to control the current-type DAC 133 to draw current from or inject current into the reference node 108 based on the comparison result between the outputs OUTP and OUTN of the second differential amplifier circuit GM2 120. For example, when the differential output OUTP of the second differential amplifier circuit GM2 120 is at a logic low level and OUTN is at a logic high level, the comparator 131 outputs a logic low level "0", and the SAR logic control module 132 outputs a first control signal SP to the current-type DAC 133 to control the current-type DAC 133 to inject current into the reference node 108; when the differential output OUTP of the second differential amplifier circuit GM2 120 is at a logic high level and OUTN is at a logic low level, the comparator 131 outputs a logic high level "1", and the SAR logic control module 132 outputs a second control signal SN to the current-type DAC 133 to control the current-type DAC 133 to draw current from the reference node 108.

[0037] Figure 3 A schematic circuit diagram of a current-mode DAC in a programmable gain amplifier according to an embodiment of the present invention is shown. Figure 3 As shown, the current-type DAC 133 of this embodiment includes M first current branches and second current branches (M is an integer greater than 1), wherein the first current branches and second current branches are connected sequentially between the power supply voltage AVDD and ground AGND, and the middle taps of the M first current branches and second current branches are connected to each other to output compensation current Is.

[0038] The first current branch consists of a first current source and a corresponding first switch (e.g., current sources I0 to I1). m and switches S0~S m ), where the current source I0~I m The currents increase in binary weights, namely I0, 2×I0, ..., 2 m-2 ×I0、2 m -1 ×I0, switch S0~S m The on and off states are controlled by M-bit binary digital signals SP. <m:0>.

[0039] The second current branch consists of a second current source and a corresponding second switch (e.g., current source I0'~I...). m 'and switch S0'~S m '), where the current source I0'~I m The currents of ' are increased according to binary weights, namely I0', 2×I0', ..., 2 m-2 ×I0'、2 m-1 ×I0', switch S0'~S m The on and off states of ' are controlled by M-bit binary digital signals SN. <m:0>.

[0040] Among them, control signal SP <m:0>and SN <m:0>This is denoted as the control word for the current-mode DAC 133. As mentioned earlier, during each offset calibration phase, the gain resistor in the programmable gain amplifier and the offset voltage of the operational amplifier will cause the differential outputs OUTP / OUTN to be high and low, respectively. The SAR logic control module 132 determines the output control signal SP based on the logic "0" or "1" output by the comparator 131. <m:0>Or output control signal SN <m:0>When comparator 131 outputs logic "0", SAR logic control module 132 sequentially outputs control signal SP. <m:0>To control switches S0 to S m When the comparator 131 outputs logic "1", the SAR logic control module 132 sequentially outputs control signal SN. <m:0>To control switches S0' to S m 'Connected'.

[0041] Taking the initial output of comparator 131 as logic "1" as an example, the SAR logic control module 132 outputs a valid control signal SP at this time. <m:0>The successive approximation comparison process in this embodiment is as follows: the current-type DAC 133 is compared and adjusted bit by bit from the high bit to the low bit. First, the control signal SP is set. <m:0>=<100…0>, meaning the highest control bit of the control signal SP is set to 1, and the remaining (M-1) bits are all 0. At this time, switch S m When the circuit is turned on, the compensation current Is = I m If the output of comparator 131 does not change at this time, then switch S m Maintain the on state, that is, keep SP. <m>=1; if the output of comparator 131 flips at this time, it will cause switch S to... m Off, i.e., SP <m>=0. Then set the control signal SP. <m-1>=1, repeat the previous operation, and obtain SP based on the comparator output. <m-1>The state is then determined. This process continues for M+1 comparisons to obtain the final state of all control bits in the control signal SP. By gradually changing one or two control bits, the misalignment or redundancy problems that occur during DC offset voltage calibration can be effectively resolved, ensuring accurate calibration of the DC offset voltage.

[0042] After the successive approximation comparison is completed, during the signal amplification stage of the ADC conversion, switches 101, 103, 104, and 105 are turned on, while switches 102, 104', and 106 are turned off. At this time, the current-mode DAC 133 calculates the signal based on the SP obtained during the offset calibration stage. <m:0>All control words connect the compensation current Is to the reference node 108, which cancels the offset voltage inside the programmable gain amplifier 100, thereby achieving the purpose of offset calibration.

[0043] In summary, the programmable gain amplifier proposed in this embodiment connects the pre-amplifier circuit into an open-loop state via an internal switch before each ADC conversion. A compensation current is obtained through a successive approximation comparison method using an offset calibration circuit. Then, during normal ADC conversion, the obtained compensation current is provided to the PGA, thereby compensating for the offset voltage. This overcomes the shortcomings of traditional chopper offset elimination techniques, which cannot calibrate the offset caused by the gain resistor, and offers advantages such as fast and accurate response. Furthermore, the offset calibration circuit of this invention uses a binary weighted current-type DAC for calibration, featuring a large calibration range and high accuracy. Moreover, the offset calibration circuit used in this invention has the advantages of simple structure, smaller area, and easy integration, making it suitable for high-precision detection ADC front-end amplifier circuits.

[0044] Those skilled in the art will understand that the terms "during," "when," and "when…" used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the commencement of a startup action, but rather that there may be some small but reasonable delay, such as various propagation delays, between the startup action and the reaction action initiated by it. The terms "approximately" or "substantially" used herein mean that an element value is expected to be close to the declared value or position. However, as is well known in the art, there are always small deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.

[0045] Furthermore, it should be noted that relational terms such as "first" and "second" used herein are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0046] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention. < / m> < / m>

Claims

1. A programmable gain amplifier for amplifying an input signal via a pair of series-coupled differential amplifier circuits, the programmable gain amplifier comprising: The first differential amplifier circuit includes a set of inputs and a set of outputs; The second differential amplifier circuit includes a set of inputs and a set of outputs, wherein a set of inputs of the second differential amplifier circuit is coupled to a set of outputs of the first differential amplifier circuit. The first set of switches is used to selectively couple a set of inputs of the first differential amplifier circuit to a bias voltage source during the offset calibration phase. The second set of switches is used to selectively couple one set of outputs of the second differential amplifier circuit to the offset calibration circuit during the offset calibration phase. The offset calibration circuit is used during the offset calibration phase to obtain a compensation current based on the output signal of the second differential amplifier circuit using successive approximation comparison, and to perform feedback calibration on the offset voltage of the programmable gain amplifier based on the compensation current. The offset calibration circuit includes: A current-mode DAC having an output coupled to a reference node between the first differential amplifier circuit and the second differential amplifier circuit; The comparator has a first input terminal coupled to the non-inverting output signal of the second differential amplifier circuit and a second input terminal coupled to the inverting output signal of the second differential amplifier circuit; The SAR logic control module is used to control the switching of the current-type DAC according to the output result of the comparator, and adjust the current value of the compensation current in a successive approximation manner until the quantization is completed.

2. The programmable gain amplifier according to claim 1, wherein, Also includes: A first set of gain resistors is configured to be coupled between the output side of the first set of switches and the corresponding input of the first differential amplifier circuit.

3. The programmable gain amplifier according to claim 2, wherein, Also includes: The third set of switches is used to couple the input side of the first set of gain resistors to the corresponding input signal during the signal amplification stage.

4. The programmable gain amplifier according to claim 1, wherein, Also includes: The second set of gain resistors has a first terminal coupled to the corresponding input of the first differential amplifier circuit; A fourth set of switches is used to selectively couple the second terminal of the second set of gain resistors to a common-mode voltage source during the offset calibration phase. as well as The fifth set of switches is used to selectively couple the second terminal of the second set of gain resistors to the corresponding output side of the second differential amplifier circuit during the signal amplification stage.

5. The programmable gain amplifier according to claim 1, wherein, Also includes: A set of Miller capacitors is configured to be coupled between the respective output and the respective input of the second differential amplifier circuit during the signal amplification stage.

6. The programmable gain amplifier according to claim 1, wherein, Also includes: The sixth set of switches is used to selectively couple the output of the second differential amplifier circuit to the input side of the ADC during the signal amplification stage.

7. The programmable gain amplifier according to claim 1, wherein, The input signal includes an inverted input signal and a non-inverted input signal, and the bias voltage source is an intermediate signal between the inverted input signal and the non-inverted input signal.

8. The programmable gain amplifier according to claim 1, wherein, The SAR logic control module is also used to control the current-type DAC to draw current from or inject current into the reference node based on the comparison result between the non-inverting output signal and the inverting output signal.

9. The programmable gain amplifier according to claim 8, wherein, When the comparison result indicates that the non-inverting output signal is less than the inverting output signal, the SAR logic control module outputs a first control signal to control the current-type DAC to inject current into the reference node. When the comparison result indicates that the non-inverting output signal is greater than the inverting output signal, the SAR logic control module outputs a second control signal to control the current-type DAC to draw current from the reference node.

10. The programmable gain amplifier according to claim 9, wherein, The current-mode DAC includes: There are M first current branches and second current branches, where M is an integer greater than 1. Each first current branch and second current branch is coupled between the power supply voltage and ground, and their center taps are coupled to the reference node.

11. The programmable gain amplifier according to claim 10, wherein, Each of the M first current branches is provided with a first switch, which is controlled to be turned on and off by the first control signal. Each of the M second current branches is provided with a second switch, which is controlled to be turned on and off by the second control signal.

12. The programmable gain amplifier according to claim 10, wherein, The currents in the M first current branches and the second current branches are increased according to binary weighting.

13. The programmable gain amplifier according to claim 11, wherein, The first control signal and the second control signal both comprise M-bit binary digital signals.

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