A switching circuit, a power management circuit, a chip and an electronic device

Abstract

Embodiments of the present application provide a switching circuit, a power management circuit, a chip and an electronic device, wherein the switching circuit comprises: a first MOS tube, a first end of the first MOS tube being connected to an input port, a body diode of the first MOS tube being a first body diode, an anode of the first body diode being connected to the first end of the first MOS tube, and a cathode of the first body diode being connected to a second end of the first MOS tube; a second MOS tube, a first end of the second MOS tube being used for outputting a second signal, a second end of the second MOS tube being connected to the second end of the first MOS tube, a body diode of the second MOS tube being a second body diode, an anode of the second body diode being connected to the first end of the second MOS tube, and a cathode of the second body diode being connected to the second end of the second MOS tube; and a switch module, the switch module being connected to a control end of the first MOS tube and a control end of the second MOS tube, and the switch module being used for controlling conduction or disconnection of the first MOS tube and the second MOS tube. In the foregoing manner, the switching circuit can be prevented from leaking electricity, and circuit safety can be improved.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a switching circuit, a power management circuit, a chip, and an electronic device. Background Technology

[0002] Power management circuits are typically used in Battery Management System (BMS) chips. The BMS chip is installed inside electronic devices to manage the charging and discharging of the device's battery. When the electronic device is connected to an adapter, the adapter charges the battery, generating either VBUS voltage or PACK voltage (the voltages corresponding to the two different adapters). The chip can select one of these voltages—VBUS, PACK, or the battery voltage VBAT—to power its internal modules. The design of the high-voltage switch is particularly important when selecting between VBUS, PACK, and VBAT. Summary of the Invention

[0003] This application provides a switching circuit, a power management circuit, a chip, and an electronic device that can prevent leakage current in the switching circuit and improve circuit safety.

[0004] This application provides a switching circuit, characterized in that the switching circuit includes: a first MOSFET, the first end of which is connected to an input port, the body diode of which is a first body diode, the anode of which is connected to the first end of the first MOSFET, and the cathode of which is connected to the second end of the first MOSFET; a second MOSFET, the first end of which is used to output a second signal, the second end of which is connected to the second end of the first MOSFET, the body diode of which is a second body diode, the anode of which is connected to the first end of the second MOSFET, and the cathode of which is connected to the second end of the second MOSFET; and a switching module, which is connected to the control terminals of the first MOSFET and the second MOSFET, and is used to control the first MOSFET and the second MOSFET to be turned on or off.

[0005] This application also provides a power management circuit, which includes a high-voltage switch, and the high-voltage switch includes the switching circuit described above.

[0006] This application also provides a chip that includes the power management circuit described above.

[0007] This application also provides an electronic device, which includes: a battery; a charging interface; and a chip, wherein the chip is as described above, a first pin of the chip is connected to the battery, and a second pin of the chip is connected to the charging interface.

[0008] The switching circuit provided in this application includes: a first MOSFET, the first terminal of which is connected to the input port, a body diode of which is a first body diode, the anode of which is connected to the first terminal of the first MOSFET, and the cathode of which is connected to the second terminal of the first MOSFET; a second MOSFET, the first terminal of which is used to output a second signal, the second terminal of which is connected to the second terminal of the first MOSFET, a body diode of which is a second body diode, the anode of which is connected to the first terminal of the second MOSFET, and the cathode of which is connected to the second terminal of the second MOSFET; and a switching module connected to the control terminals of the first and second MOSFETs, which is used to control the conduction or disconnection of the first and second MOSFETs. In this configuration, the first and second MOSFETs are back-to-back. Due to the unidirectional conduction characteristic of diodes, the body diode between the drain and source of the second MOSFET can prevent the voltage at the drain of the second MOSFET from being transmitted to the source of the second MOSFET. Therefore, the voltage at the input port will not be transmitted to the output terminal, thereby avoiding leakage current in the switching circuit and improving circuit safety. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the structure of the first embodiment of the power management circuit provided in this application;

[0011] Figure 2 This is a schematic diagram of the structure of the second embodiment of the power management circuit provided in this application;

[0012] Figure 3 This is a schematic diagram of the connection between the first pin PIN1 and the second pin PIN2 in one embodiment;

[0013] Figure 4 yes Figure 2 A circuit diagram of the first embodiment of the switching circuit for medium and high voltage switches;

[0014] Figure 5 yes Figure 2 A circuit diagram of the second embodiment of the switching circuit for medium and high voltage switches;

[0015] Figure 6 yes Figure 2 A circuit diagram of the third embodiment of the switching circuit for medium and high voltage switches;

[0016] Figure 7 This is a schematic diagram of the third embodiment of the power management circuit provided in this application;

[0017] Figure 8 This is a connection diagram of the voltage detection module 40 in one embodiment;

[0018] Figure 9 This is a circuit diagram of the voltage detection module 40 in one embodiment;

[0019] Figure 10 This is a schematic diagram of the fourth embodiment of the power management circuit provided in this application;

[0020] Figure 11 This is a schematic diagram of the structure of an embodiment of the chip provided in this application;

[0021] Figure 12 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0025] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0026] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0027] See Figure 1 , Figure 1 This is a schematic diagram of the first embodiment of the power management circuit provided in this application. The power management circuit 100 includes a first pin PIN1, a second pin PIN2, and a power module 10.

[0028] The first pin PIN1 is connected to the battery, and the second pin PIN2 is connected to the charging interface. The charging interface is used to connect an adapter to an external power source. The power module 10 is used to operate when powered by either the first pin PIN1 (battery) or the second pin PIN2 (adapter).

[0029] Optionally, in one embodiment, the power module 10 may include a voltage regulator circuit. The voltage regulator circuit generates a set voltage signal under the power supply of the first pin PIN1 (battery) or the second pin PIN2 (adapter). The set voltage signal is used to supply power to the module in the circuit or other modules in the peripheral circuit.

[0030] For example, in one embodiment, the power module 10 may include a reference voltage generation circuit and a low dropout regulator (LDO). The reference voltage generation circuit generates a reference voltage signal Vref when powered by a battery or adapter, and then inputs the reference voltage signal Vref to the low dropout regulator. The low dropout regulator generates a set voltage signal, such as a VDD signal, based on the reference voltage signal Vref to power other modules in the chip.

[0031] This embodiment mainly includes two power supply modes:

[0032] First power mode: After the second pin PIN2 is powered on, when the voltage of the battery (first pin PIN1) is greater than the first set voltage threshold, the electrical path between the first pin PIN1 and the power module 10 is opened, or when the voltage of the battery is less than the first set voltage threshold, the electrical path between the second pin PIN2 and the power module 10 is opened.

[0033] Second power mode: After the second pin PIN2 is powered on, the power path between the second pin PIN2 and the power module 10 is selected.

[0034] Understandably, the trigger condition for both power modes is that the second pin PIN2 is powered on, that is, the second pin PIN2 is connected to an external power source for charging through the adapter.

[0035] Specifically, in the first power mode, when the second pin PIN2 is connected to a power source for charging via an adapter, it is determined whether the current battery voltage is greater than a first preset voltage threshold. If the battery voltage is greater than the first preset voltage threshold, the battery is used to supply power to the power module 10, i.e., the electrical path between the first pin PIN1 and the power module 10 is selected. If the battery voltage is less than the first preset voltage threshold, the adapter is used to supply power to the power module 10, i.e., the electrical path between the second pin PIN2 and the power module 10 is selected. Understandably, in the first power mode, the power supply method for the power module 10 is mainly selected based on the battery voltage. If the adapter is not connected (not charging), only battery power can be used. If the battery voltage gradually decreases to an insufficient level to supply power, the entire system shuts down. If the adapter is connected for charging, the system selects between battery power or adapter power based on the battery voltage.

[0036] Specifically, in the second power supply mode, when the second pin PIN2 is connected to a power source for charging via an adapter, the power supply to the power module 10 is directly provided by the adapter, thus enabling the electrical path between the second pin PIN2 and the power module 10. Understandably, in the second power supply mode, if the adapter is not connected (not charging), only battery power is available. If the battery voltage gradually decreases to an insufficient level to provide power, the entire system shuts down. If the adapter is connected for charging, then the adapter provides power.

[0037] Optionally, the power management circuit 100 further includes a gating module 20, which is connected to a first pin PIN1, a second pin PIN2, and the power-consuming module 10. In a first power mode, after the second pin PIN2 is powered on, the gating module 20 selects the electrical path between the first pin PIN1 and the power-consuming module 10 when the battery voltage is greater than a first set voltage threshold, and selects the electrical path between the second pin PIN2 and the power-consuming module 10 when the battery voltage is less than the first set voltage threshold. The gating module 20 is also used in a second power mode to select the electrical path between the second pin PIN2 and the power-consuming module 10 after the second pin PIN2 is powered on.

[0038] Optionally, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the second embodiment of the power management circuit provided in this application. The power management circuit 100 includes a first pin PIN1, a second pin PIN2, a power consumption module 10, and a gating module 20. The gating module 20 further includes a gating unit 21 and a control unit 22. The gating unit 21 is connected to the first pin PIN1, the second pin PIN2, and the power consumption module 10; the control unit 22 is connected to the gating unit 30.

[0039] The selection unit 21 specifically includes a first switch S1 and a second switch S2. The first end of the first switch S1 is connected to the first pin PIN1, and the second end of the first switch S1 is connected to the input terminal of the power module 10. The first end of the second switch S2 is connected to the second pin PIN2, and the second end of the second switch S2 is connected to the input terminal of the power module 10. The first switch S1 and the second switch S2 can be high-voltage switches, and their on / off states can be controlled by the control unit 22. The specific circuit structure will be described in subsequent embodiments.

[0040] Optionally, the power management circuit 100 further includes a threshold comparison circuit, which is used to determine whether the battery voltage is greater than a first set voltage threshold. For example, the threshold comparison circuit may include a comparator COMP, the first input terminal of the comparator COMP is used to receive the first set voltage threshold V1, the second input terminal of the comparator COMP is connected to the first pin PIN1, and the output terminal of the comparator COMP is connected to the control unit 22.

[0041] In one embodiment, the first set voltage threshold V1 can be 3.1V.

[0042] Specifically, in the first power mode, after the second pin PIN2 is powered on, when the battery voltage is greater than the first set voltage threshold V1, the control unit 22 controls the gating unit 21 to select the electrical path between the first pin PIN1 and the power module 10 (on switch S1, off switch S2), or when the battery voltage is less than the first set voltage threshold V1, the control unit 22 controls the gating unit 21 to select the electrical path between the second pin PIN2 and the power module 10 (off switch S1, on switch S2). In the second power mode, after the second pin PIN2 is powered on, the control unit 22 controls the gating unit 21 to select the electrical path between the second pin PIN2 and the power module 10 (off switch S1, on switch S2).

[0043] Understandably, the control terminal of the second switch S2 mentioned above can also be further controlled by the wake-up signal WAKE. The wake-up signal WAKE is input by the third pin (not shown in the figure) and is used to indicate that the second pin PIN2 is powered on.

[0044] Optionally, in one embodiment, the number of second pins PIN2 is one or more, each second pin PIN2 is used to connect to a corresponding charging interface, and different charging interfaces are used to connect to different adapters. For example, the second pins PIN2 may include one or both of the PACK pin and the VBUS pin. Figure 3 As shown, Figure 3 This is a schematic diagram of the connection between the first pin PIN1 and the second pin PIN2 in one embodiment.

[0045] The PACK and VBUS pins are two different types of adapter charging pins, and only one can be powered on at a time. Specifically, diodes are placed between PIN1 and PIN2, between PACK and PIN2, and between VBUS and PIN2. When PACK and VBUS are not powered on, the voltage of PIN2 is equal to the voltage of PIN1, i.e., the battery voltage. When PACK is powered on, since the charging voltage is generally greater than the battery voltage, the voltage of PIN2 is equal to the voltage of PACK. Similarly, when VBUS is powered on, the voltage of PIN2 is equal to the voltage of VBUS.

[0046] See Figure 4 , Figure 4 yes Figure 2 A circuit diagram of the first embodiment of the switching circuit of the medium and high voltage switch. The switching circuit 400 includes a first MOSFET M1, a second MOSFET M2 and a switching module.

[0047] The first terminal of the first MOSFET M1 is used to receive the first signal Vin, and the body diode of the first MOSFET M1 is the first body diode D. M1First body diode D M1 The anode is connected to the first terminal of the first MOSFET M1, and the first body diode D... M1 The cathode of the first MOSFET M1 is connected to the second terminal of the first MOSFET M1; the first terminal of the second MOSFET M2 is connected to the second terminal of the first MOSFET M1, and the second terminal of the second MOSFET M2 is used to output the second signal Vout. The body diode of the second MOSFET M2 is the second body diode D. M2 Second body diode D M2 The anode of the second MOSFET M2 is connected to the second terminal of the second body diode D. M2 The cathode is connected to the first terminal of the second MOSFET M2; the switching module is connected to the control terminal of the first MOSFET M1 and the control terminal of the second MOSFET M2, and the switching module is used to control the conduction or disconnection of the first MOSFET M1 and the second MOSFET M2.

[0048] Optionally, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors. The source of the first MOS transistor M1 is used to receive the first signal Vin, and the source of the second MOS transistor M2 is used to output the second signal Vout. The drains of the first MOS transistor M1 and the second MOS transistor M2 are connected, and the gates of the first MOS transistor M1 and the second MOS transistor M2 are connected to the switching module.

[0049] Optionally, the switching circuit 400 further includes a resistor R0. The first end of the resistor R0 is used to receive the power supply voltage signal VCC, and the second end of the resistor R0 is connected to the gate of the first MOSFET M1 and the gate of the second MOSFET M2. The resistor R0 is mainly used to provide bias voltage to the gates of the first MOSFET M1 and the second MOSFET M2, preventing the gates of the first MOSFET M1 and the second MOSFET M2 from being left floating.

[0050] Optionally, the switching circuit 400 further includes a diode D0, the cathode of which is connected to the source of the first MOSFET M1, and the anode of which is connected to the gate of the first MOSFET M1 and the gate of the second MOSFET M2. The diode D0 primarily serves to protect the first MOSFET M1 and the second MOSFET M2.

[0051] Specifically, the first MOSFET M1 and the second MOSFET M2 are connected back-to-back (i.e., the cathodes of the body diodes of M1 and M2 are connected together). When the first MOSFET M1 is not turned on, the current through the body diode D of the first MOSFET M1 is applied. M1The voltage is transferred to the drains of the first MOSFET M1 and the second MOSFET M2, ensuring stable potentials at their drains and preventing a floating state in the circuit. The first MOSFET M1 and the second MOSFET M2 are back-to-back structures. Due to the unidirectional conduction characteristic of diodes, the body diode D between the drain of the second MOSFET M2 and the source of the second MOSFET... M2 This can prevent the voltage at the drain of the second MOSFET M2 from being transmitted to the source of the second MOSFET M2. Therefore, the voltage at the first pin PIN1 or the second pin PIN2 will not be transmitted to the output terminal, thus avoiding leakage current in the switching circuit.

[0052] When the switching module pulls down the voltage of the gate of the first MOSFET M1 and the gate of the second MOSFET M2, the first MOSFET M1 and the second MOSFET M2 are turned on, and the voltage of the first pin PIN1 or the second pin PIN2 is output through the source of the second MOSFET, which is equivalent to the entire switching circuit being turned on.

[0053] When the switching module pulls down the voltage between the drain of the first MOSFET M1 and the drain of the second MOSFET M2, the entire switching circuit is disconnected.

[0054] See Figure 5 , Figure 5 yes Figure 2 A circuit diagram of a second embodiment of a medium- and high-voltage switch circuit, wherein the switch circuit 400 includes a transistor M, a current mirror module, and a switch module.

[0055] The transistor M has a first terminal for receiving a first signal Vin and a second terminal for outputting a second signal Vout. The input terminal of the current mirror module is connected to the first terminal of the transistor M. The current mirror module includes a first branch B1 and a second branch B2. The current in the second branch B2 is greater than the current in the first branch B1. The second output terminal corresponding to the second branch B2 is connected to the control terminal of the transistor M. The switch module is connected to the first output terminal corresponding to the first branch B1 and the second output terminal corresponding to the second branch B2. The switch module is used to control the transistor M to be turned on or off.

[0056] Optionally, transistor M is a PMOS transistor, and the current mirror module includes two symmetrical PMOS transistors. Since the size (width-to-length ratio) of the MOS transistor in the second branch B2 is larger than that of the MOS transistor in the first branch B1, the current formed in the second branch B2 is greater than the current in the first branch B1.

[0057] Specifically, the second branch B2 can proportionally replicate the current of the first branch B1 and charge the gate of transistor M, raising the gate potential of transistor M. When the gate potential of transistor M reaches a certain value, such that |Vgs| is less than the conduction threshold, transistor M will turn off. Since the high-voltage switch has requirements for turn-off time and needs to turn off quickly, a higher current ratio can be set (current ratio = width-to-length ratio of the MOS transistor in the second branch B2 ÷ width-to-length ratio of the MOS transistor in the first branch B1) to quickly pull up the gate potential of transistor M, thereby quickly turning off transistor M and disconnecting the entire switching circuit.

[0058] When the switching module pulls down the gate voltage of transistor M, transistor M turns on, which is equivalent to the entire switching circuit turning on.

[0059] In combination with the above Figure 4 and Figure 5 For an example, see [link to example]. Figure 6 , Figure 6 yes Figure 2 A circuit diagram of the third embodiment of the switching circuit of the medium and high voltage switch. The switching circuit 400 includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a resistor R1, a resistor R2, and a diode D1.

[0060] The first terminal of the first MOSFET M1 is used to receive the first signal Vin, and the body diode of the first MOSFET M1 is the first body diode D. M1 First body diode D M1 The input terminal is connected to the first terminal of the first MOSFET M1, and the first body diode D... M1 The output terminal of the first MOSFET M1 is connected to the second terminal of the first MOSFET M1; the first terminal of the second MOSFET M2 is connected to the second terminal of the first MOSFET M1, and the second terminal of the second MOSFET M2 is used to output the second signal Vout. The body diode of the second MOSFET M2 is the second body diode D. M2 Second body diode D M2 The anode of the second MOSFET M2 is connected to the second terminal of the second body diode D. M2 The cathode is connected to the first terminal of the second MOS transistor M2.

[0061] Optionally, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors. The source of the first MOS transistor M1 is used to receive the first signal Vin, and the source of the second MOS transistor M2 is used to output the second signal Vout. The drains of the first MOS transistor M1 and the second MOS transistor M2 are connected, and the gates of the first MOS transistor M1 and the second MOS transistor M2 are connected.

[0062] Understandably, the third MOSFET M3 and the fourth MOSFET M4 form a current mirror. The third MOSFET M3 is a PMOS transistor, with its source connected to the drain of the first MOSFET M1 and its drain connected to its gate. The fourth MOSFET M4 is also a PMOS transistor, with its source connected to the drain of the second MOSFET M2 and its gate connected to the gate of the third MOSFET M3. The first terminal of resistor R1 is connected to the drain of the first MOSFET M1, and the second terminal of resistor R1 is connected to the gate of the third MOSFET M3. The fourth MOSFET M4 is larger than the third MOSFET M3.

[0063] Optionally, the switching circuit 400 includes a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, and an eighth MOSFET M8 forming a switching module. The fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, and the eighth MOSFET M8 are NMOS transistors. The drains of the fifth MOSFET M5 and the seventh MOSFET M7 are connected to the gate of the second MOSFET M2. The drain of the sixth MOSFET M6 is connected to the drain of the third MOSFET M3. The drain of the eighth MOSFET M8 is connected to the source of the second MOSFET M2. The sources of the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, and the eighth MOSFET M8 are all grounded. The gate of the fifth MOSFET M5 receives a first control signal S1 (generated by the control unit). The gate of the sixth MOSFET M6 receives a second control signal S2 (generated by the control unit). The gate of the seventh MOSFET M7 receives a wake-up signal WAKE. The gate of the eighth MOSFET M8 receives a reset signal RST.

[0064] Specifically, the first MOSFET M1 and the second MOSFET M2 are connected back-to-back (i.e., the cathodes of the body diodes of M1 and M2 are connected together, i.e., node B). When the first MOSFET M1 is not turned on, the current from the first pin PIN1 or the second pin PIN2 flows through the body diode D of the first MOSFET M1. M1 The voltage is transmitted to nodes A and B, ensuring stable potentials at nodes A and B and preventing the circuit from floating. The first MOSFET M1 and the second MOSFET M2 are back-to-back. Due to the unidirectional conduction characteristic of diodes, the body diode D between the source of node B and the second MOSFET... M2 This can prevent the voltage at node B from being transmitted to the source of the second MOSFET M2. Therefore, the voltage at the first pin PIN1 or the second pin PIN2 will not be transmitted to the output, thus avoiding leakage in the switching circuit.

[0065] When the first control signal S1 turns on the fifth MOSFET M5, or the wake-up signal WAKE turns on the seventh MOSFET M7, node A is pulled low, and the first MOSFET M1 and the second MOSFET M2 turn on, thus turning on the entire switching circuit. Diode D1 is used to clamp the voltage and prevent the MOSFETs from being damaged.

[0066] When the second control signal S2 turns on the sixth MOSFET M6, the current mirror formed by the third MOSFET M3 and the fourth MOSFET M4 operates. The fourth MOSFET M4 can proportionally replicate the current of the third MOSFET M3 and charge node A, raising the potential of node A. Since the gates of the first MOSFET M1 and the second MOSFET M2 are both connected to node A, when the potential of node A reaches a certain value, causing |Vgs| of the first MOSFET M1 and the second MOSFET M2 to be less than the turn-on threshold, the first MOSFET M1 and the second MOSFET M2 will turn off. Because the high-voltage switch has a requirement for turn-off time and needs to turn off quickly, a higher current ratio can be set (current ratio = width-to-length ratio of M4 ÷ width-to-length ratio of M3) to quickly pull node A high, thereby quickly turning off the first MOSFET M1 and the second MOSFET M2 and cutting off the switching circuit.

[0067] See Figure 7 , Figure 7 This is a schematic diagram of the third embodiment of the power management circuit provided in this application. The power management circuit 100 includes a first pin PIN1, a second pin PIN2, a power module 10, a gating unit 21, a control unit 22, and a voltage detection module 30.

[0068] The first pin PIN1 is connected to the battery, and the second pin PIN2 is connected to the charging interface, which is used to connect the adapter to connect to an external power source. The power module 10 is used to generate a set voltage signal under the power supply of the first pin PIN1 (battery) or the second pin PIN2 (adapter). The set voltage signal is used to supply power to the modules in the circuit or other modules in the peripheral circuit. The gating unit 21 is connected to the first pin PIN1, the second pin PIN2 and the power module 10. The control unit 22 is connected to the gating unit 30.

[0069] Furthermore, the voltage detection module 30 is connected to the second pin PIN2 and the control unit 22. The voltage detection module 30 is used to detect the voltage of the electrical signal at the second pin PIN2, and when the detected voltage is greater than a second preset voltage threshold (to detect whether an adapter is being used for charging), it sends a wake-up signal to the control unit 22 to wake up the control unit 22. Optionally, the control unit 22 is also used to control the gating unit 21 to select the electrical path between the first pin PIN1 and the power module 20 when the voltage detected by the voltage detection module 30 is less than the second preset voltage threshold. In addition, the control unit 22 is also used to enter a sleep state when the battery voltage is less than a first preset voltage threshold.

[0070] Optionally, in one embodiment, in conjunction with the above... Figure 3 In one embodiment, the voltage detection module 30 is used to detect the voltage of the PACK pin and the VBUS pin respectively. Figure 8 As shown, Figure 8 This is a connection diagram of the voltage detection module 30 in one embodiment.

[0071] Specifically, the voltage detection module 30 includes a PACK voltage detection module 31 and a VBUS voltage detection module 32. The PACK voltage detection module 31 is used to detect the voltage of the electrical signal of the PACK pin, and when the detected voltage is greater than a second set voltage threshold, it sends a wake-up signal to the control unit 22 to wake up the control unit 22. The VBUS voltage detection module 32 is used to detect the voltage of the electrical signal of the VBUS pin, and when the detected voltage is greater than a second set voltage threshold, it sends a wake-up signal to the control unit 22.

[0072] Optionally, the ACK voltage detection module 31 and the VBUS voltage detection module 32 can adopt similar circuit structures. The circuit of the voltage detection module 30 is described below, such as... Figure 9 As shown, Figure 9 This is a circuit diagram of the voltage detection module 30 in one embodiment.

[0073] The voltage detection module 30 includes resistors R11, R12, and R13, PMOS transistors M11, M12, M13, and M14, a first NPN transistor Q1, a second NPN transistor Q2, a first inverter INV1, and a second inverter INV2.

[0074] Understandably, PMOS transistors M11, M12, M13, and M14 form a current mirror. PMOS transistors M12, M13, and M14 can proportionally replicate the current of PMOS transistor M11, providing bias current for the branch of the second NPN transistor Q2 and the first inverter INV1 and the second inverter INV2. If the first inverter INV1 and the second inverter INV2 were directly connected to the power supply, the power consumption would be relatively high, and the bias current would be unstable. Providing bias current through a current mirror reduces power consumption and ensures a more stable and controllable bias current.

[0075] In this configuration, the first terminal of resistor R11 is connected to the second pin (PACK pin or VBUS pin); PMOS transistors M11, M12, M13, and M14 are connected as a current mirror, with their sources connected to the second terminal of resistor R11; the first terminal of resistor R12 is connected to the drain of the first MOS transistor M11; the collector of the first NPN transistor Q1 is connected to the second terminal of resistor R12, and the emitter of the first NPN transistor Q1 is grounded; the collector of the second NPN transistor Q2 is connected to the drain of PMOS transistor M12, and the emitter of the second NPN transistor Q1 is grounded. The base of transistor Q2 is connected to the base of the first NPN transistor Q1; the first end of resistor R13 is connected to the emitter of the second NPN transistor Q2, and the second end of resistor R13 is grounded; the power supply terminal of the first inverter INV1 is connected to the drain of PMOS transistor M13, and the input terminal of the first inverter INV1 is connected to the drain of PMOS transistor M12; the power supply terminal of the second inverter INV2 is connected to the drain of PMOS transistor M14, the input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and the output terminal of the second inverter INV2 is connected to the control unit 22.

[0076] The following is about Figure 9 The circuit principle will be introduced as follows:

[0077] Taking the first terminal of resistor R11 connected to the PACK pin as an example, as the voltage on the PACK pin gradually increases, the currents I2 (current flowing through resistor R1) and I1 (current flowing through resistor R3) can be expressed as:

[0078]

[0079]

[0080] Where PACK is the voltage at the PACK pin, V TH V is the turn-on threshold voltage of M11. be1 V is the voltage between the base and emitter of Q1. be2 Δ is the voltage between the base and emitter of Q2.Vbe For V be1 and V be2 The difference.

[0081] As the voltage at the PACK pin increases, when I2 = I1, the threshold flip condition is met (the PACK voltage reaches the threshold), and a Det signal is emitted. The PACK voltage can be solved using the above two equations.

[0082]

[0083] The Det signal is a digital signal used to indicate that the PACK pin has power connected to the adapter.

[0084] Optionally, in one embodiment, if multiple thresholds are required, an impedance unit can be added to the circuit described above. The first end of the impedance unit is connected to the second end of the resistor R11, the second end of the impedance unit is grounded, and the resistance value of the impedance unit is configured to be adjustable.

[0085] Understandably, the impedance unit can use multiple resistors connected in series and multiple switches to adjust the number of resistors connected in parallel in the original circuit. Figure 9 The example includes 3 resistors and 3 switches. By controlling the switches, the number of resistors connected in parallel to the original circuit can be adjusted to 0, 1, 2, or 3. Therefore, 4 different detection thresholds (4 levels) can be set for the voltage detection module. If more levels are needed, more series resistors and switches can be added.

[0086] Assuming the resistance of the blocking unit is R14, considering the resistance R14, the wake-up voltage of the PACK can be expressed as:

[0087]

[0088] Therefore, by adjusting the resistance value of R4, multiple levels of the wake-up threshold can be set.

[0089] Optionally, in one embodiment, the voltage detection module 30 further includes a diode D2, the anode of which is grounded and the cathode of which is connected to the second end of the resistor R11. The diode D2 is a Zener diode and serves a protective function.

[0090] See Figure 10 , Figure 10 This is a schematic diagram of the fourth embodiment of the power management circuit provided in this application. The power management circuit 100 includes a first pin PIN1, a second pin PIN2, a power consumption module 10, a gating unit 21, a control unit 22, and a virtual power detection module 40.

[0091] The virtual power detection module 40 is connected to the second pin PIN2 and the power module 10.

[0092] In one embodiment, in conjunction with the above Figure 3 In one embodiment, the second pin PIN2 is further connected to the PACK pin and the VBUS pin, and the virtual charge detection module 40 can be connected to the PACK pin and the VBUS pin. The virtual charge detection module 40 is used to release residual charge on the second pin PIN (PACK pin or VBUS pin), and the virtual charge detection module 40 is configured to turn off after the power-consuming module 10 is powered on.

[0093] Understandably, the virtual voltage detection module 40 is used to prevent false wake-ups due to virtual voltage on the PACK or VBUS pins, and to avoid voltage spikes on the PACK or VBUS pins caused by charge accumulation, which could lead to a false wake-up of the system. When the PACK or VBUS pins are connected to the adapter, after the system wakes up and the power module 10 powers on and outputs stably, the virtual voltage detection module 40 can be turned off.

[0094] In combination with the above Figures 1-10 Multiple embodiments:

[0095] In the first power mode, after the system is powered on and woken up via the PACK pin or VBUS pin, the comparator COMP compares the battery voltage VBAT with a set first voltage threshold V1. If VBAT is greater than the set first voltage threshold V1, the gating unit 21 selects the PIN1 pin (VBAT) to supply power to the power module 10. When VBAT is less than the set first voltage threshold V1, it automatically switches to the PIN2 pin (PACK / VBUS, i.e., powered by the adapter). If the voltage of the VBUS pin or the PACK pin is less than the wake-up threshold when VBAT is less than the set threshold, i.e., the adapter is unplugged and the battery voltage is insufficient to supply power, the system shuts down (e.g., the control unit 22 enters sleep mode).

[0096] In the second power mode, after the system is powered on and woken up via the PACK pin or VBUS pin, even if VBAT is greater than the set threshold, the gating unit 21 still selects the PIN2 pin to power the power module 10 (i.e., after waking up, the default power supply is selected by the adapter). When the voltage of the VBUS pin or the voltage of the PACK pin is less than the wake-up threshold, the gating unit 21 selects the PIN1 pin (i.e., after the adapter is unplugged, the power supply is switched to the battery). In this case, if VBAT is less than 3.1V, the system is powered off (for example, the control unit 22 enters sleep mode).

[0097] like Figure 6As shown, the second power mode is compatible with flight mode control and RST reset control. Upon entering flight mode, VBAT is forcibly activated for power supply. Both the first and second power modes' shutdown controls are hardware shutdowns, meaning the system shuts down when power supply is insufficient. In addition to hardware shutdown, this circuit also supports command shutdown (if a shutdown command is received when power supply is sufficient, the system can also be shut down). For example, when using RST for reset, switches S1 and S2 are turned off to cut off the power supply channel, and a pull-down mechanism is applied to achieve the reset function.

[0098] Optionally, when a compatible PACK is inserted, the system cannot be shut down using commands; when a VBUS is inserted, the system can be shut down using commands.

[0099] The power management circuit provided in this application includes: a first pin for connecting to a battery; a second pin for connecting to a charging interface; a power-consuming module for operating under power supplied by either the first or second pin; and a selection module for, in a first power mode, when the second pin is powered on, selecting the electrical path between the first pin and the power-consuming module when the battery voltage is greater than a first set voltage threshold, and selecting the electrical path between the second pin and the power-consuming module when the battery voltage is less than the first set voltage threshold. Through this method, the power supply channel selection can be achieved in charging / non-charging situations. On the one hand, this makes the selection of the power supply channel more intelligent and compatible with different charging methods; on the other hand, it facilitates scientific management of battery power supply and extends battery life.

[0100] In a further embodiment, a voltage detection module can be used to detect multiple voltage levels of the charging interface and realize multi-threshold wake-up operation.

[0101] In a further embodiment, a high-voltage switch design is adopted. The switching circuit includes: a first MOSFET, the first terminal of which is used to receive a first signal; the first MOSFET includes a first body diode, the anode of which is connected to the first terminal of the first MOSFET, and the cathode of which is connected to the second terminal of the first MOSFET; a second MOSFET, the first terminal of which is used to output a second signal; the second terminal of which is connected to the second terminal of the first MOSFET; the second MOSFET includes a second body diode, the anode of which is connected to the first terminal of the second MOSFET, and the cathode of which is connected to the second terminal of the second MOSFET; and a switching module, which is connected to the control terminals of the first and second MOSFETs and is used to control the conduction or disconnection of the first and second MOSFETs. This design prevents leakage current in the high-voltage switch and improves its safety.

[0102] In a further embodiment, a high-voltage switch design is employed. The switching circuit includes: a transistor, whose first terminal receives a first signal and whose second terminal outputs a second signal; a current mirror module, whose input terminal is connected to the first terminal of the transistor, the current mirror module including a first branch and a second branch, the current in the second branch being greater than that in the first branch, and the second branch being connected to the control terminal of the transistor; and a switching module connected to the first and second branches, used to control the transistor's on / off state. This design enables rapid shutdown of the high-voltage switch, improving its safety.

[0103] In a further embodiment, the design employing virtual charge detection can prevent the charging interface voltage from rising due to charge accumulation, thus avoiding the system being falsely woken up.

[0104] See Figure 11 , Figure 11 This is a schematic diagram of a chip embodiment provided in this application. The chip 110 includes a power management circuit 100. The power management circuit 100 is the power management circuit described in the above embodiments, or the power management circuit 100 includes a switching circuit described in the above embodiments.

[0105] See Figure 12 , Figure 12 This is a schematic diagram of an embodiment of the electronic device provided in this application. The electronic device 120 includes a chip 110, which is the chip described in the above embodiment.

[0106] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A switching circuit, characterized in that, The switching circuit includes: The first MOSFET has its first terminal connected to the input port. The body diode of the first MOSFET is a first body diode, with the anode of the first body diode connected to the first terminal of the first MOSFET and the cathode of the first body diode connected to the second terminal of the first MOSFET. The second MOSFET has a first terminal for outputting a second signal and a second terminal connected to the second terminal of the first MOSFET. The body diode of the second MOSFET is a second body diode, with the anode of the second body diode connected to the first terminal of the second MOSFET and the cathode of the second body diode connected to the second terminal of the second MOSFET. A switching module is provided, which is connected to the control terminal of the first MOSFET and the control terminal of the second MOSFET. The switching module is used to control the first MOSFET and the second MOSFET to be turned on or off. The switching module includes a seventh MOS transistor, which is an NMOS transistor. The drain of the seventh MOS transistor is connected to the control terminal of the first MOS transistor and the control terminal of the second MOS transistor. The source of the seventh MOS transistor is grounded, and the gate of the seventh MOS transistor is used to receive a wake-up signal. The switching module further includes a current mirror, the input terminal of which is connected to the second terminal of the first MOSFET, and the second output terminal of which is connected to the control terminal of the first MOSFET and the control terminal of the second MOSFET. The current mirror is used to raise the voltage of the control terminal of the first MOSFET and the control terminal of the second MOSFET when the seventh MOSFET is turned on. The switching module also includes a sixth MOSFET, the first end of which is connected to the first output terminal of the current mirror, and the second end of which is grounded.

2. The switching circuit according to claim 1, characterized in that, The first MOS transistor and the second MOS transistor are PMOS transistors. The source of the first MOS transistor is used to receive a first signal, and the source of the second MOS transistor is used to output a second signal. The drains of the first MOS transistor and the drains of the second MOS transistor are connected, and the gates of the first MOS transistor and the gates of the second MOS transistor are connected to the switching module.

3. The switching circuit according to claim 2, characterized in that, The switching circuit further includes a first resistor, the first end of which is used to receive a power supply voltage signal, and the second end of which is connected to the gate of the first MOSFET and the gate of the second MOSFET.

4. The switching circuit according to claim 2, characterized in that, The switching circuit further includes a first diode, the cathode of which is connected to the source of the first MOS transistor, and the anode of which is connected to the gate of the first MOS transistor and the gate of the second MOS transistor.

5. The switching circuit according to claim 1, characterized in that, The switching module includes a fifth MOS transistor, which is an NMOS transistor. The drain of the fifth MOS transistor is connected to the control terminal of the first MOS transistor and the control terminal of the second MOS transistor. The source of the fifth MOS transistor is grounded, and the gate of the fifth MOS transistor is used to receive a first control signal.

6. The switching circuit according to claim 5, characterized in that, The sixth MOS transistor is an NMOS transistor. The drain of the sixth MOS transistor is connected to the first output terminal of the current mirror. The source of the sixth MOS transistor is grounded. The gate of the sixth MOS transistor is used to receive a second control signal, wherein the second control signal and the first control signal are clock signals that do not overlap.

7. The switching circuit according to claim 1, characterized in that, The current mirror includes: The third MOS transistor is a PMOS transistor. The source of the third MOS transistor is connected to the second terminal of the first MOS transistor, and the drain of the third MOS transistor is connected to the gate of the third MOS transistor and to the drain of the sixth MOS transistor. The fourth MOS transistor is a PMOS transistor. The source of the fourth MOS transistor is connected to the second terminal of the second MOS transistor, the gate of the fourth MOS transistor is connected to the gate of the third MOS transistor, and the drain of the fourth MOS transistor is connected to the control terminal of the first MOS transistor and the control terminal of the second MOS transistor. The second resistor has its first end connected to the second end of the first MOS transistor and its second end connected to the gate of the third MOS transistor. The fourth MOS transistor is larger than the third MOS transistor.

8. The switching circuit according to claim 1, characterized in that, The switching module also includes a third resistor, the first end of which is connected to the input terminal of the current mirror, and the second end of which is connected to the second output terminal of the current mirror.

9. The switching circuit according to claim 8, characterized in that, The switching module also includes a second diode, the cathode of which is connected to the input terminal of the current mirror, and the anode of which is connected to the second output terminal of the current mirror.

10. A power management circuit, characterized in that, The power management circuit includes a high-voltage switch, which includes a switching circuit as described in any one of claims 1-9.

11. The power management circuit according to claim 10, characterized in that, The number of high-voltage switches is multiple, and each of the multiple high-voltage switches is used to receive different power signals. One of the high-voltage switches is selected to select the corresponding power signal for power supply.

12. A chip, characterized in that, The chip includes a switching circuit as described in any one of claims 1-9, or a power management circuit as described in claim 10 or 11.

13. An electronic device, characterized in that, The electronic device includes the chip as described in claim 12.

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