Non-volatile counter system with isolated dynamic boost power supply, counter circuit and power management circuit

Abstract

This application discloses a non-volatile counter system (100) comprising: a power supply circuit (101) for generating first and second supply voltage signals using power from a sensor pulse signal to supply power to first and second power domain circuits (121, 132), including a switch (S1), a boost circuit (150), and a control circuit (144) connected between the first and second power domain power supply nodes (122, 142), the control circuit (144) for selectively disconnecting the first and second power domain circuits (121, 132) from each other by the switch (S1) after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and for boosting the second supply voltage signal by the boost circuit (150) after the regulator output is disconnected from the second power domain power supply node (142) in a given pulse.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201780093301.5 (PCT / CN2017 / 094687), filed on July 27, 2017, entitled “Non-volatile counter system with isolated dynamic boost power supply, counter circuit and power management circuit”. Background Technology

[0002] Non-volatile counters are used in various position detection applications to count pulses from sensors. For example, a flow meter may include a rotating part with magnetic elements and a sensor for detecting the passing of the rotating magnet through a fixed point. The counter provides a counter value representing the number of detected magnetic pulses, and therefore the amount of liquid flowing through the meter. Other position sensor applications include elevator pulley systems with rotating parts that provide a changing magnetic field that can be sensed by a magnetic sensor. Some counter systems count pulses from two or more sensors and selectively determine whether to increment or decrement the counter value based on the sensor pulse signals. Non-volatile pulse counter systems are useful in various situations where power is lost but the location of the structure needs to be rotated or moved. For example, utility meters are used to assess the amount of water used by a consumer for billing purposes. Electric flow meters can be used to provide a counter value representing the amount of water used by a particular consumer. It is desirable to update the counter value to account for water usage, even when no external power source is available. In another example, an automated rotating tool or machine can be manually rotated during a power outage. Non-volatile pulse counter systems use energy harvested from the rotation of system components to operate the counter by making appropriate increments or decrements. This allows the system to know the position of movable parts and operate accordingly when power is applied. In another example, an elevator transport system may experience a power outage during movement, and even after the power outage, the elevator's momentum will cause a change in position. Non-volatile counter systems allow the counter value to be updated even when external power is unavailable, so that it correctly indicates the elevator's position when power is restored. For some applications, such as flow meters and rotary encoders, position sensors need to be compact, and it is beneficial to use small, low-cost energy harvesting sources. However, the energy available to harvest to power the non-volatile counter when system power is unavailable will be limited. Summary of the Invention

[0003] Disclosed examples include a non-volatile counter system for generating and storing counter values ​​based on sensor pulse signals, and a power supply circuit for generating a first supply voltage signal and a second supply voltage signal using power from the sensor pulse signals to power logic circuits and memory circuits. In one aspect, the power supply circuit includes a switch, a boost circuit, and a control circuit, the switch being connected between a first power domain supply node and a second power domain supply node. Before activating the second supply generation signal, the control circuit causes the switch to disconnect the first and second power domain circuits from each other. Additionally, after the regulator output is disconnected from the second power domain supply node in a given pulse, the control circuit causes the boost circuit to boost the second supply voltage signal. Attached Figure Description

[0004] Figure 1 This is a schematic diagram of a non-volatile counter system with a power supply circuit that provides power to a first power domain and a second power domain using power from a sensor pulse signal.

[0005] Figure 2 It is shown Figure 1 The signal diagram of the system. Detailed Implementation

[0006] In the accompanying drawings, similar reference numerals always refer to similar elements, and various features are not necessarily drawn to scale. In the following discussion and claims, the terms "comprising," "including," "having," "having," "with," or variations thereof are intended to be inclusive in a manner similar to the term "comprising," and therefore should be interpreted as "including, but not limited to...". Similarly, the terms "coupled" or "coupled" are intended to include indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or coupled to a second device, the connection may be via a direct electrical connection or via an indirect electrical connection via one or more intermediate devices and connectors.

[0007] Figure 1 A non-volatile counter system 100 is illustrated, which generates and stores counter values. The non-volatile counter system 100 includes a power supply circuit 101 having multiple power domains. In one example, the power supply circuit 101 is fabricated within an integrated circuit (IC) 102 that implements the non-volatile counter circuitry. In some embodiments, IC 102 forms part of a system-on-a-chip (SOC) product including one or more additional computing blocks (not shown). The non-volatile counter system 100 can be used as part of position sensing solutions for various applications, including but not limited to flow sensors and rotary and / or linear position sensors. IC 102 includes terminals for connection to one or more sensors. Figure 1In one example, sensor 104 (e.g., a Wiegand sensor) includes a first sensor output 106p (e.g., positive or +) providing a sensor signal WSP, and a second (e.g., negative or -) sensor output 106m providing a sensor signal WSM to IC 102. The signals WSP and WSM together form a differential sensor pulse signal. In one example, sensor 104 includes a small-diameter ferromagnetic wire with magnetic properties, such that a reversal of the magnetic field near sensor 104 causes sensor 104 to generate voltage pulse signals WSP and WSM; in this case, the voltage pulse signals WSP and WSM may be referred to as Wiegand pulses. In other examples, different types of sensors may be used that respond to changing ambient magnetic fields or other sensing conditions representing motion of a host structure (not shown) relative to the sensor to provide single-ended or differential sensor pulse signals.

[0008] In operation, IC 102 generates and stores a counter value, which can be used by the host system or a connected processor (not shown) to determine the position of the host structure relative to sensor 104. Additionally, as described in further detail below, IC 102 includes power supply circuitry for harvesting energy from sensor pulse signals WSP, WSM to allow operation of the counter value update logic and non-volatile memory. Furthermore, the disclosed example provides a novel power signal generation method to intelligently use the energy of a single pulse from the sensor pulse signals WSP, WSM to read the current counter value from the on-board non-volatile memory, update the counter value according to the sensor pulse signals WSP, WSM, and store the counter value. This provides non-volatile counter operation without an external power supply.

[0009] like Figure 1 As shown, IC 102 includes a power supply circuit 108 that uses power from sensor pulse signals WSP and WSM to generate a supply voltage signal VRECT. In one example, the power supply circuit 108 is a rectifier circuit including two input terminals connected to sensor outputs 106p and 106m, respectively. In this example, the power supply circuit 108 also includes a first diode and a second diode (not shown), the anodes of which are connected to a corresponding input line coupled to sensor outputs 106p and 106m, respectively, while their cathodes are connected to a single-ended power supply output terminal 110 to generate the supply voltage signal VRECT using power from sensor pulse signals WSP and WSM. Figure 1As schematically shown, the differential sensor pulse signals WSP and WSM can include both positive and negative pulses, but this is not a strict requirement for all possible implementations. Power supply circuit 108 rectifies both the positive and negative pulses to provide the rectifier output signal VRECT. An external rectifier capacitor CRECT is connected via a corresponding IC terminal between the power supply output terminal 110 and the system ground or other constant voltage reference node (e.g., circuit ground (GND) 103). In other possible implementations, the rectifier capacitor CRECT is internal to IC 102. Power supply circuit 108 and rectifier capacitor CRECT operate to provide the DC voltage signal VRECT using energy from the sensor pulse signals WSP and WSM. Shunt circuit 112 prevents overvoltage at the power supply output.

[0010] In one example, the system includes two or more sensors, which can be of the same type or different types, such as Wiegand sensors, fluxgate sensors, anisotropic magnetoresistive (AMR) sensors and / or giant magnetoresistive (GMR) sensors. Figure 1 IC 102 includes a sensor 114 (e.g., a GMR sensor) mounted to sense ambient magnetic fields or other sensing conditions representing motion of the host structure (not shown). Sensor 114 includes positive and negative signal connectors at sensor outputs 115p and 115m, respectively, and a grounding switch connector at sensor output 115s connected to IC 102 via corresponding IC terminals.

[0011] The rectifier output signal VRECT powers power supply circuit 101 and one or more additional loads. IC 102 includes power management circuitry 116 powered by the rectifier output signal VRECT. Power management circuitry 116 includes an output 118 for providing a reference voltage VREF to power supply circuit 101. Power supply circuit 101 includes regulator circuitry 120 with an output coupled to a first power domain power supply node 122, which uses power from the supply voltage signal VRECT to provide a first supply voltage signal VCORE. Any suitable regulator circuitry can be used to provide the voltage signal VCORE to power supply circuit 101 to implement counter value update and storage functions. In one example, regulator circuitry 120 is a low dropout (LDO) regulator that regulates the voltage signal VCORE according to the reference voltage VREF from power management circuitry 116. Regulator circuitry 120 includes an input coupled to power supply output 110 to receive the VRECT signal from power supply circuit 108, and a regulator output that uses power from the supply voltage signal VRECT to generate the first supply voltage signal VCORE.

[0012] The power supply circuit 101 includes a first power domain circuit 121 (in Figure 1 (Labeled as "Domain 1"), the first power domain circuit 121 has a first power domain power supply node 122 connected to receive the supply voltage signal VCORE from the regulator output. IC 102 includes a first domain capacitor CCORE connected between the power supply output 110 and GND 103. The first power domain circuit 121 includes a counting logic circuit 126 powered by the first supply voltage signal VCORE, and a non-volatile (NVL) control circuit 124 also powered by the VCORE signal. The counting logic circuit 126 includes an interface 128 for sending and receiving a first data signal CNTCORE representing a counter value. In one example, the interface 128 is a serial interface with one or more signal lines for sending and receiving the data signal CNTCORE. In other examples, a parallel interface may be used. The interface 128 transmits data to and from the counting logic circuit 126 via an isolation / level shifting circuit 130.

[0013] The power supply circuit 101 includes a second power domain circuit 132, which includes a non-volatile memory circuit or memory array (e.g., memory 134) powered by a second supply voltage signal VNVL. The memory 134 includes a second interface 131 for sending and receiving a second data signal CNT representing a counter value. The memory 134 stores the counter value and allows the processor or MCU 140 or other associated host circuitry to read or write to the counter value. Figure 1 In this example embodiment, MCU 140 is connected to a second interface 136 of memory 134 via isolation and level shifting circuitry 138. In this example embodiment, MCU 140 is powered by a different power domain than memory 134. In this configuration, MCU 140 may be powered down, while memory 134 is powered via a second supply voltage signal VNVL at the second power domain power supply node 142. The second supply voltage signal VNVL is generated using power collected from sensor pulse signals WSP and WSM. Initially, in each given pulse of sensor pulse signals WSP and WSM, the second supply voltage signal VNVL is generated by regulator circuitry 120. Subsequently, in a given pulse, a boost circuit formed by buffer circuitry 150 and pump capacitor CP boosts the voltage signal VNVL above the level of the first supply voltage signal VCORE. The boost circuit includes a boost output connected to the second power domain power supply node 142. The boost circuit selectively boosts or increases the second supply voltage signal VNVL according to the control signal PUMP.

[0014] The power supply circuit 101 also includes a pump timing control state machine or other control circuitry 144, a switch S1, and another isolation and level shifting circuit 148. Switch S1 is connected between the first power domain power supply node 122 and the second power domain power supply node 142. Any suitable switch that operates according to a switch control signal SCS to selectively connect or disconnect the first power domain power supply node 122 and the second power domain power supply node 142 can be used. In the illustrated example, switch S1 is a PMOS transistor with its source connected to the second power domain power supply node 142, its drain connected to the first power domain power supply node 122, and its gate control terminal connected to the output 149 of the level shifting circuit 148 to receive the switch control signal SCS. The second domain capacitor CNVL is connected between the second power domain power supply node 142 and GND 103. In the illustrated example, the capacitor CNVL is external to IC 102, and the IC includes terminals for connecting an external capacitor. In other examples, the second domain capacitor CNVL may be internal to IC 102.

[0015] Control circuit 144 includes a control output 146 that provides the control signal PUMP. In one example, control circuit 144 is powered by the supply voltage signal VCORE of the first power domain circuit 121. When the first power domain circuit 121 is initially de-energized (e.g., between pulses of sensor pulse signals WSP, WSM), the PUMP signal is low, and the switch control signal SCS at the level shift circuit output 149 is also low. When the rectifier output voltage VRECT rises in response to a given pulse of the sensor pulse signals WSP, WSM, the regulator circuit 120 provides the first supply voltage signal VCORE with a positive voltage and turns on switch S1 via the low switch control signal SCS. This also causes VNVL to rise to the same level as VCORE. In one example, control circuit 144 implements a state machine that provides the first supply voltage signal VCORE at a given pulse of the sensor pulse signals WSP, WSM (e.g., below). Figure 2 In step 218), after a predetermined time following the rise to level VREF, the PUMP signal is asserted to be active high. This causes the switch control signal SCS to go high, thereby disconnecting switch S1 and disconnecting the regulator output at the first power domain power supply node 122 from the second power domain power supply node 142.

[0016] The PUMP signal is also provided as an input to buffer circuit 150. Buffer circuit 150 can be any suitable circuit, such as a CMOS transistor, that provides an output to the terminals of capacitor CP having a logic state corresponding to the state of the PUMP signal. Buffer circuit 150 has a buffer output terminal 162 connected to one terminal of capacitor CP, and the other terminal of capacitor CP is connected to the power supply node 142 of the second power domain. When the PUMP signal is initially low during a given pulse of sensor pulse signals WSP, WSM during the startup of power circuit 101, the voltage at buffer output terminal 162 is low. This causes capacitor CP to charge to the voltage of the second supply voltage signal VNVL. At this time, VNVL is at the VCORE level. In one embodiment, after the first supply voltage signal VCORE rises to the VREF level, control circuit 144 changes the PUMP signal to a high state. In response, buffer circuit 150 changes the voltage at buffer output terminal 162 to a higher voltage (e.g., at or near the envisioned final level of VNVL of the second power domain circuit 132). The charging pump capacitor CP thus raises or boosts the second supply voltage signal VNVL to provide a boosted second supply voltage signal VNVL at the second power domain supply node 142. In one example, a boost occurs via a voltage transition at the buffer output 162 after the regulator output at the first power domain supply node 122 is disconnected from the second power domain supply node 142 in a given pulse. This prevents the first supply voltage signal VCORE at the first power domain supply node 122 and the regulator circuit 120 from draining charge from the second supply signal VNVL at the second power domain supply node 142.

[0017] Level shifting circuit 130 performs level shifting between the voltage levels of the VCORE and VNVL signals to provide a data transmission communication channel between the first power domain circuit 121 and the second power domain circuit 132. During operation during a given pulse of the sensor pulse signals WSP and WSM, counting logic circuit 126 reads a counter value from memory 134 via interfaces 128 and 131 and level shifting circuit 130. In one example, counting logic circuit 126 includes one or more registers to temporarily store the counter value read from memory 134. In this example, IC 102 also includes pulse and polarity detection circuit 152, whose inputs are connected to sensor outputs 106p and 106m, and other inputs are connected to receive GMR sensor signals GMRP and GMPM from sensor outputs 115p and 115m of sensor 114. IC 102 further includes a GMR sensing and grounding switch circuit 154, which has signal connectors at sensor outputs 115p and 115m for connecting to GMR sensor signals GMRP and GMPM, and a grounding switch connector at sensor output 115s for providing signal GNDSW. Another isolation and level shifting circuit 156 provides signal transmission between the counting logic circuit 126 of the first power domain circuit 121 and circuits 152 and 154 of IC 102.

[0018] In response to each given pulse received from sensor pulse signals WSP and WSM, counting logic circuit 126 selectively updates the counter value based on the given pulse. This update may include incrementing or decrementing the counter value based on various sensing conditions. Any suitable logic circuit can be used, which can implement any suitable algorithm to determine whether the counter value needs to be incremented or decremented based on the currently given pulse received from sensor pulse signals WSP and WSM. This algorithm may take into account, for example, the relative timing between signals from the first sensor 104 and the second sensor 114. For example, this method may be used where the rotating or moving structure includes bias magnets for actuating the first sensor 104 and the second sensor 114, respectively. In such an example, counting logic circuit 126 determines the direction of travel or rotation of the moving structure based on the relative timing of the signals from sensors 104 and 114. In other examples, counting logic circuit 126 considers the previous history of counter value increments and / or decrements when determining or evaluating whether the counter value should be incremented or decremented. In some implementations, the counting logic circuit 126 writes an updated counter value to memory 134 via interfaces 128 and 131 and level shifting circuit 130 during the pulses of the sensor pulse signals WSP and WSM. This operation advantageously allows the MCU 140 or other connected processor to resume operation after a power-off event and read the counter value from memory 134 to determine the position of the structure in motion or after it has been moved. Furthermore, the power harvesting operation of the power supply circuit 101 advantageously uses power obtained from an external supply voltage, but not required by the presence of the external supply voltage, to retain the updated counter value in memory 134.

[0019] Figure 2 The diagram shows signal graphs with curves 200, 210, 220, 230, and 240, which illustrate... Figure 1 The example IC 102 contains various signals and waveforms. Graph 200 includes WSP signal curves 202 and 204, where curve 202 illustrates an exemplary first Wiegand sensor signal WSP, and curve 204 illustrates the corresponding second Wiegand sensor signal WSM in an exemplary given pulse of the differential sensor pulse signals WSP and WSM from sensor 104. In this example, the sensor pulse signal... Figure 2The time T0 in the graph begins. Graph 210 shows an exemplary supply voltage signal curve 212 (VRECT) at the output of the power supply circuit 108, corresponding to the sensor pulse signals WSP and WSM in graph 200. In response to the rise of the WSP signal curve 202, the supply voltage signal curve 212 begins to rise after T0. Graph 210 also includes a first supply voltage signal curve 214, which shows the corresponding first supply voltage signal VCORE generated by the regulator circuit 120 at the first power domain power supply node 122. Figure 2 At time T1, the supply voltage signal curve 212 exceeds the first threshold voltage 218 (e.g., 0.8V). At time T2, the first supply voltage signal curve 214 begins to rise and eventually reaches the adjustment setpoint value (e.g., 1.0V) set by the reference voltage signal VREF from the power management circuit 116. Figure 2 Graph 220 shows a curve illustrating the exemplary control signal PUMP provided by control circuitry 144. Additionally, graph 230 includes curve 232 illustrating an example of the second supply voltage signal VNVL, and graph 240 includes curve 242 illustrating memory access (read and write) of memory 134. When switch S1 is turned on (e.g., when the PUMP signal is low), the second supply voltage signal VNVL begins to rise at T2 to substantially follow the first supply voltage signal VCORE. During this time period, the second supply voltage signal VNVL will typically be slightly lower than the first supply voltage signal VCORE due to the on-state resistance (RDSON) of the PMOS transistor switch S1. The first supply voltage signal VCORE and the connected second supply voltage signal VNVL... Figure 2 When the voltage rises between T2 and T3, the first power domain capacitor CCORE and the second power domain capacitor CNVL are charged, and the pump capacitor CP is charged to approximately the voltage of the second supply voltage signal VNVL.

[0020] As shown in graph 220, in one example, control circuit 144 implements a state machine that generates the rising edge 226 of PUMP signal 222 at time T3, which is a predetermined time 224 after T1. In this example, control circuit 144 asserts the PUMP signal at a predetermined time 224 after the exemplary supply voltage signal curve 212 exceeds the first threshold voltage 218. In response to a sufficient rise in the control signal PUMP, the switch control signal SCS from level shift circuit 148 rises to a level sufficient to turn off PMOS switch S1. Moreover, this control signal assertion raises the buffer output voltage at buffer output 162 and causes the charged pump capacitor CP to boost the second supply voltage signal VNVL, manifested as a further rise in curve 232 after T3. The boost amount is determined by the initial charging voltage of pump capacitor CP and the capacitance of capacitors CP and CNVL. Thereafter, the boosted second supply voltage signal VNVL reaches the boost level 234 shown in graph 230. In the given design, the boosted second supply voltage signal VNVL is provided at a level (e.g., 1.5V) sufficient to ensure proper operation of the memory 134 for a fixed predetermined number of accesses.

[0021] However, simultaneously, regulator circuit 120 regulates the first supply voltage signal VCORE to a lower level. In view of this, the non-volatile control circuit 124 and counting logic circuit 126, as well as any other associated circuits powered by the first supply voltage signal VCORE, do not require a boosted voltage level for proper operation. In this example, the buffer circuit 150, CP provides a boosted supply voltage signal VNVL, which is a certain amount higher than the minimum operating voltage required by memory 134, allowing a fixed number of accesses to be performed while the non-volatile control circuit 124 and counting logic circuit 126 operate according to the lower regulated voltage signal VCORE. This operation advantageously reduces the energy consumption of the circuitry in the first power domain circuitry 121. Furthermore, selectively using buffer circuit 150, CP will not suffer the energy overhead associated with powering memory 134 using a separate regulator (e.g., LDO, not shown). In view of this, using regulator circuit 120 to provide the first supply voltage signal VCORE allows circuitry (e.g., 116) powered by rectifier voltage VRECT to operate at a slightly higher voltage level. Figure 1The circuit operates at a voltage of VNVL (e.g., 1.2V). This is because any LDO requires its input voltage to be at least slightly higher than its output voltage. Conversely, if a single power supply were used instead, it would be limited by the VNVL level (1.5V), thus limiting VRECT to 1.7V. Operating at 1.7V would consume more energy than operating at 1.2V. In another conventional solution, for memory 134, which requires a minimum voltage of 1.5V to operate properly, using two separate LDO regulator circuits to power the first power domain circuit 121 and the second power domain circuit 132 respectively would require a minimum voltage of approximately 1.7V at the power supply output 110, since the LDO's input must be approximately 0.2-0.3V higher than its output. This would consume more energy than our method (where VRECT can be reduced to 1.2V). Therefore, the illustrated example advantageously allows for lower voltage operation of the circuitry supplied by a voltage signal VRECT (e.g., as low as approximately 1.2V), and also facilitates regulated operation of circuits 124, 126 within the first power domain circuitry 121 at a suitably regulated voltage (e.g., 1.0V), while providing the second domain supply voltage signal VNVL at a level (e.g., 1.5V) that ensures proper operation of the memory 134. The lower minimum VRECT also allows for the use of charge in the rectifier capacitor CRECT, which is reduced from its highest level set by the Wiegand sensor to 1.2V, instead of 1.7V in conventional solutions.

[0022] continue Figure 2 The sensor pulse signals WSP and WSM continue to increase and then decrease after T3, as shown in curve 200. In the example shown, the supply voltage signal curve 212 correspondingly reaches its peak after T3 and then gradually decreases. Once the supply voltage signal curve 212 drops to the second threshold 216 (curve 210), the control circuit 144 removes the PUMP signal, causing the falling edge 228 of the PUMP signal 222 (curve 220) to begin at T4. The falling edge 228 of the PUMP signal allows the buffer output 162 to return to GND, and the regulator circuit 120 stops regulating the voltage at the first power domain supply node 122.

[0023] During the time period between T3 and T4, the first power domain circuit 121 and the second power domain circuit 132 operate at appropriate voltages to allow the counting logic circuit 126 and the memory 134 to maintain appropriate counter values ​​to indicate the location of the moving structure associated with the non-volatile counter system 100. Specifically, graph 240 illustrates one or more memory access events in curve 242 during the time period 244 between T3 and T4. As shown in graph 230, the boosted second supply voltage signal VNVL can transition from boost level 234 to boost level 236 (e.g., from 1.8V to 1.5V) between T3 and T4, where both boost levels 234 and 236 are higher than the minimum operating voltage of the memory 134. During this time period T3 to T4, the counting logic circuit 126 can initially read the previous counter value from the memory 134, selectively update (e.g., increment or decrement) the counter value, and write the updated counter value back to the memory 134. Then, memory 134 stores the updated counter value for subsequent use by MCU 140. As described above, this operation is independent of any power outage associated with MCU 140 and other power domains in a given system implementation. Therefore, MCU 140 can be restarted after any power outage and can read the counter value from memory 134 and take any appropriate action to ensure that the stored counter value represents the current position of a particular moving or movable structure of interest (e.g., an elevator, machine tool, flow meter rotating structure).

[0024] The illustrated power supply circuit 101 advantageously uses the energy of the sensor pulse signals WSP and WSM to operate the counting logic circuit 126, the memory 134, and other circuits of IC 102. Furthermore, the power supply circuit 101 facilitates the use of the sensor 104, where the energy budget provided by the amplitude and duration of the sensor pulse signals WSP and WSM is limited. Specifically, the regulator circuit 120 advantageously regulates the first supply voltage VCORE to a value less than the minimum required operating voltage of the memory 134, but still sufficient to power the circuits 124 and 126 in the first power domain circuit 121. A boost circuit, including a buffer circuit 150 and a pump capacitor CP, boosts or increases the second supply voltage signal VNVL to a level sufficient to provide appropriate operating power to the memory 134 during the relevant portion of a given pulse of the sensor pulse signals WSP and WSM. Once the first power domain circuit 121 and the second power domain circuit 132 are effectively separated or isolated by the open switch S1, the regulator circuit 120 continues to regulate the first supply voltage VCORE according to the reference voltage VREF. In one example, the regulator circuit adjusts the first supply voltage VCORE to a value less than the boosted second supply voltage signal VNVL. Furthermore, in some examples, regulator circuit 120 adjusts VCORE to a value less than the minimum required operating voltage of memory 134. In one example, regulator circuit 120 operates with an input voltage approximately 200mV higher than its output voltage. Because the lower operating voltage VCORE supplied to circuits 124 and 126 results in a lower voltage VRECT at the power supply output 110, the disclosed example advantageously harvests more available energy than previous methods, allowing circuits 108, 112, and 116 to consume less energy and utilize the energy contained in the lower voltage VRECT. This advantageously facilitates intelligent consumption of the signal energy budget to enable counting logic circuitry operations for reading counter values ​​from memory 134, selectively updating counter values, and writing updated counter values ​​back to memory 134 during a given pulse of sensor pulse signals WSP, WSM. The examples of this disclosure also facilitate the use of sensor 104 compared to what might be possible with other power harvesting techniques previously employed. Furthermore, the disclosed techniques and circuits facilitate the intelligent use of the energy budget of a given sensor pulse signal WSP, WSM, which is suitable for the operating voltage requirements of memory 134 and circuits 124, 126.

[0025] The examples above are merely illustrative of several possible embodiments of various aspects of this disclosure, and equivalent changes and / or modifications will arise in the minds of others skilled in the art upon reading and understanding this specification and the accompanying drawings. Modifications may be made to the described embodiments within the scope of the claims, and other embodiments are possible.

Claims

1. An integrated circuit, comprising: A power supply circuit, which has a power supply input terminal and a power supply output terminal; A power supply circuit, coupled to the power supply circuit and comprising: First power domain circuit; Second power domain circuit; A regulator circuit having a regulator input coupled to the power supply output and a regulator output coupled to the first power domain circuit. A switch coupled between the first power domain circuit and the second power domain circuit, the switch having a switch control input terminal; A control circuit having a first control output coupled to the switch control input and a second control output; and A boost circuit having a boost input and a boost output, the boost input being coupled to a second control output and the boost output being coupled to a second power domain circuit, and the boost circuit being configured to generate a voltage for the second power domain circuit in response to a pulse signal at the boost input.

2. The integrated circuit according to claim 1, wherein: The second power domain circuit requires a higher voltage than the first power domain circuit.

3. The integrated circuit according to claim 1, wherein: The boost circuit includes: A buffer circuit includes a buffer input terminal and a buffer output terminal, wherein the buffer input terminal is connected to the second control output terminal to receive a control signal from the second control output terminal; and The capacitor includes a first terminal connected to the second power domain circuit and a second terminal connected to the output of the buffer; and The control circuit is configured to provide the control signal, including a rising edge, at a predetermined time after the first supply voltage signal at the first power domain circuit rises above a threshold voltage, to increase the voltage at the second terminal of the capacitor, thereby providing a second supply voltage signal at the second power domain circuit.

4. The integrated circuit according to claim 3, wherein: The boost circuit is coupled to the first power domain circuit; The first power domain circuit is coupled to the second power domain circuit. and The control circuit is configured to disconnect the first power domain circuit from the second power domain circuit before outputting the voltage to the second power domain circuit.

5. The integrated circuit according to claim 1, wherein the regulator circuit is a low-dropout regulator.

6. The integrated circuit of claim 1, wherein the first power domain circuit and the second power domain circuit are formed in a single integrated circuit.

7. A power management circuit, comprising: First circuit; Second circuit; A power supply circuit, which has a power supply input terminal and a power supply output terminal; A regulator circuit having a regulator input coupled to the power supply output and a regulator output coupled to the first circuit; A switch coupled between the first circuit and the second circuit, the switch having a switch control input terminal; A control circuit having a first control output coupled to the switch control input and having a second control output; as well as A boost circuit having a boost input and a boost output, the boost input being coupled to a second control output, the boost output being coupled to a second circuit, and the boost circuit being configured to generate a voltage for the second circuit in response to a pulse signal at the boost input.

8. The power management circuit according to claim 7, wherein: The second circuit requires a higher voltage than the first circuit.

9. The power management circuit according to claim 7, wherein: The boost circuit includes: A buffer circuit includes a buffer input terminal and a buffer output terminal, wherein the buffer input terminal is connected to the second control output terminal to receive a control signal from the second control output terminal; and The capacitor includes a first terminal connected to the second circuit and a second terminal connected to the output of the buffer; and The control circuit is configured to provide the control signal, including a rising edge, at a predetermined time after the first supply voltage signal at the first circuit rises above a threshold voltage, to increase the voltage at the second terminal of the capacitor, thereby providing a second supply voltage signal at the second circuit.

10. The power management circuit according to claim 7, wherein: The boost circuit is coupled to the first circuit; The first circuit is coupled to the second circuit; and The control circuit is configured to disconnect the first circuit from the second circuit before outputting the voltage to the second circuit.

11. The power management circuit according to claim 7, wherein the regulator circuit is a low-dropout regulator.

12. The power management circuit of claim 7, wherein the first circuit and the second circuit are formed in a single integrated circuit.

13. A power management system, comprising: First circuit; Second circuit; A power supply circuit, which has a power supply input terminal and a power supply output terminal; A regulator circuit having a regulator input coupled to the power supply output and a regulator output coupled to the first circuit; A switch coupled between the first circuit and the second circuit, the switch having a switch control input terminal; A control circuit having a first control output coupled to the switch control input and having a second control output; as well as A boost circuit having a boost input and a boost output, the boost input being coupled to a second control output, the boost output being coupled to a second circuit, and the boost circuit being configured to generate a voltage for the second circuit in response to a pulse signal at the boost input.

14. The power management system according to claim 13, wherein: The second circuit requires a higher voltage than the first circuit.

15. The power management system according to claim 13, wherein: The boost circuit includes: A buffer circuit includes a buffer input terminal and a buffer output terminal, wherein the buffer input terminal is connected to the second control output terminal to receive a control signal from the second control output terminal; and The capacitor includes a first terminal connected to the second circuit and a second terminal connected to the output of the buffer; and The control circuit is configured to provide the control signal, including a rising edge, at a predetermined time after the first supply voltage signal at the first circuit rises above a threshold voltage, to increase the voltage at the second terminal of the capacitor, thereby providing a second supply voltage signal at the second circuit.

16. The power management system according to claim 13, wherein: The boost circuit is coupled to the first circuit; The first circuit is coupled to the second circuit; and The control circuit is configured to disconnect the first circuit from the second circuit before outputting the voltage to the second circuit.

17. The power management system of claim 13, wherein the regulator circuit is a low-dropout regulator.

18. The power management system of claim 13, wherein the first circuit and the second circuit are formed in a single integrated circuit.

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