Method for manufacturing a semiconductor structure and structure thereof

Abstract

This disclosure relates to the semiconductor field, providing a method for fabricating a semiconductor structure and the structure thereof. The method for fabricating the semiconductor structure includes: providing a substrate, the substrate including first grooves spaced apart along a first direction and a filling layer located within the first grooves; patterning the substrate to form second grooves, the second grooves being located on the top surface of the first grooves; depositing a protective layer on the surface of the substrate, the protective layer being different from the filling layer; forming a bit line structure, the bit line structure being formed at the bottom of the second grooves; forming a first isolation layer, the first isolation layer being located within the second grooves and on the top surface of the bit line structure; removing a portion of the filling layer, the remaining filling layer being flush with the upper surface of the first isolation layer, the first grooves and the second grooves forming a channel pillar structure; forming a word line structure, the word line structure surrounding the channel pillar structure; and forming an isolation structure, the isolation structure being located within the second grooves and between adjacent word line structures, which can improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a method for fabricating a semiconductor structure and the structure thereof. Background Technology

[0002] As the integration density of dynamic memory continues to increase, while researching the arrangement of transistors in dynamic memory array structures and how to reduce the size of individual functional devices in dynamic memory array structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When using a vertical gate-all-around (GAA) transistor structure as a dynamic memory select transistor (access transistor), its area can reach 4F. 2 (F: Minimum pattern size achievable under given process conditions) can, in principle, achieve higher density efficiency.

[0004] However, it is currently necessary to improve the performance of semiconductor structures. Summary of the Invention

[0005] This disclosure provides a method for fabricating a semiconductor structure and the structure thereof, which can at least improve the performance of the semiconductor structure.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including first grooves spaced apart along a first direction and a filling layer located within the first grooves; patterning the substrate to form second grooves, the second grooves being spaced apart along a second direction and located on the top surface of the first grooves, the first grooves and the second grooves forming a channel columnar structure; forming a protective layer on the surface of the substrate, the protective layer being different from the filling layer; forming a bit line structure, the bit line structure being formed at the bottom of the second grooves; forming a first isolation layer, the first isolation layer being located within the second grooves and on the top surface of the bit line structure; removing a portion of the filling layer, the remaining filling layer being flush with the upper surface of the first isolation layer; forming a word line structure, the word line structure surrounding the channel columnar structure and spaced apart along the second direction; and forming an isolation structure, the isolation structure being located within the second grooves and between adjacent word line structures.

[0007] In some embodiments, the method further includes: a first dielectric layer located on the top surface of the bitline structure and the sidewall of the channel column structure; the method of forming the protective layer includes: forming a first protective layer located on the top surface of the substrate; patterning a portion of the first dielectric layer to expose a portion of the inner wall of the second groove; forming a second protective layer located on the inner wall of the second groove and the sidewall of the first protective layer, wherein the first protective layer and the second protective layer constitute the protective layer.

[0008] In some embodiments, the method of forming the word line structure includes: after forming the protective layer, patterning the first dielectric layer so that the top surface of the first dielectric layer is flush with the top surface of the first isolation layer; forming a second dielectric layer, the second dielectric layer being located on the top surface of the first dielectric layer and covering part of the sidewall of the channel column structure; forming an initial word line structure, the initial word line structure filling the first groove and the second groove; patterning the initial word line structure using the protective layer as a mask until the top surface of the first isolation layer is exposed, the remaining initial word line structure serving as the word line structure.

[0009] In some embodiments, the step of removing a portion of the filler layer includes: before forming the protective layer, removing the first dielectric layer and a portion of the filler layer in the same step; the top surface of the filler layer is flush with the top surface of the first dielectric layer; after forming the protective layer, removing the first dielectric layer and a portion of the filler layer in the same step; the remaining filler layer is flush with the upper surface of the first isolation layer.

[0010] In some embodiments, the method of forming the isolation structure includes: forming a first isolation structure located on the top surface of the first isolation layer, the sidewall of the letter line structure, and the sidewall of the protective layer; forming a second isolation structure that fills the third groove, wherein the first isolation structure and the second isolation structure constitute the isolation structure.

[0011] In some embodiments, the method of forming the protective layer includes: before patterning the substrate, further comprising: removing a portion of the filler layer and forming a first initial protective layer on the top surface of the filler layer; patterning the first initial protective layer and the substrate to form a second groove, with the remaining first initial protective layer serving as a first protective layer; forming a second protective layer, the second protective layer being located on the inner wall of the second groove and the side wall of the first protective layer, the first protective layer and the second protective layer constituting the protective layer.

[0012] In some embodiments, the method further includes: a first dielectric layer located on the top surface of the bit line structure and the sidewall of the channel column structure; the method of forming the word line structure includes: forming an initial word line structure located on the top surface of the first dielectric layer and the first isolation layer and the bottom surface of the protective layer; patterning the initial word line structure and the first isolation layer using the protective layer as a mask until the top surface of the first isolation layer is exposed, with the remaining initial word line structure serving as the word line structure.

[0013] In some embodiments, the step of removing a portion of the fill layer includes: removing a portion of the fill layer before patterning the substrate; and removing a portion of the fill layer after forming the protective layer and before forming the initial word line structure.

[0014] In some embodiments, the method of forming the isolation structure includes: forming a first isolation structure, the first isolation structure being located on the top surface of the first isolation layer, the sidewalls of the word line structure and the sidewalls of the protective layer, the first isolation structure and the protective layer constituting the isolation structure.

[0015] In some embodiments, the method of forming the protective layer includes: forming a first protective layer located on the top surface of the substrate; forming a second protective layer located on the sidewall of the first protective layer and on the top surface of the second groove, wherein the first protective layer and the second protective layer constitute the protective layer.

[0016] In some embodiments, the method further includes: a first dielectric layer located on the top surface of the bitline structure and the sidewall of the channel columnar structure; the method of forming the wordline structure includes: removing a portion of the first dielectric layer and the filler layer in the same step, so that the top surface of the first dielectric layer is flush with the upper surface of the first isolation layer; forming a second dielectric layer located on the top surface of the first dielectric layer and covering a portion of the sidewall of the channel columnar structure; forming an initial wordline structure, the initial wordline structure filling the first groove and the second groove, the top surface of the initial wordline structure being flush with the bottom surface of the first protective layer; patterning the initial wordline structure and the first isolation layer using the protective layer as a mask until the top surface of the bitline structure is exposed, the remaining initial wordline structure serving as the wordline structure.

[0017] In some embodiments, the method of forming the isolation structure includes: forming a first isolation structure and a second isolation structure, wherein the first isolation structure is an air gap formed by the first isolation layer, the word line structure and the second isolation structure, the second isolation structure is located between the word line structures, and the top surface of the second isolation structure is flush with the top surface of the word line structure.

[0018] In some embodiments, the method of forming the bit line structure includes: forming a fourth groove located on the bottom surface of a second groove; forming a first bit line conductive layer using a metal silicide process, the first bit line conductive layer located on the surface of the fourth groove facing the substrate; forming a second bit line conductive layer, the second bit line conductive layer filling the fourth groove, the first bit line conductive layer and the second bit line conductive layer constituting the bit line structure.

[0019] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a substrate; a channel pillar structure located within the substrate and spaced apart along a first direction and a second direction; a bit line structure communicating with the channel pillar structure and spaced apart within the substrate along the second direction, with the bit line structure located on the bottom surface of the channel pillar structure; a first isolation layer located on the top surface of the bit line structure; a filling layer located within the substrate, with the top surface of the filling layer flush with the top surface of the first isolation layer; a word line structure surrounding the channel pillar structure and spaced apart along the second direction; and an isolation structure located at least between adjacent word line structures.

[0020] In some embodiments, the isolation structure includes a first isolation structure and a second isolation structure. The first isolation structure is an air gap formed by the first isolation layer, the word line structure and the second isolation structure. The second isolation structure is located between the word line structures, and the top surface of the second isolation structure is flush with the top surface of the word line structure.

[0021] In some embodiments, the isolation structure includes: a protective layer located on the top surface and part of the sidewalls of the channel column structure; and a first isolation structure located on the top surface of the first isolation layer, the sidewalls of the word line structure, and the sidewalls of the protective layer.

[0022] In some embodiments, the isolation structure includes: a first isolation structure located on the top surface of the first isolation layer and the sidewall of the letter line structure; and a second isolation structure located on the top surface of the channel column structure and between the channel column structure and the first isolation structure.

[0023] In some embodiments, the bit line structure includes: a first bit line conductive layer, the first bit line conductive layer being located within the substrate and in contact with the bottom surface of the channel column structure; and a second bit line conductive layer, the second bit line conductive layer being located on the top surface of the first bit line conductive layer.

[0024] In some embodiments, the top surface of a portion of the second bit line conductive layer is lower than the bottom surface of the channel column structure, and the bottom surface of the first isolation structure is lower than the bottom surface of the channel column structure.

[0025] The technical solution provided by the embodiments of this disclosure has at least the following advantages: a word line structure is formed by forming a surrounding channel pillar structure to form a fully surrounding gate transistor structure, and an isolation structure is formed between adjacent word line structures after the word line structure is formed. The isolation structure can increase the insulation between adjacent word lines, thereby improving the performance of the semiconductor structure. That is, the performance of the semiconductor structure is improved while satisfying the semiconductor structure density efficiency. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figures 1 to 18 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0028] Figures 19 to 31 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

[0029] Figures 32 to 40 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure. Detailed Implementation

[0030] As is known from the background art, with the continuous increase in integration density, how to balance the size of individual functional devices in a semiconductor structure and the electrical performance of small-sized functional devices has become a problem. Therefore, it is necessary to provide a method for fabricating a semiconductor structure and its structure, so as to meet the performance requirements of the semiconductor structure while satisfying the integration density of the semiconductor structure.

[0031] This disclosure provides a method for fabricating a semiconductor structure. By forming a word line structure with a surrounding channel pillar structure, a fully surrounding gate transistor structure can be formed. By forming an isolation structure between the word line structures, electrical connections between adjacent word lines can be avoided, thereby satisfying the integration density of the semiconductor structure while meeting the performance requirements of the semiconductor structure.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] refer to Figure 1 , Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure.

[0034] In some embodiments, the semiconductor structure includes: a substrate 100; a channel pillar structure 110 located within the substrate 100 and spaced apart along a first direction X and a second direction Y; a bit line structure 120 connected to the channel pillar structure 110, spaced apart along the second direction Y within the substrate 100, and located on the bottom surface of the channel pillar structure 110; and a word line structure 130 surrounding the channel pillar structure 110 and spaced apart along the second direction Y.

[0035] In some embodiments, a dielectric layer 140 is formed around the channel column structure 110, the dielectric layer 140 wrapping around the channel column structure 110 to avoid direct contact between the channel column structure 110 and the word line 130.

[0036] By forming word lines 130 that surround the channel pillar structure 110, a fully encircling gate structure can be formed, thereby satisfying the integration density of the semiconductor structure while meeting the performance requirements of the semiconductor structure.

[0037] refer to Figures 2 to 4 , Figures 2 to 4 For the embodiments of this disclosure Figure 1 A cross-sectional view along the direction of the dashed line.

[0038] A substrate 100 is provided, the substrate 100 including first grooves 150 spaced apart along a first direction X within the substrate 100 and a filling layer 160 located within the first grooves 150.

[0039] In some embodiments, the first groove 150 can be formed using a self-aligned double patterning (SADP) process. In other embodiments, the first groove 150 can also be formed using a self-aligned quadruple patterning (SAQP) process. SADP or SAQP techniques can make the pattern of the formed first groove 150 more precise.

[0040] In some embodiments, the substrate 100 may be made of silicon, germanium, or silicon germanide, and may also be doped. For example, if the substrate 100 is made of silicon, a trace amount of trivalent element, such as boron, indium, gallium, or aluminum, may be doped into the substrate 100 to form a P-type substrate. Similarly, a trace amount of pentavalent element, such as phosphorus, antimony, or arsenic, may be doped into the substrate 100 to form an N-type substrate. The selection of doping elements for the substrate 100 may be based on actual needs and product performance. This disclosure does not limit the material of the substrate 100 or the doped elements.

[0041] In some embodiments, the material of the filler layer 160 may be an insulating material such as silicon oxide or silicon nitride.

[0042] In some embodiments, the filler layer 160 also covers the top surface of the substrate 100, and the filler layer 160 located on the top surface of the substrate 100 can be removed by chemical polishing to expose the top surface of the substrate 100.

[0043] refer to Figures 5 to 12 A patterned substrate 100 is formed to form a second groove 170. The second groove 170 is distributed at intervals along the second direction Y, and the second groove 170 is located on the top surface of the first groove 150. The first groove 150 and the second groove 170 form a channel column structure 110. A protective layer 180 is formed on the surface of the substrate 100. The protective layer 180 is different from the fill layer 160.

[0044] refer to Figure 5 A first protective layer 181 is formed, which is located on the top surface of the substrate.

[0045] In some embodiments, the material of the first protective layer 181 may be silicon nitride or similar materials. Silicon nitride is a relatively hard material, so that the morphology of the first protective layer 181 will not change significantly in subsequent steps, thereby making the pattern formed more accurate when patterning is performed using the first protective layer 181 as a mask.

[0046] refer to Figure 6A first dielectric layer 190 is formed, which is located on the sidewall of the channel column structure 110. In some embodiments, the first dielectric layer 190 can be formed by thermal oxidation of the channel column structure 110. The first dielectric layer 190 is used to protect the channel column structure 110 when the bit line structure is subsequently formed.

[0047] In some embodiments, the first dielectric layer 190 is also located on the bottom surface of the second groove 170. The first dielectric layer 190 located on the bottom surface of the second groove 170 can be removed by back etching to expose the surface of the substrate 100. By retaining the first dielectric layer 190 on the sidewall of the channel column structure 110, the channel column structure 110 can be protected from contamination when the bit line structure is subsequently formed.

[0048] refer to Figures 7 to 9 This forms a bit line structure 120; the bit line structure 120 is formed at the bottom of the second groove 170.

[0049] For details, please refer to Figure 7 This forms a fourth groove 200, which is located on the bottom surface of the second groove 170.

[0050] In some embodiments, the width of the fourth groove 200 along the first direction X can be greater than the spacing between adjacent channel pillar structures 110, thereby requiring less substrate material for metallization during the subsequent formation of the bit line structure 120. This facilitates the formation of a continuous first bit line conductive layer 121, thereby improving the transmission rate of the bit line structure 120. In other embodiments, the width of the fourth groove 200 along the first direction X can be equal to the spacing between adjacent channel pillar structures 110.

[0051] In some embodiments, the shape of the cross-sectional view of the fourth groove 200 along the first direction X may be an ellipse or a semicircle. In other embodiments, the shape of the cross-sectional view of the fourth groove 200 along the first direction X may also be a rectangle.

[0052] refer to Figure 8 The first conductive layer 121 is formed using a metal silicide process. The first conductive layer 121 is located on the surface of the fourth groove 200 facing the substrate 100.

[0053] In some embodiments, a first conductive layer 121 is formed within the substrate 100 by forming a metal layer on the surface of the substrate 100 and then performing rapid thermal annealing and selective wet etching. The metal layer may be made of a metal such as titanium or cobalt. The metal layer is then removed after its formation. Forming the first conductive layer 121 using a metal silicide process can reduce the resistance of the first conductive layer 121.

[0054] refer to Figure 9 A second bit line conductive layer 122 is formed, which fills the fourth groove 200. The first bit line conductive layer 121 and the second bit line conductive layer 122 constitute the bit line structure 120. The bit line structure 120 is located on the bottom surface of the first dielectric layer 190.

[0055] In some embodiments, the material of the second bit line conductive layer 122 may be metal. By setting the material of the second bit line conductive layer 122 to metal, the conduction speed of the bit line structure 120 can be improved, thereby improving the response speed of the semiconductor structure.

[0056] refer to Figure 10 and Figure 11 This forms the first isolation layer 210.

[0057] For details, please refer to Figure 10 This forms the first initial isolation layer 211.

[0058] In some embodiments, the first initial isolation layer 211 fills the second groove 170. The material of the first initial isolation layer 211 can be the same as the material of the filler layer 160, thereby reducing the types of materials used in the production process and providing a basis for removing part of the filler layer 160 and the first initial isolation layer 211 in the same step.

[0059] refer to Figure 11 The first initial isolation layer 211 is graphically visualized to form the first isolation layer 210; part of the fill layer 160 is removed, and the remaining fill layer 160 is flush with the upper surface of the first isolation layer 210.

[0060] In some embodiments, the process of patterning the first initial isolation layer 211 further includes: patterning a portion of the first dielectric layer 190 to expose a portion of the inner wall of the second groove 170, and the top surface of the first dielectric layer 190 is flush with the top surface of the first isolation layer 210.

[0061] In some embodiments, before forming the protective layer, the first dielectric layer 190 and part of the filler layer 160 can be removed in the same step; the top surface of the filler layer 160 is flush with the top surface of the first dielectric layer 190.

[0062] In some embodiments, the first dielectric layer 190, the first isolation layer 210, and the fill layer 160 may all be made of silicon oxide. Therefore, during the formation of the patterned first initial isolation layer 211, a portion of the first dielectric layer 190 and a portion of the fill layer 160 are removed. In other embodiments, the first dielectric layer 190, the first isolation layer 210, and the fill layer 160 are made of different materials. Therefore, the first dielectric layer 190, the first isolation layer 210, and the fill layer 160 are patterned separately until their top surfaces are flush. Patterning the first dielectric layer 190, the first isolation layer 210, and the fill layer 160 provides a process basis for the subsequent formation of the word line structure.

[0063] refer to Figure 12 A second protective layer 182 is formed, which is located on the inner wall of the second groove 170 and the side wall of the first protective layer 181. The first protective layer 181 and the second protective layer 182 constitute the protective layer 180.

[0064] In some embodiments, the material of the second protective layer 182 is the same as that of the first protective layer 181, such as silicon nitride, and the second protective layer 182 can be formed by depositing silicon nitride.

[0065] In some embodiments, during the deposition of the second protective layer 182, the second protective layer 182 also covers the entire surface of the first isolation layer 210. A portion of the second protective layer 182 on the surface of the first isolation layer 210 can be removed by etching back to expose the first isolation layer 210.

[0066] refer to Figures 13 to 16 This forms a character line structure 130, which is formed at the bottom of the second groove 170.

[0067] For details, please refer to Figure 13 After forming the protective layer 180, the process also includes removing the first dielectric layer 190 and part of the filler layer 160 in the same step; the remaining filler layer 160 is flush with the upper surface of the first isolation layer 210.

[0068] It is understood that the materials of the first dielectric layer 190 and the fill layer 160 can be the same. Therefore, by removing the first dielectric layer 190 and the fill layer 160 in the same step, the number of process steps in the entire production process can be reduced, and the height difference between the surfaces of the removed first dielectric layer 190 and the fill layer 160 can be smaller, thereby increasing the reliability of the formed semiconductor structure.

[0069] refer to Figure 14 A second dielectric layer 220 is formed, which is located on the top surface of the first dielectric layer 190 and covers part of the sidewall of the channel column structure 110.

[0070] In some embodiments, the second dielectric layer 220 can be formed by thermal oxidation; in other embodiments, the second dielectric layer 220 can also be formed by deposition. The second dielectric layer 220 can serve as dielectric layer 140 (see reference). Figure 1 This avoids direct contact between the character line structure and the channel column structure 110.

[0071] refer to Figure 15 This forms an initial character line structure 131, which fills the first groove 150 and the second groove 170.

[0072] In some embodiments, the material of the initial word line structure 131 may be a metal such as tungsten. By setting the material of the initial word line structure 131 to be a metal, the transmission rate of the word line structure can be improved.

[0073] refer to Figure 16 The initial word line structure 131 is patterned using the protective layer 180 as a mask until the top surface of the first isolation layer 210 is exposed, and the remaining initial word line structure 131 is used as the word line structure 130.

[0074] In some embodiments, the patterned initial word line structure 131 includes: removing the initial word line structure 131 located between the protective layers 180 and the initial word line structure 131 exposed by the protective layers 180 to form word line structures 130 spaced apart along the second direction Y. It is understood that the word line structure 130 includes word line structures 130 located on the sidewalls of the channel pillar structure 110 distributed along the first direction X and word line structures 130 spaced apart along the second direction Y to form word line structures 130 surrounding the channel pillar structure 110. By forming word line structures 130 surrounding the channel pillar structure 110, the integration density of the semiconductor structure can be improved.

[0075] refer to Figure 17 and Figure 18 This forms an isolation structure 230, which is located within the second groove 170 and between adjacent character line structures 130.

[0076] refer to Figure 17 A first isolation structure 231 is formed, which is located on the top surface of the first isolation layer 210, the sidewall of the word line structure 130, and the sidewall of the protective layer 180. By forming the first isolation structure 231, adjacent word line structures 130 can be isolated, thereby avoiding interference between adjacent word line structures 130 and improving the reliability of the semiconductor structure.

[0077] refer to Figure 18 Remove the protective layer 180 (reference) Figure 17A third groove (not shown) is formed; a second isolation structure 232 is formed, which fills the third groove. The first isolation structure 231 and the second isolation structure 232 constitute the isolation structure 230. In some embodiments, the protective layer 180 can be etched away from the top surface of the cross-section along the BB direction, and then a corresponding material can be deposited to form the second isolation structure 232. The second isolation structure 232 can serve as a protective layer for the word line structure 130, thereby reducing the stress on the word line structure 130 when the semiconductor structure is subjected to stress, thereby improving the reliability of the semiconductor structure.

[0078] This embodiment of the disclosure forms a word line structure 130 that surrounds the channel pillar structure 110 to form a fully all-around gate transistor structure. After forming the word line structure 130, an isolation structure 230 is formed between adjacent word line structures 130. The isolation structure 230 can increase the insulation between adjacent word line structures 130, thereby improving the performance of the semiconductor structure. This improves the integration density of the semiconductor structure while satisfying the performance requirements of the semiconductor structure.

[0079] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure, which is largely the same as the aforementioned embodiment, with the main differences including: a different method for forming a protective layer and a different structure of the protective layer. The method for fabricating a semiconductor structure according to another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the aforementioned embodiments can be referred to the corresponding descriptions in the aforementioned embodiments, and will not be repeated hereafter.

[0080] refer to Figures 19 to 30 , Figure 19 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figures 20 to 30 For along Figure 19 A cross-sectional view along the direction of the dashed line.

[0081] refer to Figure 19 The semiconductor structure includes: a substrate 300; channel pillar structures 310 spaced apart along a first direction X and a second direction; a bit line structure 320 extending along the first direction; a word line structure 330 extending along the second direction; and a dielectric layer 340 surrounding the surface of the channel pillar structures.

[0082] refer to Figure 20 A substrate 300 is provided, the substrate 300 including: first grooves 350 spaced apart along a first direction X.

[0083] refer to Figure 21 The process involves forming a fill layer 360, and prior to patterning the substrate 300, a partial removal of the fill layer 360 is included. Removing the partial fill layer 360 provides a process basis for the subsequent formation of the first initial protective layer.

[0084] refer to Figure 22 A first protective layer 381 is formed, which is located on the top surface of the filler layer 360.

[0085] refer to Figure 23 The first initial protective layer 383 and the substrate 300 are patterned to form the second groove 370, and the remaining first initial protective layer 383 serves as the first protective layer 381. The first groove 350 and the second groove 370 form a channel column structure 310.

[0086] In some embodiments, a mask layer 384 may be formed before the first initial protective layer 383 is patterned, and the mask layer 384 may be made of the same material as the first initial protective layer 383.

[0087] refer to Figure 24 After forming the second groove 370, the process also includes forming a first dielectric layer 390, which is located on the side wall of the channel column structure 310. The first dielectric layer 390 protects the channel column structure 310 from being affected when the bit line structure is subsequently formed.

[0088] Continue to refer to Figure 24 The fourth groove 400 is formed, which is located on the bottom surface of the second groove 170. The formation of the fourth groove 400 provides space and process basis for the subsequent formation of the bit line structure.

[0089] refer to Figure 25 A first bit line conductive layer 321 is formed using a metal silicide process. The first bit line conductive layer 321 is located on the surface of the fourth groove 400 facing the substrate 300. A second bit line conductive layer 322 is formed, filling the fourth groove 400. The first bit line conductive layer 321 and the second bit line conductive layer 322 constitute the bit line structure 320. Forming the first bit line conductive layer 321 using a metal silicide process can reduce the resistance of the first bit line conductive layer 321. Forming the second bit line conductive layer 322 can reduce the contact resistance between the bit line structure 320 and the substrate 300. The bit line structure 320 is located on the bottom surface of the first dielectric layer 390.

[0090] refer to Figure 26 A first isolation layer 410 is formed, which is located within the second groove 370 and on the top surface of the bit line structure 320. In some embodiments, the first isolation layer 410 can be formed by first filling the second groove 370 and then etching back.

[0091] refer to Figure 27A second protective layer 382 is formed, which is located on the inner wall of the second groove 370 and the side wall of the first protective layer 381. The first protective layer 381 and the second protective layer 382 constitute the protective layer 380. The protective layer 380 can be used as part of the isolation structure, and the protective layer 380 can also be used as a mask for the subsequent formation of the word line structure.

[0092] In some embodiments, the second protective layer 382 is also located on the sidewall of the mask layer 384.

[0093] refer to Figure 28 In some embodiments, the step of removing a portion of the fill layer 360 may further include: removing a portion of the fill layer 360 after forming the protective layer 380 and before forming the initial word line structure. Removing a portion of the fill layer 360 provides a process basis and space for the subsequent formation of the initial word line structure.

[0094] In some embodiments, after removing the filler layer 360, a second dielectric layer 420 is further formed. In some embodiments, the second dielectric layer 420 can be formed by oxidizing a portion of the channel columnar structure 310, and the second dielectric layer 420 is located within the channel columnar structure 310; in another embodiment, the second dielectric layer can be formed by deposition, and the second dielectric layer is located on the sidewall of the channel columnar structure. The second dielectric layer 420 is used to prevent the word line structure from directly contacting the channel columnar structure 310.

[0095] In some embodiments, the second dielectric layer 420 is dielectric layer 340 (reference). Figure 19 Part of ).

[0096] refer to Figure 29 An initial word line structure 331 is formed, which is located on the top surface of the first dielectric layer 390 and the first isolation layer 410 and the bottom surface of the protective layer 380.

[0097] refer to Figure 30 The initial word line structure 331 is patterned using the protective layer 380 as a mask until the top surface of the first isolation layer 410 is exposed. The remaining initial word line structure 331 serves as the word line structure 330. The word line structure 330 includes word line structures 330 located on the sidewalls of the channel pillar structure 310 distributed along the first direction X and word line structures 330 spaced apart along the second direction Y, to form a word line structure 330 surrounding the channel pillar structure 310. By forming a word line structure 330 surrounding the channel pillar structure 310, the integration density of the semiconductor structure can be improved.

[0098] refer to Figure 31An isolation structure 430 is formed, specifically including: forming a first isolation structure 431, which is located on the top surface of the first isolation layer 410, the sidewall of the word line structure 330, and the sidewall of the protective layer 380. The first isolation structure 431 and the protective layer 380 constitute the isolation structure 430. By forming the isolation structure 430, the word line structure 330 can be isolated from the outside world, thereby protecting the word line structure 330 and reducing the stress on the word line structure 330, thus improving the reliability of the semiconductor structure.

[0099] In some embodiments, the mask layer 384 may also be part of the isolation structure 430.

[0100] In this embodiment, a first initial protective layer 383 is formed before the channel column structure 310 is formed, and then the channel column structure 310 is formed. At this time, part of the top surface of the partial filling layer 360 includes the first protective layer 381. Then, a second protective layer 382 is formed. The second protective layer 382 and the first protective layer 381 together serve as the protective layer 380. In the subsequent formation of the word line structure 330, the protective layer 380 also serves as a mask.

[0101] This disclosure embodiment forms a word line structure 130 that surrounds the channel pillar structure 110 to form a fully all-around gate transistor structure, thereby improving the integration density of the semiconductor structure while satisfying the performance requirements of the semiconductor structure.

[0102] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure, which is largely the same as the aforementioned embodiment, with the main differences including: a different method for forming a protective layer and a different structure of the protective layer. The following will describe a method for fabricating a semiconductor structure according to another embodiment of this disclosure in conjunction with the accompanying drawings. It should be noted that the same or corresponding parts as those in the aforementioned embodiments can be referred to the corresponding descriptions in the aforementioned embodiments, and will not be repeated hereafter.

[0103] refer to Figures 32 to 40 , Figure 32 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figures 33 to 40 For along Figure 32 A cross-sectional view along the direction of the dashed line.

[0104] refer to Figure 32 The semiconductor structure includes: a substrate 500; channel pillar structures 510 spaced apart along a first direction X and a second direction; a bit line structure 520 extending along the first direction; a word line structure 530 extending along the second direction; and a dielectric layer 540 surrounding the surface of the channel pillar structures.

[0105] refer to Figure 33A substrate 500 is provided, the substrate 500 includes a fill layer 560, and the substrate 500 also includes second grooves 570 spaced apart along a second direction and channel columnar structures 510 between the second grooves 570.

[0106] In some embodiments, the method of forming a protective layer may include forming a first protective layer 581, the first protective layer 581 being located on the top surface of the substrate 500.

[0107] In some embodiments, a first dielectric layer 590 is formed on the sidewall of the channel column structure 510, the first dielectric layer 590 being used to protect the channel column structure 510 from being affected during the subsequent formation of the bit line structure.

[0108] refer to Figure 34 In some embodiments, the method of forming the bit line structure 520 may include: forming a fourth groove located on the bottom surface of the second groove 570; forming a first bit line conductive layer 521 using a metal silicide process, the first bit line conductive layer 521 located on the surface of the fourth groove facing the substrate 500; and forming a second bit line conductive layer 522 that fills the fourth groove. The first bit line conductive layer 521 and the second bit line conductive layer 522 constitute the bit line structure 520.

[0109] The resistance of the bit line structure 520 can be reduced by forming the first bit line conductive layer 521 through the metal silicide process, and the contact resistance between the bit line structure 520 and the substrate 500 can be reduced by forming the second bit line conductive layer 522 that fills the fourth groove, thereby improving the performance of the semiconductor structure.

[0110] refer to Figure 35 A first isolation layer 610 is formed, located within the second groove 570, with the top surface of the first isolation layer 610 lower than the bottom surface of the first protective layer 581. In some embodiments, the method for forming the first isolation layer 610 may be to first form a first initial isolation layer that fills the second groove 570, and then etch back the first initial isolation layer to form the first isolation layer 610. During the back etching of the first initial isolation layer, a portion of the first dielectric layer 590 and the filler layer 560 are removed in the same step, so that the top surface of the first dielectric layer 590 is flush with the upper surface of the first isolation layer 610.

[0111] After forming the first insulating layer 610, the process further includes forming a second dielectric layer 620. The second dielectric layer 620 is located on the top surface of the first dielectric layer 590 and covers a portion of the sidewalls of the channel columnar structure 510. In some embodiments, the second dielectric layer 620 can be formed by thermal oxidation. By oxidizing a portion of the sidewalls of the channel columnar structure 510, the second dielectric layer 620 is formed. The second dielectric layer 620 formed by thermal oxidation has a high density, and thus can be used as the dielectric layer 540 (see reference). Figure 32 ).

[0112] refer to Figure 36 and Figure 37 An initial character line structure 531 is formed, which fills the first groove and the second groove 570. The top surface of the initial character line structure 531 is flush with the bottom surface of the first protective layer 581.

[0113] In some embodiments, the initial word line structure 531 includes a word line conductive layer 532 and a word line protective layer 533, wherein the word line conductive layer 532 is used to transmit signals and the word line protective layer 533 is used to protect the word line conductive layer 532.

[0114] refer to Figure 38 A second protective layer 582 is formed, located on the sidewall of the first protective layer 581 and on the top surface of the second groove 570. The first protective layer 581 and the second protective layer 582 constitute the protective layer 580. The formation of the second protective layer 582 provides a mask for the subsequent patterned initial character line structure 531. The spacing between adjacent character line structures formed subsequently can be controlled by controlling the width of the second protective layer 581.

[0115] refer to Figure 39 The initial word line structure 531 and the first isolation layer 610 are patterned using the protective layer 580 as a mask until the top surface of the bit line structure 520 is exposed. The remaining initial word line structure 531 serves as the word line structure 530. Patterning the initial word line structure 531 forms a spaced word line structure 530, and provides a process basis for the subsequent formation of an isolation structure with air gaps.

[0116] refer to Figure 40 A first isolation structure 631 and a second isolation structure 632 are formed. The first isolation structure 631 is an air gap formed by the first isolation layer 610, the word line structure 530, and the second isolation structure 632. The second isolation structure 632 is located between the word line structures 530, and the top surface of the second isolation structure 632 is flush with the top surface of the word line structure 530. By forming an isolation structure 630 with an air gap, the parasitic capacitance between adjacent word line structures 530 can be reduced, thereby improving the electrical performance of the semiconductor structure.

[0117] In this embodiment of the disclosure, by forming an initial word line structure 531 that fills the first groove and the second groove 570 during the formation of the initial word line structure 531, a protective layer 580 that is only located on the surface of the substrate 500 is formed during the formation of the second protective layer 582, and an isolation structure 630 with an air gap is subsequently formed during the formation of the isolation structure 630, thereby reducing the parasitic capacitance between adjacent word line structures 530.

[0118] This disclosure embodiment forms a word line structure 530 that surrounds the channel pillar structure 510 to form a fully all-around gate transistor structure, thereby improving the integration density of the semiconductor structure while satisfying the performance requirements of the semiconductor structure.

[0119] This disclosure also provides a semiconductor structure that can be formed using some or all of the above steps. The following description, in conjunction with the accompanying drawings, will describe a method for fabricating a semiconductor structure according to another embodiment of this disclosure. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated hereafter.

[0120] refer to Figure 1 , Figure 18 , Figure 19 , Figure 30 , Figure 32 and Figure 40 , Figure 1 , Figure 19 and Figure 32 Top views of semiconductor structures provided in different embodiments of this disclosure. Figure 18 , Figure 29 and Figure 36 The different embodiments of this disclosure provide the following: Figure 1 , Figure 19 and Figure 32 A cross-sectional view along the direction of the dashed line.

[0121] For details, please refer to Figure 1 and Figure 18The semiconductor structure includes: a substrate 100; channel pillar structures 110 located within the substrate 100 and spaced apart along a first direction X and a second direction Y; bit line structures 120 connected to the channel pillar structures 110, bit line structures 130 spaced apart along the second direction Y within the substrate 100, and bit line structures 120 located on the bottom surface of the channel pillar structures 110; and a first isolation layer 210. 10 is located on the top surface of bit line structure 120; fill layer 160 is located within substrate 100, and the top surface of fill layer 160 is flush with the top surface of first isolation layer 210; word line structure 130 surrounds channel pillar structure 110 and is spaced apart along the second direction Y; isolation structure 230 is located at least between adjacent word line structures 130; dielectric layer 140 surrounds the surface of channel pillar structure 110.

[0122] By setting the word line structure 130 to surround the channel pillar structure 110, a fully surrounding gate transistor structure can be formed, thereby improving the integration density of the semiconductor structure and also meeting the performance requirements of the semiconductor structure.

[0123] In some embodiments, the channel column structure 110 includes a first doped region, a channel region, and a second doped region arranged sequentially. The first doped region is in contact with the bit line structure 120, and the channel region and the second doped region are located between adjacent word line structures 130. The doped ions of the first doped region, the channel region, and the second doped region are the same.

[0124] By doping the channel columnar structure 110 with the same type of ions, a junctionless transistor can be formed. A junctionless transistor is one where the dopant ions in the first doped region, channel region, and second doped region are of the same type, for example, both dopant ions are N-type ions. Furthermore, the dopant ions in the first doped region, channel region, and second doped region can be the same. Here, "junctionless" refers to the absence of a PN junction; that is, the transistor formed by the channel columnar structure 110 does not have a PN junction. Because the device is a junctionless transistor, it is advantageous to avoid the phenomenon of fabricating ultra-steep PN junctions at the nanoscale using ultra-steep source-drain concentration gradient doping processes. Therefore, it can avoid problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes. It also helps suppress short-channel effects, allowing operation at the nanometer scale, thus contributing to further improvements in the integration density and electrical performance of semiconductor structures. It is understood that the additional doping here refers to doping performed to ensure that the dopant ion types in the first and second doped regions are different from those in the channel region.

[0125] In some embodiments, the bit line structure 120 includes: a first bit line conductive layer 121, which is located within the substrate 100 and contacts the bottom surface of the channel pillar structure 110; and a second bit line conductive layer 122, which is located on the top surface of the first bit line conductive layer 121. Forming the first bit line conductive layer 121 can reduce the resistance of the bit line structure 120, and forming the second bit line conductive layer 122 can increase the transmission speed of the bit line structure 120.

[0126] In some embodiments, the top surface of the second bit line conductive layer 122 is lower than the bottom surface of the channel column structure 110, and the bottom surface of the first isolation layer 210 is lower than the bottom surface of the channel column structure 110. In other words, the top surface of the second bit line conductive layer 122 is lower than the bottom surface of the channel column structure 110, and a portion of the first isolation layer 210 is surrounded by the first bit line conductive layer 121, thereby increasing the insulation performance between the word line structure 130 and the bit line structure 120.

[0127] In some embodiments, a first dielectric layer 190 and a second dielectric layer 220 are also included. The first dielectric layer 190 is located on the sidewall of the channel column structure 110, and the second dielectric layer 220 is located on the first dielectric layer 190. The second dielectric layer 220 can serve as a dielectric layer 140, thereby preventing the channel column structure 110 from directly contacting the word line structure 130.

[0128] In some embodiments, the isolation structure 230 includes: a first isolation structure 231 located on the top surface of the first isolation layer 210 and the sidewall of the word line structure 130; and a second isolation structure 232 located on the top surface of the channel pillar structure 110 and between the channel pillar structure 110 and the first isolation structure 231. By forming the first isolation structure 231, adjacent word line structures 130 can be isolated, thereby avoiding interference between adjacent word line structures 130 and improving the reliability of the semiconductor structure. By forming the second isolation structure 232, the stress on the word line structure 130 can be reduced, thereby improving the reliability of the semiconductor structure.

[0129] This embodiment of the disclosure forms a word line structure 130 that surrounds the channel pillar structure 110 to form a fully all-around gate transistor structure. After forming the word line structure 130, an isolation structure 230 is formed between adjacent word line structures 130. The isolation structure 230 can increase the insulation between adjacent word line structures 130, thereby improving the performance of the semiconductor structure. This improves the integration density of the semiconductor structure while satisfying the performance requirements of the semiconductor structure.

[0130] Another embodiment of this disclosure also provides another semiconductor structure, which is substantially the same as the foregoing embodiments, with the main differences including: a different isolation structure. The fabrication method of the semiconductor structure provided in another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated hereafter.

[0131] refer to Figure 19 and Figure 31 In other embodiments, the semiconductor structure includes: a substrate 300; a channel pillar structure 310; a bit line structure 320 communicating with the channel pillar structure 310; a first isolation layer 410 located on the top surface of the bit line structure 320; a fill layer 360 located within the substrate 300, with the top surface of the fill layer 360 flush with the top surface of the first isolation layer 410; a word line structure 330 surrounding the channel pillar structure 310; an isolation structure 430 located at least between adjacent word line structures 330; and a dielectric layer 340 surrounding the surface of the channel pillar structure 310.

[0132] The bit line structure 320 includes: a first bit line conductive layer 321, which is located within the substrate 300 and is in contact with the bottom surface of the channel column structure 310; and a second bit line conductive layer 322, which is located on the top surface of the first bit line conductive layer 321.

[0133] In some embodiments, the isolation structure 430 may include: a protective layer 380 located on the top surface and part of the sidewalls of the channel columnar structure 310; and a first isolation structure 431 located on the top surface of the first isolation layer 410, the sidewalls of the word line structure 330, and the sidewalls of the protective layer 380. By forming the isolation structure 430, the word line structure 330 can be isolated from the outside world, thereby protecting the word line structure 330 and reducing the stress on the word line structure 330, thus improving the reliability of the semiconductor structure.

[0134] In some embodiments, the protective layer 380 may include a first protective layer 381 and a second protective layer 382.

[0135] In some embodiments, the semiconductor structure further includes a first dielectric layer 390 and a second dielectric layer 420. The first dielectric layer 390 is located on the sidewall of the channel pillar structure 310, and the second dielectric layer 420 is located on the first dielectric layer 390. The second dielectric layer 420 can serve as a dielectric layer 340, thereby preventing the channel pillar structure 310 from directly contacting the word line structure 330.

[0136] In some embodiments, the semiconductor structure further includes a mask layer 384, which is located on the top surface of the channel pillar structure 310 and can protect the channel pillar structure 310.

[0137] This disclosure embodiment forms a word line structure 330 that surrounds the channel column structure 310 to form a fully all-around gate transistor structure, thereby improving the integration density of the semiconductor structure while satisfying the performance requirements of the semiconductor structure.

[0138] Another embodiment of this disclosure also provides another semiconductor structure, which is substantially the same as the foregoing embodiments, with the main differences including: a different isolation structure. The fabrication method of the semiconductor structure provided in another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated hereafter.

[0139] refer to Figure 32 and Figure 40 In other embodiments, the semiconductor structure includes: a substrate 500; a channel pillar structure 510; a bit line structure 520 communicating with the channel pillar structure 510; a first isolation layer 610 located on the top surface of the bit line structure 520; a filler layer 560 located within the substrate 500, with the top surface of the filler layer 560 flush with the top surface of the first isolation layer 610; a word line structure 530 surrounding the channel pillar structure 510; an isolation structure 630 located at least between adjacent word line structures 530; and a dielectric layer 540 surrounding the surface of the channel pillar structure 510.

[0140] In some embodiments, the isolation structure 630 includes a first isolation structure 631 and a second isolation structure 632. The first isolation structure 631 is an air gap formed by the first isolation layer 610, the word line structure 530, and the second isolation structure 632. The second isolation structure 632 is located between the word line structures 530, and the top surface of the second isolation structure 632 is flush with the top surface of the word line structure 530. By providing the isolation structure 630 with the air gap, the parasitic capacitance between adjacent word line structures 530 can be reduced.

[0141] In some embodiments, the bit line structure 520 includes: a first bit line conductive layer 521, which is located within the substrate 500 and is in contact with the bottom surface of the channel column structure 510; and a second bit line conductive layer 522, which is located on the top surface of the first bit line conductive layer 521.

[0142] In some embodiments, the word line structure 530 includes a word line conductive layer 532 and a word line protective layer 533 stacked together.

[0143] The semiconductor structure also includes a first dielectric layer 590 and a second dielectric layer 620. The first dielectric layer 590 is located on the sidewall of the channel pillar structure 510, and the second dielectric layer 620 is located on the first dielectric layer 590. The second dielectric layer 620 can serve as a dielectric layer 540, thereby avoiding direct contact between the channel pillar structure 510 and the word line structure 530.

[0144] This disclosure embodiment forms a word line structure 530 that surrounds the channel pillar structure 510 to form a fully all-around gate transistor structure, thereby improving the integration density of the semiconductor structure while satisfying the performance requirements of the semiconductor structure.

[0145] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including first grooves spaced apart along a first direction and a filling layer located within the first grooves; The substrate is patterned to form a second groove, the second groove being spaced apart along a second direction, and the second groove being located in the top surface of the sidewall of the first groove, the first groove and the second groove forming a channel column structure; A protective layer is formed on the surface of the substrate, the protective layer being different from the filler layer; A bit line structure is formed at the bottom of the second groove; A first isolation layer is formed, which is located within the second groove and on the top surface of the bit line structure; Remove part of the filler layer, leaving the remaining filler layer flush with the upper surface of the first isolation layer; A character line structure is formed, the character line structure surrounds the channel column structure and is spaced apart along the second direction; Forming an isolation structure, the isolation structure being located within the second groove and between adjacent word line structures; the method of forming the protective layer includes: Before patterning the substrate, the method further includes: removing a portion of the filler layer and forming a first initial protective layer on the top surface of the filler layer; The first initial protective layer and the substrate are patterned to form the second groove, with the remaining first initial protective layer serving as the first protective layer; A second protective layer is formed, which is located on the inner wall of the second groove and the side wall of the first protective layer. The first protective layer and the second protective layer constitute the protective layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Also includes: A first dielectric layer is located on the top surface of the bit line structure and the sidewall of the channel columnar structure. The method for forming the bit line structure includes: An initial word line structure is formed, wherein the initial word line structure is located on the top surface of the first dielectric layer and the first isolation layer and on the bottom surface of the protective layer; The initial word line structure is patterned using the protective layer as a mask until the top surface of the first isolation layer is exposed, and the remaining initial word line structure is used as the word line structure.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The step of removing part of the filler layer includes: Before patterning the substrate, a portion of the filler layer is removed; After the protective layer is formed but before the initial word line structure is formed, part of the fill layer is removed.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The method of forming the isolation structure includes: A first isolation structure is formed, which is located on the top surface of the first isolation layer, the sidewall of the word line structure and the sidewall of the protective layer, and the first isolation structure and the protective layer constitute the isolation structure.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method for forming the bitline structure includes: A fourth groove is formed, the fourth groove being located on the bottom surface of the second groove; A first conductive line layer is formed using a metal silicide process, and the first conductive line layer is located on the surface of the fourth groove facing the substrate. A second bit line conductive layer is formed, which fills the fourth groove. The first bit line conductive layer and the second bit line conductive layer constitute the bit line structure.

6. A semiconductor structure, characterized in that, include: Substrate; A channel columnar structure is located within the substrate, and the channel columnar structure is arranged at intervals along a first direction and a second direction; Bit line structure, the bit line structure is connected to the channel column structure, the bit line structure is arranged at intervals in the substrate along the second direction, and the bit line structure is located on the bottom surface of the channel column structure; A first isolation layer is located on the top surface of the bit line structure; A filler layer, wherein the filler layer is located within the substrate and the top surface of the filler layer is flush with the top surface of the first isolation layer; A character line structure, wherein the character line structure surrounds the channel column structure and is spaced apart along the second direction; An isolation structure, wherein the isolation structure is located at least between adjacent word line structures; The isolation structure includes a first isolation structure and a second isolation structure. The first isolation structure is the first isolation layer. The air gap is formed by the first isolation layer, the word line structure and the second isolation structure. The second isolation structure is located between the word line structures, and the top surface of the second isolation structure is flush with the top surface of the word line structure.

7. The semiconductor structure according to claim 6, characterized in that, The isolation structure includes: A protective layer is located on the top surface and part of the sidewalls of the channel columnar structure; The first isolation structure is located on the top surface of the first isolation layer, the sidewall of the word line structure, and the sidewall of the protective layer.

8. The semiconductor structure according to claim 6, characterized in that, The isolation structure includes: A first isolation structure is located on the top surface of the first isolation layer and the side wall of the word line structure. The second isolation structure is located on the top surface of the channel column structure and between the channel column structure and the first isolation structure.

9. The semiconductor structure according to claim 6, characterized in that, The bitline structure includes: The first bit line conductive layer is located within the substrate and is in contact with the bottom surface of the channel columnar structure. The second bit line conductive layer is located on the top surface of the first bit line conductive layer.

10. The semiconductor structure according to claim 9, characterized in that, The top surface of a portion of the second bit line conductive layer is lower than the bottom surface of the channel columnar structure, and the bottom surface of the first isolation structure is lower than the bottom surface of the channel columnar structure.

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