Te-based chalcogenic austenite threshold switching device and nonvolatile memory array

Abstract

The application discloses a Te-based sulfide austenite threshold switch device and a nonvolatile memory array, and belongs to the technical field of threshold switch device preparation. The threshold switch device comprises a top electrode, a bottom electrode and a functional layer with a threshold switch function between the top electrode and the bottom electrode. The functional layer comprises a Te-based sulfide material layer and a dielectric layer. The dielectric layer is a compound XY, X is one or more elements selected from Al, Zr, Ta, Zn, Si and B, Y is one or more elements selected from O, N and S, and the total thickness of the dielectric layer is not more than 5 nm. The application studies the gating characteristics of the Te-based sulfide material layer. After a specific dielectric layer is superimposed on the basis of the Te-based sulfide material layer to serve as the functional layer, the device can be prevented from being broken down, the leakage current of the device can be effectively inhibited, and the threshold voltage can be improved.

Description

Technical Field

[0001] This invention belongs to the field of threshold switching device fabrication technology, and more specifically, relates to a Te-based chalcogenide austenitic threshold switching device and a non-volatile memory array. Background Technology

[0002] Oswald threshold switches (OTSs) offer advantages such as high switching speed, low manufacturing cost, and ease of 3D stacking, making them suitable for DRAM applications in terms of speed and density. Currently, there are solutions for information storage based on controllable threshold voltage changes using Oswald threshold switches. However, the two threshold voltage states achieved by Te-based Oswald threshold switches suffer from small threshold increments and large leakage current in the low threshold state, making them unsuitable for large-scale memory arrays. Therefore, there is a need for an Oswald threshold switch device with large threshold increments and low leakage current to realize ultra-large-scale OTS-only memory arrays. Summary of the Invention

[0003] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a Te-based chalcogenide austenitic threshold switch device and a non-volatile memory array, the purpose of which is to solve the technical problems of small threshold increment and large leakage current of threshold switch devices.

[0004] To achieve the above objectives, according to one aspect of the present invention, a Te-based chalcogenide austenitic threshold switch device is provided, comprising a top electrode and a bottom electrode, and a functional layer with threshold switching function located between the top electrode and the bottom electrode, wherein the functional layer comprises a Te-based chalcogenide material layer and a dielectric layer, the dielectric layer being a compound XY, where X is one or more elements selected from Al, Zr, Ta, Zn, Si, and B, and Y is one or more elements selected from O, N, and S, and the total thickness of the dielectric layer does not exceed 5 nm.

[0005] In one embodiment, the Te-based chalcogenide material layer is A. a Te, where A is one or more elements selected from B, C, Al, Si, P, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, As, In, Sn, and Sb, and the value of a is 0.1 to 1.

[0006] In one embodiment, the total thickness d1 of the Te-based chalcogenide material layer ranges from 5 nm to 100 nm.

[0007] In one embodiment, the total thickness d1 of the Te-based chalcogenide material layer ranges from 10 nm to 40 nm, and the total thickness d2 of the dielectric layer ranges from 0.5 nm to 5 nm.

[0008] In one embodiment, the dielectric layer is Al2O3 or SiO2.

[0009] In one embodiment, the functional layer includes a Te-based chalcogenide material layer and a dielectric layer.

[0010] In one embodiment, the functional layer includes a Te-based chalcogenide material layer and two dielectric layers, wherein the Te-based chalcogenide material layer is sandwiched between the two dielectric layers, and the total thickness of the two dielectric layers does not exceed 5 nm.

[0011] In one embodiment, the materials of the top electrode and the bottom electrode include one or more of W, Pt, Au, Ti, Al, Ag, Cu, or Ni.

[0012] According to another aspect of the present invention, a non-volatile memory array is provided, comprising arrayed non-volatile memory cells, wherein the non-volatile memory cells include the Te-based chalcogenide austenitic threshold switching device described above.

[0013] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0014] This invention studies the gate characteristics of Te-based chalcogenide material layers. A specific dielectric layer is superimposed on the Te-based chalcogenide material layer as a functional layer. This dielectric layer is a compound XY, where X is one or more elements selected from Al, Zr, Ta, Zn, Si, and B, and Y is one or more elements selected from O, N, and S. The thickness of the dielectric layer does not exceed 5 nm. The choice of dielectric layer is crucial. If the dielectric constant of the dielectric layer is too low, it is insufficient to suppress device leakage current; if the dielectric constant of the dielectric layer is too high or the thickness of the dielectric layer is too thick, it is difficult to turn on the device. Simultaneously, a contact barrier exists between the dielectric layer and the Te-based chalcogenide material layer. If the material selection is inappropriate, the contact barrier will be too high, requiring a higher turn-on voltage. Excessive voltage can lead to breakdown risk in the Te-based chalcogenide material layer. This invention comprehensively considers breakdown risk, leakage current suppression effect, and turn-on difficulty, finding that using the aforementioned material to fabricate a dielectric layer of no more than 5 nm can ensure that the device is not broken down while effectively suppressing device leakage current and increasing the threshold voltage.

[0015] Applying the aforementioned Te-based chalcogenide austenitic threshold switching device to non-volatile memory arrays, the inherent threshold voltage difference during forward and reverse operation of chalcogenide materials is amplified by the different polarities of the dielectric layer under these conditions. This further increases the threshold voltage increment, thereby improving the read margin of large-scale memory arrays. Furthermore, lower leakage current enables large-scale integration of memory arrays.

[0016] Furthermore, the preferred range for the total thickness d1 of the Te-based chalcogenide material layer is 10nm≤d1≤40nm, and the preferred range for the total thickness d2 of the dielectric layer is 0.5nm≤d2≤5nm. The Te-based chalcogenide austenitic threshold switch device prepared within this range can achieve the electrical performance of a normal selector, as well as the effects of a high threshold voltage and a low leakage current.

[0017] Furthermore, the dielectric layer is made of Al2O3 or SiO2. This film is simple to prepare and can easily achieve the normal electrical performance of the selector, as well as the effects of high threshold voltage and low leakage current. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a Te-based chalcogenide austenitic threshold switch device provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of another Te-based chalcogenide austenitic threshold switch device provided in an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of another Te-based chalcogenide austenitic threshold switch device provided in an embodiment of the present invention;

[0021] Figure 4 These are initialization curves of a Te-based chalcogenide austenitic threshold switch device with an Al2O3 dielectric layer and a Te-based chalcogenide austenitic threshold switch device without a dielectric layer, as shown in the embodiments of the present invention.

[0022] Figure 5(a) and 5(b) These are pulse activation diagrams of a Te-based chalcogenide austenitic threshold switch device with a dielectric layer and a Te-based chalcogenide austenitic threshold switch device without a dielectric layer, respectively, in embodiments of the present invention.

[0023] Figure 5(c) is a schematic diagram of the initialization curve of the Te-based chalcogenide austenitic threshold switch containing a SiO2 dielectric layer in an embodiment of the present invention;

[0024] Figure 6 This is a voltage-current scan curve when the Al2O3 dielectric layer thickness exceeds 5nm in one embodiment;

[0025] Figure 7 This is a voltage-current scan curve when the SiO2 dielectric layer thickness exceeds 5nm in one embodiment;

[0026] Figure 8 This is a voltage-current scan curve for a TiO2 dielectric layer with a thickness not exceeding 5 nm in one embodiment;

[0027] Figure 9 This is a voltage and current scan curve of a non-volatile memory cell in one embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0029] This invention relates to a Te-based chalcogenide austenitic threshold switch device, characterized in that it includes a top electrode and a bottom electrode, and a functional layer with threshold switching function located between the top electrode and the bottom electrode. The functional layer includes a Te-based chalcogenide material layer and a dielectric layer. The dielectric layer is a compound XY, where X is one or more elements selected from Al, Zr, Ta, Zn, Si, and B, and Y is one or more elements selected from O, N, and S. The total thickness of the dielectric layer does not exceed 5 nm.

[0030] Specifically, the stacking order of the Te-based chalcogenide material layer and the dielectric layer can be flexibly set, and the dielectric layer can be one layer or two layers.

[0031] like Figure 1 The diagram shown is a schematic diagram of the Te-based chalcogenide austenitic threshold switch device in the first embodiment. Its structure from top to bottom consists of a top electrode 1, a dielectric layer 2, a Te-based chalcogenide material layer 3, and a bottom electrode 4.

[0032] like Figure 2 The diagram shown is a schematic diagram of the Te-based chalcogenide austenitic threshold switch device in the second embodiment. Its structure from top to bottom consists of a top electrode 1, a Te-based chalcogenide material layer 3, a dielectric layer 2, and a bottom electrode 4.

[0033] like Figure 3 The diagram shown is a schematic diagram of the Te-based chalcogenide austenitic threshold switch device in the third embodiment. Its structure from top to bottom consists of a top electrode 1, a dielectric layer 2, a Te-based chalcogenide material layer 3, a dielectric layer 2, and a bottom electrode 4.

[0034] The Te-based chalcogenide austenitic threshold switch device designed in this invention has a simple structure. By optimizing the functional layer with threshold switching function and introducing a specific dielectric layer on the basis of the Te-based chalcogenide material layer, it is possible to ensure that the device is not broken down while effectively suppressing the leakage current and improving the threshold voltage.

[0035] Optionally, the Te-based chalcogenide material layer is A aTe, where A is one or more elements selected from B, C, Al, Si, P, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, As, In, Sn, and Sb, and the value of a is 0.1 to 1.

[0036] Optionally, the total thickness d1 of the Te-based chalcogenide material layer is in the range of 5 nm ≤ d1 ≤ 100 nm. Specifically, the preferred range of the total thickness d1 of the Te-based chalcogenide material layer is 10 nm ≤ d1 ≤ 40 nm, and the preferred range of the total thickness d2 of the dielectric layer is 0.5 nm ≤ d2 ≤ 5 nm. The Te-based chalcogenide austenitic threshold switch device prepared within this range can achieve the electrical performance of a normal selector transistor as well as the effects of a high threshold voltage and low leakage current.

[0037] Optionally, the materials of the top electrode and the bottom electrode include one or more of W, Pt, Au, Ti, Al, Ag, Cu, or Ni.

[0038] In this invention, the selection of dielectric layer material and thickness are the most critical.

[0039] Taking GeTe9 as the Te-based chalcogenide material layer as an example, such as Figure 4 The figure shows a comparison of the IV curves of a Te-based chalcogenide austenitic threshold switch device with and without a dielectric layer. The figure shows that the device conducts when the absolute value of the voltage applied across the electrodes is higher than the absolute value of the threshold voltage, and turns off when the absolute value of the voltage applied across the electrodes is lower than the absolute value of the threshold voltage. Without the dielectric layer, the initial voltage of the device is 2.36V. After introducing the Al2O3 dielectric layer, the initial voltage of the device is 5.69V, showing a significant increase in the initial voltage.

[0040] like Figure 5(a) and 5(b) The figures show pulse switching diagrams of the Te-based chalcogenide austenitic threshold switching device with and without a dielectric layer. Figure 5(a) shows the pulse switching diagram with an Al2O3 dielectric layer, and Figure 5(b) shows the pulse switching diagram without a dielectric layer. With a dielectric layer, the threshold voltage is 2.75V, and without a dielectric layer, the threshold voltage is 1.5V. The threshold voltage of the device is significantly improved after the introduction of the dielectric layer.

[0041] Figure 5(c) shows the initialization curve of a Te-based chalcogenide austenitic threshold switch device with SiO2 as the dielectric layer and a thickness of 3nm. In this embodiment, the initialization voltage of the device with the dielectric layer is 4.25V, which is significantly higher than the initialization voltage of 2.36V without the dielectric layer.

[0042] When the dielectric layer does not meet the conditions defined in this invention, the device performance cannot be improved.

[0043] like Figure 6 The figure shows the IV curve when the thickness of the Al2O3 dielectric layer exceeds 5nm in one embodiment. When Al2O3 is used as the dielectric layer, the IV curve does not have a switching threshold when the thickness exceeds 5nm, and the device loses its switching characteristics.

[0044] like Figure 7 The figure shows the IV curve when the SiO2 dielectric layer thickness exceeds 5nm in one embodiment. With SiO2 as the dielectric layer, when the thickness exceeds 5nm, the IV curve does not have a switching threshold, and the device loses its switching characteristics.

[0045] like Figure 8 The figure shows the IV curve when a TiO2 dielectric layer is selected in one embodiment and the thickness does not exceed 5nm. When TiO2 is used as the dielectric layer, even if the thickness does not exceed 5nm, the IV curve does not have a switching threshold and the device loses its switching characteristics.

[0046] Accordingly, the present invention also relates to a non-volatile memory array comprising arrayed non-volatile memory cells, wherein the non-volatile memory cells include the Te-based chalcogenide austenitic threshold switching device described above.

[0047] like Figure 9 The image shows an example of the electrical characteristics of a non-volatile memory cell. Figure 9 The right side of the zero mark on the horizontal axis is the positive direction. To obtain the positive high threshold state 310, a negative electrical operation is applied to the non-volatile memory cell to turn it on. That is, the corresponding negative electrical operation is the write logic "0" operation of the non-volatile memory cell. The threshold voltage corresponding to the positive high threshold state 310 is V "0". To obtain the positive low threshold state 320, a positive electrical operation is applied to the non-volatile memory cell to turn it on. That is, the corresponding positive electrical operation is the write logic "1" operation of the non-volatile memory cell. The threshold voltage corresponding to the positive low threshold state 320 is V "1". The threshold increment of the non-volatile memory cell is the difference between V "0" and V "1".

[0048] This invention studies the gating characteristics of Te-based chalcogenide material layers. A specific dielectric layer is superimposed on the Te-based chalcogenide material layer to serve as the functional layer. Taking into account breakdown risk, leakage current suppression effect, and turn-on difficulty, the dielectric layer is specified as a compound XY, where X is one or more elements selected from Al, Zr, Ta, Zn, Si, and B, and Y is one or more elements selected from O, N, and S. The thickness of the dielectric layer does not exceed 5 nm. Experiments have shown that using the above materials to fabricate a dielectric layer of no more than 5 nm can ensure that the device is not broken down while effectively suppressing leakage current and increasing the threshold voltage.

[0049] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A non-volatile memory array, comprising non-volatile memory cells arranged in an array, characterized in that, The non-volatile memory cell is a Te-based chalcogenide austenitic threshold switch device. The Te-based chalcogenide austenitic threshold switch device includes a top electrode and a bottom electrode, and a functional layer with threshold switching function located between the top electrode and the bottom electrode. The functional layer includes a Te-based chalcogenide material layer and a dielectric layer. The dielectric layer is a compound XY, where X is one or more elements selected from Al, Zr, Ta, Zn, Si, and B, and Y is one or more elements selected from O and N. The total thickness of the dielectric layer does not exceed 5 nm. When its total thickness exceeds 5 nm, the IV curve of the Te-based chalcogenide austenitic threshold switch device does not have a switching threshold. The non-volatile memory array applies a negative electrical operation to the non-volatile memory cell to turn it on and present it as a positive high threshold state, which is the write logic "0" operation of the non-volatile memory cell; it applies a positive electrical operation to the non-volatile memory cell to turn it on and present it as a positive low threshold state, which is the write logic "1" operation of the non-volatile memory cell. The difference between the positive high threshold state and the positive low threshold state is the threshold increment of the corresponding non-volatile memory cell.

2. The non-volatile memory array as described in claim 1, characterized in that, The Te-based chalcogenide material layer is A. a Te, where A is one or more elements selected from B, C, Al, Si, P, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, As, In, Sn, and Sb, and the value of a is 0.1 to 1.

3. The non-volatile memory array as described in claim 1, characterized in that, The total thickness d1 of the Te-based chalcogenide material layer ranges from 5 nm to 100 nm.

4. The non-volatile memory array as described in claim 1, characterized in that, The total thickness d1 of the Te-based chalcogenide material layer ranges from 10 nm to 40 nm, and the total thickness d2 of the dielectric layer ranges from 0.5 nm to 5 nm.

5. The non-volatile memory array as described in claim 1, characterized in that, The dielectric layer is Al2O3 or SiO2.

6. The non-volatile memory array as described in claim 1, characterized in that, The functional layer includes a Te-based chalcogenide material layer and a dielectric layer.

7. The non-volatile memory array as described in claim 1, characterized in that, The functional layer includes a Te-based chalcogenide material layer and two dielectric layers, wherein the Te-based chalcogenide material layer is sandwiched between the two dielectric layers, and the total thickness of the two dielectric layers does not exceed 5 nm.

8. The non-volatile memory array as described in claim 1, characterized in that, The materials of the top electrode and the bottom electrode include one or more of W, Pt, Au, Ti, Al, Ag, Cu, or Ni.

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