Heterojunction electronic memristor, preparation method and resistance change performance acquisition method

Abstract

The present invention discloses a heterojunction electronic memristor, a preparation method and a method for obtaining resistive switching performance, belonging to the field of micro-nano electronic devices. It includes a first electrode, a doped Si layer, a charge trapping layer and a second electrode stacked in sequence from bottom to top; the charge trapping layer and the doped Si layer form a heterojunction resistive switching region; the material of the charge trapping layer is AgO x , 0.4 < x < 1.2. The present invention is based on the charge trapping and release of the AgO x layer for resistive switching, with a clear and stable mechanism. Compared with memristive devices based on ion migration, it has better consistency and yield, which is beneficial to large-scale integration. The device uses the defects naturally formed in the charge trapping layer AgO x during the preparation process as traps for charge trapping, and affects the position of the Fermi level by trapping and releasing charges, thereby exhibiting multi-value resistive switching performance. The device has excellent analog resistive switching characteristics, showing good linearity and symmetry during pulse enhancement and suppression, and is suitable for neuromorphic computing.

Description

Technical Field

[0001] This invention belongs to the field of micro and nano electronic devices, and more specifically, relates to a heterojunction electronic memristor, its fabrication, and a method for obtaining resistive switching performance. Background Technology

[0002] In recent years, the application of artificial intelligence in daily life has become increasingly profound. Besides improvements in algorithms themselves, the most important factor is the enhancement of computing power. Among these improvements, graphics processing units (GPUs), due to their superior parallel computing capabilities, have become the primary platform for running neural networks. However, with the emergence of larger network models and smaller edge computing demands, GPUs, facing the challenge of Moore's Law failing, are finding it difficult to achieve significant performance improvements. New computing architectures and corresponding computing devices are urgently needed to address this issue.

[0003] Building upon this foundation, in-memory computing architectures have garnered significant attention due to their improved integration, faster computation efficiency, and reduced power consumption. Memristors, with their in-memory computing capabilities, have also been extensively studied. The most prominent device among these is the ion-mist memristor, based on ion migration. However, constrained by the uncontrollable nature of ion migration, the consistency of such devices is often poor. To control the ion migration process and reduce its randomness, complex process and structural designs are often required to ensure reliable operation, which further increases the difficulty and cost of large-scale integration. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a heterojunction electronic memristor, its preparation and resistive switching performance acquisition method, aiming to solve the problem of poor consistency of ionic memristors.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a heterojunction electronic memristor, comprising a first electrode, a doped Si layer, a charge trapping layer, and a second electrode stacked sequentially from bottom to top;

[0006] The charge trapping layer and the doped Si layer are combined to form a heterojunction resistive switching region;

[0007] The charge trapping layer is made of AgO. x 0.4 <x<1.2。

[0008] Preferably, the dopant impurities in the doped Si layer are a combination of one or more materials that reduce the resistivity of Si.

[0009] It should be noted that doping with impurities reduces the resistivity of Si in order to reduce the voltage and current limitations of the doped Si layer, thereby increasing the resistive switching window of the device.

[0010] Preferably, the resistivity of the doped Si layer is less than 10 ohm-cm.

[0011] It should be noted that the resistivity is below 10 ohm-cm because the resistivity of Ag₂O at standard stoichiometry is around this value. When the resistivity is below this value, the resistivity switching window of the device increases accordingly.

[0012] Preferably, the first electrode forms an ohmic contact with the doped Si layer, and the second electrode forms an ohmic contact with the charge trapping layer.

[0013] It should be noted that the first and second electrodes are in contact with the doped Si layer and AgO. x All contacts are ohmic contacts, the purpose of which is to eliminate the interface resistance and capacitance effects caused by non-ohmic contacts (such as Schottky contacts) in order to improve the resistive switching performance of the device.

[0014] Preferably, the thickness of the first electrode is 3nm-200nm, the thickness of the doped Si layer is 3nm-500um, the thickness of the charge trapping layer is 3nm-200nm, and the thickness of the second electrode is 3nm-200nm.

[0015] To achieve the above objectives, in a second aspect, the present invention provides a method for fabricating a heterojunction electronic memristor as described in the first aspect, comprising:

[0016] (1) Prepare a doped Si layer by using melt doping in the Czochralski method or zone melting method of single crystal Si growth; or grow an intrinsic Si layer by one of the Czochralski method or zone melting method, and then prepare a doped Si layer by thermal diffusion doping or ion implantation, and use it as a substrate for the next process.

[0017] (2) A first electrode is fabricated on the back side of the doped Si layer;

[0018] (3) A charge trapping layer is prepared on the doped Si layer;

[0019] (4) A second electrode patterned mask layer is fabricated on the charge trapping layer;

[0020] (5) A second electrode is prepared on the mask layer, and the mask layer is removed to obtain the device.

[0021] To achieve the above objectives, in a third aspect, the present invention provides a method for fabricating a heterojunction electronic memristor as described in the first aspect, comprising:

[0022] (1) Take an arbitrary smooth substrate and prepare a first electrode on the surface of the substrate;

[0023] (2) An intrinsic Si layer is grown on the first electrode by sputtering, physical vapor deposition or chemical vapor deposition, and then a doped Si layer is prepared by thermal diffusion doping or ion implantation.

[0024] (3) Prepare a charge trapping layer on the doped Si layer;

[0025] (4) Prepare a second electrode patterning mask layer on the charge trapping layer;

[0026] (5) Prepare a second electrode on the mask layer and remove the mask layer to obtain the device.

[0027] To achieve the above object, in a fourth aspect, the present invention provides a method for obtaining the resistive switching performance of a heterojunction electron-type memristor as described in the first aspect, including:

[0028] Apply a negative voltage in the AgO x direction to the heterojunction memristor:

[0029] If the injected carrier concentration is lower than the hot carrier concentration, the charge conduction in the device follows Ohm's law, and the conductance value of the heterojunction memristor remains unchanged;

[0030] If the injected carrier concentration exceeds the hot carrier concentration but is lower than the trapped hole concentration, the current conduction follows the Mark-Helfrich's space charge limited current law, and the electron emission follows the Poole-Frenkel emission mechanism. As the negative voltage increases, the Fermi level moves down, the positively charged space charge decreases, and the conductance value of the heterojunction memristor increases;

[0031] Apply a positive voltage in the AgO x direction to the heterojunction memristor:

[0032] If the injected carrier concentration is lower than the hot carrier concentration, the charge conduction in the device follows Ohm's law, and the conductance value of the heterojunction memristor remains unchanged;

[0033] If the injected carrier concentration exceeds the hot carrier concentration but is lower than the trapped hole concentration, the current conduction follows the Mark-Helfrich's space charge limited current law, and the electron emission follows the Poole-Frenkel emission mechanism. As the positive voltage increases, the Fermi level moves up, the positively charged space charge increases, and the conductance value of the heterojunction memristor decreases.

[0034] Generally speaking, compared with the prior art through the above technical solutions conceived by the present invention, the following beneficial effects are obtained:

[0035] (1) The present invention provides a heterojunction electron-type memristor, including a first electrode, a doped Si layer, a charge trapping layer, and a second electrode stacked in sequence from bottom to top; the charge trapping layer and the doped Si layer form a heterojunction resistive switching region in combination; the material of the charge trapping layer is AgO x , 0.4 < x < 1.2. The present invention is based on AgO xThe charge trapping and release of the layer is used for resistive switching, and the mechanism is clear and stable. Compared with memristor devices based on ion migration (such as junction devices based on CuAlO2 / ZnO), it has better consistency and yield, which is conducive to large-scale integration.

[0036] (2) This invention provides a method for obtaining the resistive switching performance of the above-mentioned heterojunction electronic memristor, utilizing the charge trapping layer AgO x The naturally occurring defects (mainly Ag vacancies) formed during the fabrication process act as charge traps, influencing the Fermi level position through charge trapping and release, thus exhibiting multi-valued resistive switching performance. The device possesses excellent analog resistive switching characteristics, demonstrating good linearity and symmetry during pulse enhancement and suppression, making it suitable for neuromorphic computing. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of a heterojunction electronic memristor film provided in an embodiment of the present invention.

[0038] Figure 2 The Pt / p provided in Embodiment 1 of this invention + -Si / AgO x / Pt junction memristor device multi-value resistive switching principle and band structure schematic diagram.

[0039] Figure 3 The Pt / p provided in Embodiment 1 of this invention + -Si / AgO x Linear IV curve of / Pt memristor device under cyclic voltage scan.

[0040] Figure 4 The Pt / p provided in Embodiment 1 of this invention + -Si / AgO x Linear IV curve of / Pt memristor device under continuous voltage sweep.

[0041] Figure 5 The Pt / n provided in Embodiment 2 of this invention + -Si / AgO x Linear IV curve of / Pt memristor device under continuous voltage sweep.

[0042] Figure 6 The Pt / n provided in Embodiment 2 of this invention + -Si / AgO x Box plot of conductance versus number of pulses for a Pt memristor device under 5000 consecutive pulse excitations (50 cycles).

[0043] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0044] 1-First electrode, 2-Doped Si layer, 3-Charge trapping layer, 4-Second electrode. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0046] like Figure 1 As shown, this invention provides a heterojunction electronic memristor, comprising a first electrode 1, a doped Si layer 2, a charge trapping layer 3, and a second electrode 4 stacked sequentially from bottom to top; the charge trapping layer and the doped Si layer combine to form a heterojunction resistive switching region; the material of the charge trapping layer is AgO. x 0.4 <x<1.2。

[0047] Preferably, the dopant impurities in the Si-doped layer are a combination of one or more materials that reduce the resistivity of Si. For example, one or more of B, Al, Ga, In, Li, P, As, Sb, Te, and Ti, which form N-type or P-type conductivity, constituting a PN junction or PP junction with the charge trapping layer. The inversion (PN) heterojunction memristor has adjustable self-rectification performance, which allows the device to eliminate crosstalk without a selector in cross-array integration, facilitating large-scale integration.

[0048] Preferably, the resistivity of the doped Si layer is less than 10 ohm-cm.

[0049] Preferably, 0.4 <x≤0.5。

[0050] Preferably, 0.5 <x<1.0。

[0051] Preferably, 1.0 ≤ x < 1.2.

[0052] Preferably, the first electrode forms an ohmic contact with the doped Si layer, and the second electrode forms an ohmic contact with the charge trapping layer. The first electrode is one of Al, Ti, TiN, W, Pt, Ag, and Cu. The second electrode is one of Pt, Au, Pd, Te, W, Cu, Ag, and Al.

[0053] Preferably, the thickness of the first electrode is 3nm-200nm, the thickness of the doped Si layer is 3nm-500um, the thickness of the charge trapping layer is 3nm-200nm, and the thickness of the second electrode is 3nm-200nm.

[0054] This invention provides a method for fabricating the above-mentioned heterojunction electronic memristor, comprising:

[0055] (1) Prepare a doped Si layer by using melt doping in the Czochralski method or zone melting method of single crystal Si growth; or grow an intrinsic Si layer by one of the Czochralski method or zone melting method, and then prepare a doped Si layer by thermal diffusion doping or ion implantation, and use it as a substrate for the next process.

[0056] (2) A first electrode is fabricated on the back side of the doped Si layer;

[0057] (3) A charge trapping layer is prepared on the doped Si layer;

[0058] (4) A second electrode patterned mask layer is fabricated on the charge trapping layer;

[0059] (5) A second electrode is fabricated on the mask layer, and the mask layer is removed to obtain the device;

[0060] or,

[0061] (1) Take an arbitrary smooth substrate and prepare a first electrode on the surface of the substrate;

[0062] (2) An intrinsic Si layer is grown on the first electrode by sputtering, physical vapor deposition or chemical vapor deposition, and then a doped Si layer is prepared by thermal diffusion doping or ion implantation.

[0063] (3) A charge trapping layer is prepared on the doped Si layer;

[0064] (4) A second electrode patterned mask layer is fabricated on the charge trapping layer;

[0065] (5) A second electrode is prepared on the mask layer, and the mask layer is removed to obtain the device.

[0066] The fabrication process of the second electrode, the charge trapping layer, and the first electrode is one of sputtering, physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, pulsed laser deposition, or electrochemical methods.

[0067] This invention provides a method for obtaining the resistive switching performance of the above-mentioned heterojunction electronic memristor, comprising:

[0068] Apply AgO to the heterojunction memristor x When the voltage is negative in the direction:

[0069] If the injected carrier concentration is lower than the hot carrier concentration, the charge conduction in the device follows Ohm's law, and the conductivity of the heterojunction memristor remains unchanged.

[0070] If the injected carrier concentration exceeds the hot carrier concentration but is lower than the trapped hole concentration, the current conduction follows the Mark-Helfridge space charge-limited current law, and the electron emission follows the Poul-Frenkel emission mechanism. As the negative voltage increases, the Fermi level shifts downward, the positively charged space charge decreases, and the conductivity of the heterojunction memristor increases.

[0071] Apply AgO to the heterojunction memristor x When the voltage is forward in the direction:

[0072] If the injected carrier concentration is lower than the hot carrier concentration, the charge conduction in the device follows Ohm's law, and the conductivity of the heterojunction memristor remains unchanged.

[0073] If the injected carrier concentration exceeds the hot carrier concentration but is lower than the trapped hole concentration, the current conduction follows the Mark-Helfridge space charge-limited current law, and the electron emission follows the Poul-Frenkel emission mechanism. As the positive voltage increases, the Fermi level shifts upward, the positively charged space charge increases, and the conductivity of the heterojunction memristor decreases.

[0074] Example 1

[0075] This embodiment demonstrates a four-layer planar memristor unit, and the specific fabrication process is as follows:

[0076] (1) A silicon wafer with a resistivity of 0.005 ohm-cm was obtained by degenerate doping of the melt with B element during the single crystal Czochralski growth process, which is a doped Si layer. The wafer was selected with a crystal phase of

[100] and a thickness of 500 μm. The Si layer was obtained by degenerate doping of the melt with B element during the single crystal Czochralski growth process. The wafer was cut into 1×1 cm samples, soaked in acetone, and cleaned in an ultrasonic environment for 10-15 minutes. Then it was soaked in anhydrous ethanol and cleaned in an ultrasonic environment for 5 minutes. The ultrasonic power was 40W. Finally, it was cleaned with deionized water and dried with a nitrogen gun.

[0077] (2) Take a clean sample and grow a first electrode Pt layer of about 100 nm on its back side using magnetron sputtering. The sputtering power is 200 W, the Ar atmosphere is 0.5 Pa, and the sputtering time is 1000 s.

[0078] (3) Preparation of AgO by magnetron sputtering x The target material is an Ag target, and sputtering is performed using AC. The thickness of the charge-trapping layer is controlled by adjusting the sputtering time during the sputtering process, thus obtaining the AgO charge-trapping layer. x This refers to the charge trapping layer. In this embodiment, AgO is grown using an O2:Ar ratio of 24:40. x Regarding film thickness, AgO x The thickness of the layer is 30nm.

[0079] (4) A square photolithographic pattern is prepared on the charge trapping layer by photolithography. The size of the second electrode is 100μm×100μm. The steps of the photolithography process are: spin coating, pre-baking, pre-exposure, post-baking, post-exposure, and development.

[0080] (5) A 100 nm Pt layer is grown on the sample after step (4) by magnetron sputtering with a sputtering power of 200 W, an Ar atmosphere of 0.5 Pa, and sputtering for 1000 s to obtain the second electrode.

[0081] (6) The thin film sample prepared in step (5) is soaked in acetone for 30-50 minutes, then washed with anhydrous ethanol and deionized water, and dried with nitrogen.

[0082] After completing the above steps, Pt / p is prepared. + -Si / AgO x / Pt memristor unit.

[0083] like Figure 2 As shown, this invention utilizes AgO in a heterojunction x The layer traps and releases charges to change the resistance of the device, achieving multi-value resistive switching performance. The specific resistive switching principle is as follows:

[0084] (a) Under small voltage bias (p + -Si is positive bias), the injected carrier concentration is lower than the hot carrier concentration, and the charge conduction in the device follows Ohm's law.

[0085] (b) As the applied voltage increases, the injected carrier concentration exceeds the hot carrier concentration but is lower than the trapped hole concentration. At this point, holes enter AgO through Poole-Frank emission. x Traps within the layer, current conduction follows Mark Helfridge's space charge-limited current law; holes in AgO x Trapping within the layer lowers the Fermi level, thereby increasing the device's conductivity.

[0086] (c) When a reverse voltage is applied (p + -Si is a negative bias voltage), AgO x Holes trapped in the layer will be released from the trap by entering the trap through the Poul-Frank electron emission. Current conduction follows the space charge-limited current law of Mark Helfridge, thereby raising the Fermi level and thus lowering the conductivity state.

[0087] When x is 0.5, the composition is Ag₂O, with Ag ions in a +1 valence state. When x is 1.0, the composition is AgO, with Ag ions in a mixed valence state of +1 and +3. In both cases, AgO… xThe material has better stability, and the heterojunction electronic memristor is more robust.

[0088] Example 2

[0089] The only difference between the heterojunction memristor in this embodiment and the heterojunction memristor in Embodiment 1 is that the doping type of the Si layer is N-type and the doped impurity is P; everything else remains the same.

[0090] In this embodiment, the specific fabrication process of the heterojunction memristor is as follows:

[0091] (1) Select crystal orientation

[100] and thickness of 500 μm. During the single crystal Czochralski growth process, degenerate doping of P element is performed on the melt to obtain a silicon wafer with resistivity of 0.005 ohm-cm, which is a doped Si layer. Cut it into 1×1 cm samples, soak them in acetone, clean them in an ultrasonic environment for 10-15 minutes, then soak them in anhydrous ethanol and clean them in an ultrasonic environment for 5 minutes. The ultrasonic power is 40W. Finally, clean them with deionized water and dry them with a nitrogen gun.

[0092] (2) Take a clean sample and grow a first electrode Pt layer of about 100 nm on its back side using magnetron sputtering. The sputtering power is 200 W, the Ar atmosphere is 0.5 Pa, and the sputtering time is 1000 s.

[0093] (3) Preparation of AgO by magnetron sputtering x The target material is an Ag target, and sputtering is performed using AC. The thickness of the charge-trapping layer is controlled by adjusting the sputtering time during the sputtering process, thus obtaining the AgO charge-trapping layer. x This refers to the charge trapping layer. In this embodiment, AgO is grown using an O2:Ar ratio of 24:40. x Regarding film thickness, AgO x The thickness of the layer is 30nm.

[0094] (4) A square photolithographic pattern is prepared on the charge trapping layer by photolithography. The size of the second electrode is 100μm×100μm. The steps of the photolithography process are: spin coating, pre-baking, pre-exposure, post-baking, post-exposure, and development.

[0095] (5) A 100 nm Pt layer is grown on the sample after step (4) by magnetron sputtering with a sputtering power of 200 W, an Ar atmosphere of 0.5 Pa, and sputtering for 1000 s to obtain the second electrode.

[0096] (6) The thin film sample prepared in step (5) is soaked in acetone for 30-50 minutes, then washed with anhydrous ethanol and deionized water, and dried with nitrogen.

[0097] After completing the above steps, Pt / n was prepared. + -Si / AgO x / Pt memristor unit.

[0098] Electrical property testing

[0099] In all embodiments of the present invention, an Agilent B1500A semiconductor device analyzer was used to perform DC I / V scanning and pulse switching characteristic tests on the memristor unit.

[0100] Figure 3 This is the Pt / p prepared in Example 1 of the present invention. + -Si / AgO x The linear IV curve of a Pt memristor device under cyclic voltage scanning is shown, where negative voltage scanning (0V to -1V) and positive voltage scanning (0V to 1V) are performed on the device, constituting one cycle, for a total of 50 cycles. Figure 3 It can be seen that the devices exhibit good consistency.

[0101] Figure 4 This is the Pt / p prepared in Example 1 of the present invention. + -Si / AgO x The linear IV curve of a Pt memristor device under continuous voltage scanning is shown, where the device cell is subjected to multiple consecutive negative DC voltage scans and multiple consecutive positive scans. The negative voltage scan range is controlled between -1V and 0V, and the positive voltage scan range is controlled between 0V and 1V. Figure 4 It can be seen that during continuous unidirectional scanning, the device hysteresis curve changes steadily in one direction, exhibiting multi-value resistive switching performance, which is consistent with the characteristics of analog memristor devices.

[0102] Figure 5 This is the Pt / n prepared in Example 2 of the present invention. + -Si / AgO x The linear I / V curve of a Pt memristor device under continuous voltage scanning is shown, in which multiple consecutive negative DC I / V voltage scans and multiple consecutive positive scans are performed on the device unit. The negative voltage scan range is controlled between -1V and 0V, and the positive voltage scan range is controlled between 0V and 1V. Figure 5 It can be seen that during continuous unidirectional scanning, the device hysteresis curve steadily changes in one direction, exhibiting multi-value resistive switching performance, which is consistent with the characteristics of analog memristor devices. Furthermore, the figure shows a certain rectification ratio between the forward and negative scans; therefore, in large-scale integration based on cross-arrays, no gating device is needed, which can greatly improve integration density.

[0103] Figure 6 This is the Pt / n prepared in Example 2 of the present invention.+ -Si / AgO x Box plot of the conductance versus pulse count of a / Pt memristor device under 5000 consecutive pulse excitations (50 cycles), where the enhancement pulse amplitude is -0.8V and the pulse width is 40ms; the suppression pulse amplitude is 0.8V and the pulse width is 40ms; and the readout pulse amplitude is 0.4V and the pulse width is 10ms. Each cycle consists of 50 enhancement pulses and 50 suppression pulses, for a total of 50 cycles. Figure 6 It can be seen that in each cycle, the device conductance can steadily increase and decrease under pulse excitation, exhibiting long-term enhancement and long-term suppression characteristics consistent with the simulated synapse. Furthermore, it shows good inter-device consistency over 50 cycles, with an average coefficient of variation of 4.16% (standard deviation divided by mean). The lower this value, the better the overall consistency. Compared with ionic memristors, this coefficient of variation is excellent.

[0104] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A heterojunction electronic memristor, characterized in that, It includes a first electrode, a doped Si layer, a charge trapping layer, and a second electrode, which are stacked sequentially from bottom to top. The charge trapping layer and the doped Si layer are combined to form a heterojunction resistive switching region; The material of the charge trapping layer is AgO x 0.4 < x < 1.

2.

2. The heterojunction electronic memristor of claim 1, wherein, The doping impurities in the doped Si layer are a combination of one or more materials that reduce the resistivity of Si.

3. The heterojunction electronic memristor of claim 2, wherein, The resistivity of the doped Si layer is less than 10 ohm-cm.

4. The heterojunction electronic memristor of any one of claims 1 to 3, wherein, The first electrode forms an ohmic contact with the doped Si layer, and the second electrode forms an ohmic contact with the charge trapping layer.

5. The heterojunction electronic memristor of any one of claims 1 to 3, wherein, The thickness of the first electrode is 3nm-200nm, the thickness of the doped Si layer is 3nm-500μm, the thickness of the charge trapping layer is 3nm-200nm, and the thickness of the second electrode is 3nm-200nm.

6. The method of claim 1 to 5, wherein the method comprises: include: (1) Prepare doped Si layers by using melt doping during the Czochralski or zone melting method of single-crystal Si growth; Alternatively, an intrinsic Si layer can be grown using either the Czochralski method or the zone melting method, and then a doped Si layer can be prepared by thermal diffusion doping or ion implantation, which can then be used as a substrate for the next process. (2) A first electrode is fabricated on the back side of the doped Si layer; (3) A charge trapping layer is prepared on the doped Si layer; (4) A second electrode patterned mask layer is fabricated on the charge trapping layer; (5) A second electrode is prepared on the mask layer, and the mask layer is removed to obtain the heterojunction electronic memristor.

7. The method of claim 1 to 5, wherein the method comprises: include: (1) Take an arbitrary smooth substrate and prepare a first electrode on the surface of the substrate; (2) An intrinsic Si layer is grown on the first electrode by sputtering, physical vapor deposition or chemical vapor deposition, and then a doped Si layer is prepared by thermal diffusion doping or ion implantation. (3) A charge trapping layer is prepared on the doped Si layer; (4) A second electrode patterned mask layer is fabricated on the charge trapping layer; (5) A second electrode is prepared on the mask layer, and the mask layer is removed to obtain the heterojunction electronic memristor.

8. A method for obtaining the resistive switching properties of a heterojunction electronic memristor according to any one of claims 1 to 5, characterized in that, include: Applying AgO to the heterojunction electronic memristor x a negative voltage in the direction of: If the injected carrier concentration is lower than the hot carrier concentration, the charge conduction in the device follows Ohm's law, and the conductivity of the heterojunction electronic memristor remains unchanged. If the injected carrier concentration exceeds the hot carrier concentration but is lower than the trapped hole concentration, the current conduction follows the Mark-Helfridge space charge-limited current law, and the electron emission follows the Poul-Frenkel emission mechanism. As the negative voltage increases, the Fermi level shifts downward, the positively charged space charge decreases, and the conductivity of the heterojunction electronic memristor increases. Applying AgO to the heterojunction electronic memristor x The positive voltage of the direction is: If the injected carrier concentration is lower than the hot carrier concentration, the charge conduction in the device follows Ohm's law, and the conductivity of the heterojunction electronic memristor remains unchanged. If the injected carrier concentration exceeds the hot carrier concentration but is lower than the trapped hole concentration, the current conduction follows the Mark-Helfridge space charge-limited current law, and the electron emission follows the Poul-Frenkel emission mechanism. As the positive voltage increases, the Fermi level shifts upward, the positively charged space charge increases, and the conductivity of the heterojunction electronic memristor decreases.

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