Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: forming a second electrode layer on a first dielectric layer, the second electrode layer covering the first dielectric layer in a first region; forming a second dielectric layer on the second electrode layer and a second region; forming a third electrode layer on the second dielectric layer, the third electrode layer having an overlapping region with the first region and the second region in a projection plane parallel to the substrate; forming a first electrical connection structure in contact with the second electrode layer, and forming a second electrical connection structure in contact with the third electrode layer and a first electrode layer in the second region; or forming a third electrical connection structure in contact with the first electrode layer, and forming a fourth electrical connection structure in contact with the second electrode layer and the third electrode layer. By adjusting the connection relationship between different electrode layers, different equivalent capacitance densities can be obtained, thereby meeting the needs of different types of capacitors.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in materials and design have led to generation after generation of integrated circuits. Each generation features smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of fabricating and manufacturing integrated circuits, requiring similar developments in IC fabrication and manufacturing to achieve these advancements. Throughout the development of integrated circuits, functional density (the number of interconnect devices per chip area) has gradually increased, while geometric dimensions (the smallest components that can be manufactured using specific processes) have gradually decreased.

[0003] One type of capacitor is the metal-insulator-metal (MIM) capacitor, which is commonly used in mixed-signal and logic devices (such as embedded memories and RF devices). MIM capacitors are typically used to store charge in various semiconductor devices. To meet the performance requirements of these devices, the capacitance density of MIM capacitors is also gradually increasing.

[0004] However, the equivalent capacitance density of MIM capacitors still needs to be improved, and the available options for equivalent capacitance density are limited. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which can obtain different equivalent capacitance densities, thereby meeting the needs of different types of capacitors.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a first electrode layer located on the substrate, the first electrode layer including a first region and a second region; a first dielectric layer located on the top and sidewalls of the first electrode layer; a second electrode layer covering the first dielectric layer located in the first region; a second dielectric layer located on the second electrode layer and the second region; a third electrode layer located on the second dielectric layer, wherein on a projection plane parallel to the substrate, the third electrode layer overlaps with both the first region and the second region; and a first electrical connection structure group comprising: a first electrical connection structure in contact with the second electrode layer; a second electrical connection structure located in the second region and in contact with both the third electrode layer and the first electrode layer; or, a second electrical connection structure group comprising: a third electrical connection structure in contact with the first electrode layer; and a fourth electrical connection structure in contact with both the second electrode layer and the third electrode layer.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a first electrode layer on the substrate, the first electrode layer including a first region and a second region; forming a first dielectric layer on the top and sidewalls of the first electrode layer; forming a second electrode layer on the first dielectric layer, the second electrode layer covering the first dielectric layer located in the first region; forming a second dielectric layer on the second electrode layer and the second region; forming a third electrode layer on the second dielectric layer, wherein on a projection plane parallel to the substrate, the third electrode layer overlaps with both the first region and the second region; forming a first electrical connection structure in contact with the second electrode layer, and forming a second electrical connection structure in contact with both the third electrode layer and the first electrode layer in the second region; or, forming a third electrical connection structure in contact with the first electrode layer, and forming a fourth electrical connection structure in contact with both the second electrode layer and the third electrode layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure provided by the embodiments of the present invention, on a projection plane parallel to the substrate, the third electrode layer overlaps with both the first and second regions. That is, the third electrode layer is disposed opposite to both the second and first electrode layers. By providing a first electrical connection structure group, including: a first electrical connection structure in contact with the second electrode layer; and a second electrical connection structure located in the second region and in contact with both the third and first electrode layers, capacitors are formed between the first and second electrode layers, and between the second and third electrode layers, which is beneficial for improving the equivalent capacitance density. Alternatively, by providing a second electrical connection structure group, including: a third electrical connection structure in contact with the first electrode layer; and a fourth electrical connection structure in contact with both the second and third electrode layers, capacitors are formed between the first and second electrode layers, and between the first and third electrode layers. Therefore, the embodiments of the present invention are beneficial for providing options for obtaining different equivalent capacitance densities to meet the needs of different types of capacitors.

[0010] In the semiconductor structure formation method provided by the embodiments of the present invention, a third electrode layer is formed on a second dielectric layer. On a projection plane parallel to the substrate, the third electrode layer overlaps with both the first and second regions. That is, the third electrode layer is disposed opposite to both the second and first electrode layers, thereby forming a first electrical connection structure in contact with the second electrode layer, and a second electrical connection structure in contact with both the third and first electrode layers is formed in the second region. This allows the first and second electrode layers, as well as the second and third electrode layers, to form capacitors, which is beneficial for improving the equivalent capacitance density. Alternatively, a third electrical connection structure in contact with the first electrode layer and a fourth electrical connection structure in contact with both the second and third electrode layers are formed, allowing the first and second electrode layers, and the first and third electrode layers, to form capacitors. Thus, the embodiments of the present invention are beneficial for providing options for obtaining different equivalent capacitance densities to meet the needs of different types of capacitors. Attached Figure Description

[0011] Figures 1 to 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 3 to 4 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;

[0013] Figures 5 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0014] Figures 12 to 14 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation

[0015] As the background technology shows, the equivalent capacitance density of MIM capacitors still needs improvement, and the available options for equivalent capacitance density are limited. Specifically, the structure of a traditional MIM capacitor includes a bottom electrode layer, a dielectric layer, and a top electrode layer stacked sequentially from bottom to top. In this case, the MIM capacitor only has a single dielectric layer, and the bottom and top electrode layers are positioned opposite each other to form a single capacitor, resulting in a relatively low equivalent capacitance density.

[0016] To address the technical problem, embodiments of the present invention provide a semiconductor structure in which, on a projection plane parallel to the substrate, the third electrode layer overlaps with both the first and second regions. That is, the third electrode layer is disposed opposite to both the second and first electrode layers. By providing a first electrical connection structure group, capacitors are formed between the first and second electrode layers, and between the second and third electrode layers, which is beneficial for improving the equivalent capacitance density. Alternatively, a second electrical connection structure group is provided, forming capacitors between the first and second electrode layers, and between the first and third electrode layers. Therefore, embodiments of the present invention provide options for obtaining different equivalent capacitance densities to meet the needs of different types of capacitors.

[0017] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figure 1 and Figure 2 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention. Figure 1 This is a cross-sectional view. Figure 2 for Figure 1 The corresponding top view.

[0018] like Figure 1 and Figure 2 As shown, in this embodiment, the semiconductor structure includes: a substrate 100; a first electrode layer 10 located on the substrate 100, the first electrode layer 10 including a first region 10I and a second region 10II; a first dielectric layer 120 located on the top and sidewalls of the first electrode layer 10; a second electrode layer 20 covering the first dielectric layer 120 located in the first region 10I; a second dielectric layer 130 located on the second electrode layer 20 and the second region 10II; and a third electrode layer 30 located on the second dielectric layer 130, parallel to the substrate. On the projection surface of the bottom 100, the third electrode layer 30 overlaps with both the first region 10I and the second region 10II; the first electrical connection structure group includes: a first electrical connection structure 150, which is in contact with the second electrode layer 20; a second electrical connection structure 160, which is located in the second region 10II and is in contact with both the third electrode layer 30 and the first electrode layer 10; or, the second electrical connection structure group includes: a third electrical connection structure, which is in contact with the first electrode layer; and a fourth electrical connection structure, which is in contact with both the second and third electrode layers.

[0019] In this embodiment, a first connection structure group 210 is provided in a semiconductor structure as an example for illustration.

[0020] The substrate 100 provides a process platform for the subsequent formation of MIM capacitors. In this embodiment, the substrate 100 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0021] In this embodiment, the MIM capacitor is formed in the back-end process. Therefore, an inter-metal dielectric (IMD) layer (not shown) is also formed on the substrate 100. Depending on the process, one or more stacked metal layers are formed in the inter-metal dielectric layer along the normal direction of the substrate surface, such as a first metal (M1) layer, a second metal (M2) layer, etc. When there are multiple metal layers, adjacent metal layers are electrically connected through a via interconnect structure located between them.

[0022] In this embodiment, the semiconductor structure further includes an etch stop layer 110, located between the substrate 100 and the first electrode layer 10, and between the substrate 100 and the first dielectric layer 120.

[0023] The etching stop layer 110 is used to define the position of etching stop during the formation of the first electrode layer 10, the first electrical connection structure group 210 or the second electrical connection structure group, so as to reduce the probability of damage to the substrate 100 and also help to improve the bottom height consistency of the first electrical connection structure group 210 and the bottom height consistency of the second electrical connection structure group.

[0024] As an example, the etch stop layer 110 is made of silicon nitride. In other embodiments, the etch stop layer may also be made of other materials that have high etch selectivity with the substrate material, such as one or more of silicon nitride, aluminum oxide, aluminum nitride, and NDC (nitride-doped carbon).

[0025] The first electrode layer 10 is used as the electrode plate of the MIM capacitor. Specifically, the first electrode layer 10 is located on the etch stop layer 110.

[0026] The material of the first electrode layer 10 is a conductive material. As an example, the material of the first electrode layer 10 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0027] The first dielectric layer 120 serves as an insulating layer in the formation of the MIM capacitor, used to isolate the first electrode layer 10 and the subsequent second electrode layer. Specifically, the first dielectric layer 120 conformally covers the first electrode layer 10 and the substrate 100.

[0028] In this embodiment, the first dielectric layer 120 is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor, and correspondingly increase the capacitance density.

[0029] Specifically, the first dielectric layer 120 is a high-k dielectric layer formed by stacking, that is, the first dielectric layer 120 is a high-k composite dielectric layer. Once the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the first dielectric layer 120 can meet the process requirements while maintaining good formation quality. For this purpose, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0030] In this embodiment, the first dielectric layer 120 is a ZAZ layer. The ZAZ layer comprises a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, depending on process requirements, the material of the first dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0031] The second electrode layer 20 is used as the electrode plate of the MIM capacitor.

[0032] The second electrode layer 20 covers the first dielectric layer 120 located in the first region 10I, so that the second electrode layer 20 is disposed opposite to the first region 10I, and thus the second electrode layer 20 can form a MIM capacitor with the first electrode layer 10 in the first region 10I.

[0033] In this embodiment, the second electrode layer 20 exposes the second region 10II so that the third electrode layer 30 can cover the second region 10II, thereby facilitating the second electrical connection structure 160 to penetrate the third electrode layer of the second region 10II, and the second electrical connection structure 160 can contact the first electrode layer 10, thereby realizing the electrical connection between the first electrode layer 10 and the third electrode layer 30.

[0034] It should be noted that, in this embodiment, the second electrode layer 20 includes a connection region 20I for electrical connection. In this embodiment, the connection region 20I is located on the side of the first electrode layer 10. The connection region 20I is used to form an electrical connection structure that electrically connects the second electrode layer 20.

[0035] The material of the second electrode layer 20 is a conductive material. As an example, the material of the second electrode layer 20 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0036] The second dielectric layer 130 serves as an insulating layer for the MIM capacitor, isolating the second electrode layer 20 from the third electrode layer 30. In this embodiment, the second dielectric layer 130 conformally covers the second electrode layer 20 and the second region 10II.

[0037] In this embodiment, the material of the second dielectric layer 130 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor, and correspondingly increase the capacitance density.

[0038] Specifically, the second dielectric layer 130 is a high-k dielectric layer formed by stacking, that is, the second dielectric layer 130 is a high-k composite dielectric layer. Once the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the second dielectric layer 130 can meet the process requirements while maintaining good formation quality. For this purpose, the high-k dielectric material includes any one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0039] The material of the second dielectric layer 130 can be the same as or different from the material of the first dielectric layer 120.

[0040] In this embodiment, the second dielectric layer 130 is a ZAZ layer. The ZAZ layer comprises a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, depending on process requirements, the material of the second dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0041] The third electrode layer 30 is used as an electrode plate in the MIM capacitor.

[0042] On a projection plane parallel to the substrate 100, the third electrode layer 30 overlaps with both the first region 10I and the second region 10II. That is, the third electrode layer 30 is disposed opposite to the second electrode layer 20 and the first electrode layer 10, thereby establishing a first electrical connection structure group 210, comprising: a first electrical connection structure 150 in contact with the second electrode layer 20; and a second electrical connection structure 160 located in the second region 10II and in contact with both the third electrode layer 30 and the first electrode layer 10. This allows the first electrode layer 10 and the second electrode layer 20, as well as the second electrode layer 20 and the third electrode layer 30, to form capacitors, which is beneficial for improving the equivalent capacitance density. Alternatively, by establishing a second electrical connection structure group, comprising: a third electrical connection structure in contact with the first electrode layer; and a fourth electrical connection structure in contact with both the second and third electrode layers, the first electrode layer 10 and the second electrode layer 20, and the first electrode layer 10 and the third electrode layer 30, can form capacitors, thereby obtaining different equivalent capacitance densities and meeting the needs of different types of capacitors.

[0043] In this embodiment, the example is taken as a semiconductor structure in which a first connection structure group 210 is provided, such that a capacitor is formed between the first electrode layer 10 and the second electrode layer 20, and between the second electrode layer 20 and the third electrode layer 30. This is beneficial to improving the equivalent capacitance density.

[0044] Correspondingly, the third electrode layer 30 and the second region 10II have an overlapping area so that a second electrical connection structure 160 is formed on the second region 10II, penetrating the third electrode layer 30 and contacting the first electrode layer 10, so as to realize the electrical connection between the third electrode layer 30 and the first electrode layer 10.

[0045] It should be noted that the third electrode layer 30 exposes the connection region 20I so that a first electrical connection structure 150 in contact with the second electrode layer 20 can be formed on the connection region 20I, thereby realizing the electrical connection between the second electrode layer 20 and the external circuit.

[0046] The material of the third electrode layer 30 is a conductive material. As an example, the material of the third electrode layer 30 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0047] The first electrical connection structure group 210 is used to realize the electrical connection between the MIM capacitor and the external circuit.

[0048] In this embodiment, capacitors are formed between the first electrode layer 10 and the second electrode layer 20, and between the second electrode layer 20 and the third electrode layer 30. The first electrode layer 10 and the third electrode layer 30 are connected to the same potential through the second electrical connection structure 160, thereby connecting the two capacitors in parallel, which increases the capacitance value per unit area, i.e., increases the equivalent capacitance density.

[0049] The first electrical connection structure 150 is used to realize the electrical connection between the second electrode layer 20 and the external circuit. Specifically, in this embodiment, the first electrical connection structure 150 is located on the connection area 20I and is in contact with the second electrode layer 20.

[0050] In this embodiment, the second electrode layer 20 of the connection region 20I covers the first dielectric layer 120 located on the substrate 100; the first electrical connection structure 150 penetrates the second electrode layer 20 of the connection region 20I, and the bottom of the first electrical connection structure 150 contacts the top surface of the etch stop layer 110, so that the bottom of the first electrical connection structure 150 can stop on the etch stop layer 110, which is beneficial to improve the bottom height consistency of the first electrical connection structure 150.

[0051] The material of the first electrical connection structure 150 is a conductive material. In this embodiment, the material of the first electrical connection structure 150 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0052] The second electrical connection structure 160 is used to electrically connect the first electrode layer 10 and the third electrode layer 30, and also to realize the electrical connection between the first electrode layer 10 and the third electrode layer 30 and the external circuit, so that when the capacitor is working, the first electrode layer 10 and the third electrode layer 30 can be connected to the same potential.

[0053] Specifically, in this embodiment, the second electrical connection structure 160 penetrates the first dielectric layer 120, the second dielectric layer 130 and the third electrode layer 30 located in the second region 10II and is in contact with the first electrode layer 10. The second electrical connection structure 160 electrically connects the first electrode layer 10 and the third electrode layer 30.

[0054] In this embodiment, the second electrical connection structure 160 penetrates the first electrode layer 10, and the bottom of the second electrical connection structure 160 is in contact with the top surface of the etch stop layer 110, thereby improving the height uniformity of the bottom of the second electrical connection structure 160.

[0055] The material of the second electrical connection structure 160 is a conductive material. In this embodiment, the material of the second electrical connection structure 160 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0056] It should be noted that, in this embodiment, the semiconductor structure further includes: a dielectric layer 170, located on the substrate 100 and covering the third electrode layer 30 and the second dielectric layer 130.

[0057] Dielectric layer 170 is used to achieve isolation between electrical connection structures. The material of dielectric layer 170 is a dielectric material. As an example, the material of dielectric layer 170 is silicon oxide.

[0058] It should also be noted that in this embodiment, a semiconductor structure comprising three stacked electrode layers is used as an example for illustration. In other embodiments, additional electrode layers may be stacked on top of the third electrode layer.

[0059] For example, in other embodiments, the semiconductor structure further includes: one or more fourth electrode layers located on the third electrode layer, and on a projection plane parallel to the substrate, odd-numbered fourth electrode layers cover the first region and the connection region and expose the second region, and even-numbered fourth electrode layers have overlapping regions with the first region and the second region; and a fourth dielectric layer located between the fourth electrode layer and the third electrode layer and between adjacent fourth electrode layers.

[0060] The first electrical connection structure penetrates the fourth electrode layer of the odd-numbered layer located in the connection region and is in contact with the second electrode layer. The first electrical connection structure electrically connects the second electrode layer and the fourth electrode layer of the odd-numbered layer.

[0061] The second electrical connection structure penetrates the fourth electrode layer of the even-numbered layer located in the second region and is in contact with the first electrode layer. The second electrical connection structure electrically connects the first electrode layer and the fourth electrode layer of the even-numbered layer.

[0062] Correspondingly, MIM capacitors are formed between two adjacent electrode layers, and multiple MIM capacitors are connected in parallel, which helps to further improve the equivalent capacitance density.

[0063] It should be noted that in this embodiment, odd-numbered layers and even-numbered layers refer to the number of layers corresponding to the fourth electrode layer along the direction from the substrate to the first electrode layer. For example, the fourth electrode layer closest to the third electrode layer is the first fourth electrode layer, and the fourth electrode layer adjacent to the first electrode layer is the second fourth electrode layer. Accordingly, the first fourth electrode layer is an odd-numbered fourth electrode layer, the second fourth electrode layer is an even-numbered fourth electrode layer, and so on.

[0064] In one embodiment, the second electrode layer of the connection region covers the first electrode layer located on the substrate; the first electrical connection structure penetrates the second electrode layer located in the connection region; and the second electrical connection structure penetrates the first electrode layer located in the second region.

[0065] For a detailed description of the fourth electrode layer and the fourth dielectric layer, please refer to the corresponding description of the first electrode layer and the first dielectric layer in the foregoing embodiments, which will not be repeated here.

[0066] Figure 3 and Figure 4 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. Note that the diagram is not a cross-sectional view. Figure 4 for Figure 3 The corresponding top view. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are:

[0067] In this embodiment, a second electrical connection structure group 220 is provided in the semiconductor structure, including: a third electrical connection structure 150a, which is in contact with the first electrode layer 10a; and a fourth electrical connection structure 160a, which is in contact with the second electrode layer 20a and the third electrode layer 30a.

[0068] In this embodiment, when the MIM capacitor is working, the second electrode layer 20a and the third electrode layer 30a are connected to the same potential through the fourth electrical connection structure 160a, and the first electrode layer 10a is connected to another potential through the third electrical connection structure 150a. Thus, the second electrode layer 20a and the first electrode layer 10a of the first region 10I form a MIM capacitor, and the third electrode layer 30a and the first electrode layer 10a of the second region 10II form a MIM capacitor. This can improve the ability to obtain different equivalent capacitance densities, thereby meeting the needs of different types of capacitors.

[0069] The third electrical connection structure 150a is used to realize the electrical connection between the first electrode layer 10a and the external circuit.

[0070] The fourth electrical connection structure 160a is used to realize the electrical connection between the second electrode layer 20a and the third electrode layer 30a, and also to realize the electrical connection between the second electrode layer 20a and the third electrode layer 30a and the external circuit.

[0071] Specifically, in this embodiment, the first electrode layer 10a further includes a third region 10III for electrical connection; the second electrode layer 20a includes a connection region 20I for electrical connection.

[0072] Accordingly, the third electrode layer 30a covers the connection region 20I and exposes the third region 10III, so that a third electrical connection structure in contact with the first electrode layer 10a is formed in the third region 10III, and a fourth electrical connection structure penetrating the third electrode layer 30a and in contact with the second electrode layer 20a is formed in the connection region 20I.

[0073] Accordingly, in this embodiment, the third electrical connection structure 150a is located on the third region 10III and is in contact with the first electrode layer 10a; the fourth electrical connection structure 160a penetrates the second dielectric layer and the third electrode layer 30a located in the connection region 20I and is in contact with the second electrode layer 20a, and the second electrical connection structure 160a is electrically connected to the second electrode layer 20a and the third electrode layer 30a.

[0074] For a detailed description of the third electrical connection structure 150a and the fourth electrical connection structure 160a, please refer to the corresponding descriptions of the first electrical connection structure and the second electrical connection structure in the foregoing embodiments, which will not be repeated here.

[0075] It should be noted that, in other embodiments, the semiconductor structure may further include: a fifth dielectric layer located on the third electrode layer; and a fifth electrode layer located on the fifth dielectric layer, wherein on a projection plane parallel to the substrate, a fourth electrode layer covers the third region.

[0076] The third electrical connection structure penetrates the fifth electrode layer located in the third region and is in contact with the first electrode layer. More specifically, the third electrical connection structure penetrates the first electrode layer located in the third region; the fourth electrical connection structure penetrates the second electrode layer located in the connection region.

[0077] Correspondingly, when the MIM capacitor is working, the first electrode layer and the fifth electrode layer are connected to the same potential, and the second electrode layer and the third electrode layer are connected to the same potential. This makes the first electrode layer and the second electrode layer form a capacitor, the first electrode layer and the third electrode layer form a capacitor, and the third electrode layer and the fifth electrode layer form a capacitor, which can also improve the capacitance value per unit area.

[0078] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0079] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0080] refer to Figure 5 Provides a base of 100.

[0081] Substrate 100 is used to provide a process platform for the subsequent formation of MIM capacitors.

[0082] In this embodiment, the substrate 100 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0083] In this embodiment, the MIM capacitor is formed in the back-end process. Therefore, an inter-metal dielectric (IMD) layer (not shown) is also formed on the substrate 100. Depending on the process, one or more stacked metal layers are formed in the inter-metal dielectric layer along the normal direction of the substrate surface, such as a first metal (M1) layer, a second metal (M2) layer, etc. When there are multiple metal layers, adjacent metal layers are electrically connected through a via interconnect structure located between them.

[0084] Continue to refer to Figure 5 An etch stop layer 110 is formed on the substrate 100.

[0085] The etching stop layer 110 is used to define the etching stop position during the subsequent formation of the first electrode layer, the first electrical connection structure and the second electrical connection structure, or the first electrode layer, the third electrical connection structure and the fourth electrical connection structure, so as to reduce the probability of damage to the substrate 100, and also to improve the bottom height consistency of the first electrical connection structure and the second electrical connection structure, and the bottom height consistency of the third electrical connection structure and the fourth electrical connection structure.

[0086] As an example, the etch stop layer 110 is made of silicon nitride. In other embodiments, the etch stop layer may also be made of other materials that have high etch selectivity with the substrate material, such as one or more of silicon nitride, aluminum oxide, aluminum nitride, and NDC (nitride-doped carbon).

[0087] refer to Figure 6 A first electrode layer 10 is formed on a substrate 100. The first electrode layer 10 includes a first region 10I and a second region 10II.

[0088] The first electrode layer 10 is used as the electrode plate of the MIM capacitor. Specifically, the first electrode layer 10 is formed on the etch stop layer 110.

[0089] The material of the first electrode layer 10 is a conductive material. As an example, the material of the first electrode layer 10 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0090] In this embodiment, the step of forming the first electrode layer 10 includes: forming a first electrode material layer (not shown) on the etch stop layer 110; patterning the first electrode material layer to form the first electrode layer 10.

[0091] Specifically, an etching process is used to pattern the first electrode material layer. During the patterning of the first electrode material layer, the etching stop layer 110 can define the etching stop position, thereby reducing the probability of the patterning process of the first electrode material layer causing damage to the substrate 100.

[0092] In this embodiment, the first electrode layer 10 is formed using a sputtering process. Sputtering has high process compatibility and low process cost.

[0093] refer to Figure 7 A first dielectric layer 120 is formed on the top and sidewalls of the first electrode layer 10.

[0094] The first dielectric layer 120 serves as an insulating layer in the formation of the MIM capacitor, used to isolate the first electrode layer 10 and the subsequent second electrode layer. Specifically, the first dielectric layer 120 conformally covers the first electrode layer 10 and the substrate 100.

[0095] In this embodiment, the first dielectric layer 120 is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor, and correspondingly increase the capacitance density.

[0096] Specifically, the first dielectric layer 120 is a high-k dielectric layer formed by stacking, that is, the first dielectric layer 120 is a high-k composite dielectric layer. Once the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the first dielectric layer 120 can meet the process requirements while maintaining good formation quality. For this purpose, the high-k dielectric material includes any one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0097] In this embodiment, the first dielectric layer 120 is a ZAZ layer. The ZAZ layer comprises a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking.

[0098] In other embodiments, depending on process requirements, the material of the first dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0099] In this embodiment, chemical vapor deposition (CVD) is used to form the first dielectric layer 120, which offers high process compatibility and helps reduce process costs. In other embodiments, based on actual process requirements, other suitable deposition processes can be used to form the first dielectric layer, such as atomic layer deposition (ALD).

[0100] refer to Figure 8 A second electrode layer 20 is formed on the first dielectric layer 120, and the second electrode layer 20 covers the first dielectric layer 120 located in the first region 10I.

[0101] The second electrode layer 20 is used as the electrode plate of the MIM capacitor.

[0102] The second electrode layer 20 covers the first dielectric layer 120 located in the first region 10I, so that the second electrode layer 20 is disposed opposite to the first region 10I, and thus the second electrode layer 20 can form a MIM capacitor with the first electrode layer 10 in the first region 10I.

[0103] In this embodiment, the second electrode layer 20 exposes the second region 10II so that the third electrode layer formed subsequently can cover the second region 10II, thereby facilitating the subsequent formation of a second electrical connection structure that penetrates the second region 10II. The second electrical connection structure can contact the first electrode layer 10, thereby realizing the electrical connection between the first electrode layer 10 and the third electrode layer.

[0104] It should be noted that, in this embodiment, during the step of forming the second electrode layer 20, the second electrode layer 20 includes a connection region 20I for electrical connection. In this embodiment, the connection region 20I is located on the side of the first electrode layer 10. The connection region 20I is used to subsequently form an electrical connection structure that electrically connects the second electrode layer 20.

[0105] The material of the second electrode layer 20 is a conductive material. As an example, the material of the first electrode layer 20 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0106] In this embodiment, the step of forming the second electrode layer 20 includes: conformally covering the second electrode material layer (not shown) on the first dielectric layer 120; removing the second electrode material layer located in the second region 10II and a portion of the second electrode material layer on the first dielectric layer 120 located on the substrate 100, and using the remaining second electrode material layer as the second electrode layer 20.

[0107] As an example, a sputtering process is used to form a second electrode material layer.

[0108] refer to Figure 9 A second dielectric layer 130 is formed on the second electrode layer 20 and the second region 10II.

[0109] The second dielectric layer 130 serves as an insulating layer for the MIM capacitor, and is used to isolate the second electrode layer 20 from the subsequently formed third electrode layer.

[0110] In this embodiment, the second dielectric layer 130 conformally covers the second electrode layer 20 and the second region 10II.

[0111] In this embodiment, the material of the second dielectric layer 130 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor, and correspondingly increase the capacitance density.

[0112] Specifically, the second dielectric layer 130 is a high-k dielectric layer formed by stacking, that is, the second dielectric layer 130 is a high-k composite dielectric layer. After the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the second dielectric layer 130 can meet the process requirements while having better formation quality.

[0113] Therefore, the materials for the high-k dielectric layer include any one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0114] The material of the second dielectric layer 130 can be the same as or different from the material of the first dielectric layer 120.

[0115] In this embodiment, the second dielectric layer 130 is a ZAZ layer. The ZAZ layer comprises a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, depending on process requirements, the material of the second dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0116] In this embodiment, chemical vapor deposition (CVD) is used to form the second dielectric layer 130, which offers high process compatibility and helps reduce process costs. In other embodiments, based on actual process requirements, other suitable deposition processes can be used to form the second dielectric layer, such as atomic layer deposition (ALD).

[0117] Continue to refer to Figure 9 A third electrode layer 30 is formed on the second dielectric layer 130. On a projection plane parallel to the substrate 100, the third electrode layer 30 overlaps with both the first region 10I and the second region 10II.

[0118] The third electrode layer 30 is used as an electrode plate in the MIM capacitor.

[0119] On a projection plane parallel to the substrate 100, the third electrode layer 30 overlaps with both the first region 10I and the second region 10II. That is, the third electrode layer 30 is disposed opposite to the second electrode layer 20 and the first electrode layer 10 to facilitate the subsequent formation of a first electrical connection structure in contact with the second electrode layer, and a second electrical connection structure in contact with both the third and first electrode layers in the second region; or, a third electrical connection structure in contact with the first electrode layer, and a fourth electrical connection structure in contact with both the second and third electrode layers.

[0120] The third electrode layer 30 and the second region 10II have an overlapping area so that a second electrical connection structure that penetrates the third electrode layer 30 and contacts the first electrode layer 10 can be subsequently formed on the second region 10II to realize the electrical connection between the third electrode layer 30 and the first electrode layer 10.

[0121] It should be noted that in the step of forming the third electrode layer 30, the third electrode layer 30 exposes the connection region 20I so that a third electrical connection structure that contacts the second electrode layer 20 can be formed on the connection region 20I, thereby realizing the electrical connection between the second electrode layer and the external circuit.

[0122] The material of the third electrode layer 30 is a conductive material. As an example, the material of the third electrode layer 30 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0123] In this embodiment, the step of forming the third electrode layer 30 includes: conformally covering the third electrode material layer (not shown) on the second dielectric layer 130; removing the third electrode material layer located in the connection region 20I, and using the remaining second electrode material layer as the third electrode layer 30.

[0124] As an example, a sputtering process is used to form a third electrode material layer.

[0125] Reference Figure 10 and Figure 11 , Figure 10 This is a cross-sectional view. Figure 11 for Figure 10 In the corresponding top view, in this embodiment, after forming the third electrode layer 30, the method for forming the semiconductor structure further includes: forming a first electrical connection structure 150 in contact with the second electrode layer 20, and forming a second electrical connection structure 160 in contact with the third electrode layer 30 and the first electrode layer 10 in the second region 10II; or, forming a third electrical connection structure in contact with the first electrode layer, and forming a fourth electrical connection structure in contact with the second electrode layer and the third electrode layer.

[0126] By forming a first electrical connection structure 150 in contact with the second electrode layer 20, and forming a second electrical connection structure 160 in contact with the third electrode layer 30 and the first electrode layer 10 in the second region 10II, capacitors are formed between the first electrode layer 10 and the second electrode layer 20, and between the second electrode layer 20 and the third electrode layer 30, which is beneficial to improving the equivalent capacitance density. Alternatively, by forming a third electrical connection structure in contact with the first electrode layer, and a fourth electrical connection structure in contact with the second and third electrode layers, capacitors are formed between the first electrode layer and the second electrode layer, and between the first electrode layer and the third electrode layer. Thus, the embodiments of the present invention are beneficial to providing options for obtaining different equivalent capacitance densities to meet the needs of different types of capacitors.

[0127] In this embodiment, the example is given of forming a first electrical connection structure 150 and a second electrical connection structure 160, such that the first electrode layer 10 and the second electrode layer 20, as well as the second electrode layer 20 and the third electrode layer 30, both constitute capacitors, which is beneficial to improving the equivalent capacitance density.

[0128] Therefore, in this embodiment, the first electrode layer 10 and the second electrode layer 20, as well as the second electrode layer 20 and the third electrode layer 30, each constitute a capacitor. The first electrode layer 10 and the third electrode layer 30 are connected to the same potential through the second electrical connection structure 160, thereby connecting the two capacitors in parallel, which increases the capacitance value per unit area, i.e., increases the equivalent capacitance density.

[0129] The first electrical connection structure 150 is used to realize the electrical connection between the second electrode layer 20 and the external circuit.

[0130] The material of the first electrical connection structure 150 is a conductive material, including one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0131] In this embodiment, the step of forming the first electrical connection structure 150 includes: forming the first electrical connection structure 150 in contact with the second electrode layer 20 on the connection region 20I.

[0132] In this embodiment, the second electrode layer 20 of the connection region 20I covers the first dielectric layer 120 located on the substrate 100; the first electrical connection structure 150 penetrates the second electrode layer 20 of the connection region 20I, and the bottom of the first electrical connection structure 150 contacts the top surface of the etch stop layer 110, so that the bottom of the first electrical connection structure 150 can stop on the etch stop layer 110, which is beneficial to improving the bottom height consistency of the first connection structure 150.

[0133] The second electrical connection structure 160 is used to electrically connect the first electrode layer 10 and the third electrode layer 30, and also to realize the electrical connection between the first electrode layer 10 and the third electrode layer 30 and the external circuit, so that when the capacitor is working, the first electrode layer 10 and the third electrode layer 30 can be connected to the same potential.

[0134] The material of the second electrical connection structure 160 is a conductive material, including one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0135] In this embodiment, the step of forming the second electrical connection structure 160 includes: forming a second electrical connection structure 160 that penetrates the first dielectric layer 120, the second dielectric layer 130 and the third electrode layer 30 located in the second region 10II and is in contact with the first electrode layer 10, wherein the second electrical connection structure 160 is electrically connected to the first electrode layer 10 and the third electrode layer 30.

[0136] In this embodiment, the second electrical connection structure 160 penetrates the first electrode layer 10, and the bottom of the second electrical connection structure 160 is in contact with the top surface of the etch stop layer 110, thereby improving the height uniformity of the bottom of the second electrical connection structure 160.

[0137] In this embodiment, the first electrical connection structure 150 and the second electrical connection structure 160 constitute the first electrical connection structure group 210.

[0138] It should be noted that, in this embodiment, before forming the first electrical connection structure 150 and the second electrical connection structure 160, the method for forming the semiconductor structure further includes: forming a dielectric layer 170 on the substrate 100.

[0139] Dielectric layer 170 is used to achieve isolation between electrical connection structures. The material of dielectric layer 170 is a dielectric material. As an example, the material of dielectric layer 170 is silicon oxide.

[0140] Accordingly, in this embodiment, the steps of forming the first electrical connection structure 150 and the second electrical connection structure 160 include: forming a first conductive via (not shown) penetrating the second electrode layer 20 and the dielectric layer 170 of the connection region 20I; forming a second conductive via (not shown) penetrating the first electrode layer 10 and the third electrode layer 30 of the second region 10II; and filling the first conductive via and the second conductive via to form the first electrical connection structure 150 located in the first conductive via and the second electrical connection structure 160 located in the second conductive via.

[0141] In this embodiment, an etching process is used to form a first conductive via and a second conductive via with the top surface of the etching stop layer 110 as the etching stop position. This reduces the probability of the etching process forming the first conductive via and the second conductive via damaging the substrate 100 and improves the consistency of the bottom height of the first conductive via and the second conductive via.

[0142] It should also be noted that this embodiment uses the formation of three stacked electrode layers as an example. In other embodiments, after forming the third electrode layer, more electrode layers may be stacked to form.

[0143] For example, in other embodiments, after forming the third electrode layer and before forming the first electrical connection structure and the second electrical connection structure, the method for forming the semiconductor structure further includes: forming one or more fourth electrode layers on the third electrode layer, and forming a fourth dielectric layer between adjacent fourth electrode layers and between the fourth electrode layer and the third electrode layer, and on a projection plane parallel to the substrate, the odd-numbered fourth electrode layers cover the first region and the connection region and expose the second region, and the even-numbered fourth electrode layers have overlapping regions with the first region and the second region.

[0144] In the step of forming the first electrical connection structure, the first electrical connection structure penetrates the odd-numbered fourth electrode layer located in the connection region and is in contact with the second electrode layer. The first electrical connection structure electrically connects the second electrode layer and the odd-numbered fourth electrode layer.

[0145] In the step of forming the second electrical connection structure, the second electrical connection structure penetrates the fourth electrode layer of the even-numbered layer located in the second region and is in contact with the first electrode layer. The second electrical connection structure electrically connects the first electrode layer and the fourth electrode layer of the even-numbered layer.

[0146] Correspondingly, MIM capacitors are formed between two adjacent electrode layers, and multiple MIM capacitors are connected in parallel, which helps to further improve the equivalent capacitance density.

[0147] It should be noted that in this embodiment, odd-numbered layers and even-numbered layers refer to the number of layers corresponding to the fourth electrode layer along the direction from the substrate to the first electrode layer. For example, the fourth electrode layer closest to the third electrode layer is the first fourth electrode layer, and the fourth electrode layer adjacent to the first electrode layer is the second fourth electrode layer. Accordingly, the first fourth electrode layer is an odd-numbered fourth electrode layer, the second fourth electrode layer is an even-numbered fourth electrode layer, and so on.

[0148] In one embodiment, the second electrode layer of the connection region covers the first electrode layer located on the substrate; the first electrical connection structure penetrates the second electrode layer located in the connection region; and the second electrical connection structure penetrates the first electrode layer located in the second region.

[0149] Figures 12 to 14 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are:

[0150] refer to Figure 12 In the step of forming the first electrode layer 10a, the first electrode layer 10a further includes a third region 10III for electrical connection; in the step of forming the second electrode layer 20a, the second electrode layer 20a includes a connection region 20I for electrical connection.

[0151] Continue to refer to Figure 12 In the step of forming the third electrode layer 30a, the third electrode layer 30a covers the connection region 20I and exposes the third region 10III so that a third electrical connection structure in contact with the first electrode layer 10a can be formed in the third region 10III, and a fourth electrical connection structure penetrating the third electrode layer 30a and in contact with the second electrode layer 20a can be formed in the connection region 20I.

[0152] refer to Figures 13 to 14 , Figure 13 This is a cross-sectional view. Figure 14 for Figure 13 The corresponding top view shows a third electrical connection structure in contact with the first electrode layer, and a fourth electrical connection structure in contact with the second and third electrode layers.

[0153] In this embodiment, when the MIM capacitor is working, the second electrode layer 20a and the third electrode layer 30a are connected to the same potential through the fourth electrical connection structure 160a, and the first electrode layer 10a is connected to another potential through the third electrical connection structure 150a. Thus, the second electrode layer 20a and the first electrode layer 10a of the first region 10I form a MIM capacitor, and the third electrode layer 30a and the first electrode layer 10a of the second region 10II form a MIM capacitor. This can improve the ability to obtain different equivalent capacitance densities, thereby meeting the needs of different types of capacitors.

[0154] The third electrical connection structure 150a is used to realize the electrical connection between the first electrode layer 10a and the external circuit.

[0155] In this embodiment, the step of forming the third electrical connection structure 150a includes: forming a first electrical connection structure 150a in contact with the first electrode layer 10a on the third region 10III.

[0156] The fourth electrical connection structure 160a is used to realize the electrical connection between the second electrode layer 20a and the third electrode layer 30a, and also to realize the electrical connection between the second electrode layer 20a and the third electrode layer 30a and the external circuit.

[0157] In this embodiment, the step of forming the fourth electrical connection structure 160a includes: forming a fourth electrical connection structure 160a that penetrates the second dielectric layer and the third electrode layer 30a and is in contact with the second electrode layer 20a in the connection region 20I, and the fourth electrical connection structure 160a electrically connects the second electrode layer 20a and the third electrode layer 30a.

[0158] For a detailed description of the materials and formation steps of the third electrical connection structure 150a and the fourth electrical connection structure 160a, please refer to the corresponding descriptions of the first electrical connection structure and the second electrical connection structure in the foregoing embodiments, which will not be repeated here.

[0159] It should be noted that, in other embodiments, the method for forming the semiconductor structure further includes: after forming the third electrode layer and before forming the third electrical connection structure and the fourth electrical connection structure, forming a fifth dielectric layer on the third electrode layer; forming a fifth electrode layer on the fifth dielectric layer, wherein the fifth electrode layer covers the third region on a projection plane parallel to the substrate.

[0160] In the step of forming the third electrical connection structure, the third electrical connection structure penetrates the fifth electrode layer located in the third region and is in contact with the first electrode layer.

[0161] More specifically, the third electrical connection structure penetrates the first electrode layer located in the third region; the fourth electrical connection structure penetrates the second electrode layer located in the connection region.

[0162] Correspondingly, when the MIM capacitor is working, the first electrode layer and the fifth electrode layer are connected to the same potential, and the second electrode layer and the third electrode layer are connected to the same potential. This makes the first electrode layer and the second electrode layer form a capacitor, the first electrode layer and the third electrode layer form a capacitor, and the third electrode layer and the fifth electrode layer form a capacitor, which can also improve the capacitance value per unit area.

[0163] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A first electrode layer is located on the substrate, and the first electrode layer includes a first region and a second region; the first electrode layer also includes a third region for electrical connection; The first dielectric layer is located on the top and sidewalls of the first electrode layer; The second electrode layer covers the first dielectric layer located in the first region; The second electrode layer includes a connection region for electrical connection; The second dielectric layer is located on the second electrode layer and the second region; The third electrode layer is located on the second dielectric layer. On a projection plane parallel to the substrate, the third electrode layer overlaps with both the first region and the second region. The third electrode layer covers the connection area and exposes the third region; The second electrical connection structure group includes: a third electrical connection structure in contact with the first electrode layer; a fourth electrical connection structure in contact with the second electrode layer and the third electrode layer; the third electrical connection structure is located on the third region and in contact with the first electrode layer; the fourth electrical connection structure penetrates the second dielectric layer and the third electrode layer located in the connection region and is in contact with the second electrode layer, and the fourth electrical connection structure is electrically connected to the second electrode layer and the third electrode layer.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a fifth dielectric layer located on the third electrode layer; and a fifth electrode layer located on the fifth dielectric layer, which covers the third region on a projection plane parallel to the substrate. The third electrical connection structure penetrates the fifth electrode layer located in the third region and is in contact with the first electrode layer.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, The third electrical connection structure penetrates the first electrode layer located in the third region; the fourth electrical connection structure penetrates the second electrode layer located in the connection region.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an etch stop layer located between the substrate and the first electrode layer, and between the substrate and the first dielectric layer.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer includes any one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN; The material of the second dielectric layer includes any one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN; The material of the first electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; The material of the second electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; The material of the third electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the third electrical connection structure includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; The material of the fourth electrical connection structure includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

7. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A first electrode layer is formed on the substrate, the first electrode layer including a first region and a second region; in the step of forming the first electrode layer, the first electrode layer further includes a third region for electrical connection; A first dielectric layer is formed on the top and sidewalls of the first electrode layer; A second electrode layer is formed on the first dielectric layer, the second electrode layer covering the first dielectric layer located in the first region; the second electrode layer includes a connection region for electrical connection; A second dielectric layer is formed on the second electrode layer and the second region; A third electrode layer is formed on the second dielectric layer, and on a projection plane parallel to the substrate, the third electrode layer overlaps with both the first region and the second region; in the step of forming the third electrode layer, the third electrode layer covers the connection area and exposes the third region; A third electrical connection structure is formed that is in contact with the first electrode layer, and a fourth electrical connection structure is formed that is in contact with the second electrode layer and the third electrode layer; The step of forming the third electrical connection structure includes: forming a third electrical connection structure in contact with the first electrode layer on the third region; The step of forming the fourth electrical connection structure includes: forming a fourth electrical connection structure that penetrates the second dielectric layer and the third electrode layer and is in contact with the second electrode layer in the connection region, wherein the fourth electrical connection structure electrically connects the second electrode layer and the third electrode layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the semiconductor structure further includes: forming a fifth dielectric layer on the third electrode layer after forming the third electrode layer and before forming the third electrical connection structure and the fourth electrical connection structure; forming a fifth electrode layer on the fifth dielectric layer, wherein the fifth electrode layer covers the third region on a projection plane parallel to the substrate; In the step of forming the third electrical connection structure, the third electrical connection structure penetrates the fifth electrode layer located in the third region and is in contact with the first electrode layer.

9. The method for forming a semiconductor structure as described in claim 7 or 8, characterized in that, The third electrical connection structure penetrates the first electrode layer of the third region; the fourth electrical connection structure penetrates the second electrode layer of the connection region.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the semiconductor structure further includes: after providing the substrate and before forming the first electrode layer, forming an etch stop layer on the substrate.

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