Reversible resistive memory logic gate device

Abstract

A memory device includes two phase change memory (PCM) cells and a bridge. A first PCM cell includes an electrical input and a phase change material. A second PCM cell includes an electrical input independent of the electrical input of the first PCM cell and another phase change material. The bridge is electrically connected to both PCM cells.

Description

Technical Field

[0001] This invention relates to integrated circuits, and more specifically, to logic gate memories for computation. Background Technology

[0002] Traditional complementary metal-oxide-semiconductor (CMOS) semiconductors have been scaled down in size, allowing the production of handheld devices with enormous computing power. However, CMOS consumes a significant amount of electrical energy, for example, to enable silicon logic gates to hold their values ​​in order to store data in computer memory. Unfortunately, this power consumption limits battery life, which reduces the flexibility and usability of devices. Summary of the Invention

[0003] According to an embodiment of the present invention, a memory device includes two phase-change memory (PCM) cells and a bridge. A first PCM cell includes an electrical input and a phase-change material. A second PCM cell includes an electrical input independent of the electrical input of the first PCM cell and another phase-change material. The bridge is electrically connected to the two PCM cells.

[0004] According to embodiments of the present invention, a memory device for an integrated circuit is disclosed. The logic gate memory device includes: a first phase-change memory (PCM) cell including a first electrical output; and a second PCM cell including a second electrical output. The memory device further includes a first electrical input electrically connected to the first PCM cell and a second electrical input electrically connected to the second PCM cell, wherein the second electrical input is independent of the first electrical input. The memory device also includes a bridge electrically connected to the first electrical output and the second electrical output.

[0005] According to an embodiment of the present invention, a method for using a memory device is disclosed, the memory device including a first PCM cell having a first input and a first phase change memory (PCM) material, a second PCM cell having a second input independent of the first input and a second PCM material, and a bridge electrically connecting a first output of the first PCM cell and a second output of the second PCM cell. The method includes: transmitting a first current pulse from the first input to the first PCM material to generate a first amorphous region in the first PCM cell; measuring the voltage drop across the first PCM cell and the second PCM cell using a third input electrically connected to the first PCM cell and a second input electrically connected to the second PCM cell; and determining whether the memory device is storing a true result or a false result based on the voltage drop. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view of an integrated circuit including a NAND logic gate memory device (LGMD) according to an embodiment of the present invention, wherein the LGMD includes phase change memory (PCM) material.

[0007] Figures 2A-2H These are a series of cross-sectional views of a NAND LGMD in different states according to an embodiment of the present invention.

[0008] Figure 3 This is a cross-sectional view of a "NOR" LGMD comprising PCM material according to an embodiment of the present invention.

[0009] Figures 4A-4H These are a series of cross-sectional views of a NOR LGMD under different states according to an embodiment of the present invention.

[0010] Figures 5A-5D These are a series of cross-sectional views of "NOT" LGMD, which includes PCM material, according to an embodiment of the present invention. Detailed Implementation

[0011] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments may be devised without departing from the scope of the invention. Note that various connections and positional relationships (e.g., above, below, adjacent, etc.) are set forth between elements in the following description and drawings. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limiting in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, the description of forming layer "A" above layer "B" includes cases where one or more intermediate layers (e.g., layers "C" and "D") are between layer "A" and layer "B," provided that the relevant characteristics and functions of layers "A" and "B" are substantially not altered by the intermediate layers.

[0012] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms “comprising,” “including,” “having,” “containing,” or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such compositions, mixtures, processes, methods, articles, or apparatus. Furthermore, unless otherwise expressly stated, any numerical ranges included herein include their boundaries.

[0013] For the purposes described below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall apply to the described structures and methods, as oriented as shown in the accompanying drawings. The terms “cover,” “on top,” “positioned on,” or “positioned on top” indicate that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an intermediate element (such as an interface structure) may be present between the first and second elements. The term “direct contact” means that the first element (such as a first structure) and the second element (such as a second structure) are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer. It should be noted that the term “selective to…”, such as, for example, “the first element is selective to the second element,” means that the first element can be etched, and the second element can act as an etch stop layer.

[0014] Figure 1 This is a cross-sectional view of an integrated circuit 100 including a NAND logic gate memory device (LGMD) 102. In the illustrated embodiment, the LGMD 102 includes inputs 104-1 to 104-4 (collectively referred to as "input 104"), PCM cells 106-1 and 106-2 (collectively referred to as "PCM cell 106"), outputs 108-1 and 108-2 (collectively referred to as "output 108"), and bridges 110-1 and 110-2 (collectively referred to as "bridge 110"). PCM units 106-1 and 106-2 respectively include bottom electrodes 112-1 and 112-2 (collectively referred to as "bottom electrode 112"), heaters 114-1 and 114-2 (collectively referred to as "heater 114"), PCM materials 116-1 and 116-2 (collectively referred to as "PCM material 116"), and top electrodes 118-1 to 118-4 (collectively referred to as "top electrode 118").

[0015] In the illustrated embodiment, integrated circuit 100 is formed from multiple layers 120-1 to 120-12 (collectively referred to as “layers 120”), and components of LGMD 102 are located in each layer 120. For example, PCM cells 106-1 and 106-2 extend through layers 120-4 to 120-8. In another example, inputs 104-1 and 104-2 are in layer 120-9, while inputs 104-3 and 104-4 are in layer 120-4. Additionally, LGMD 102 can be connected to other components (e.g., silicon transistors, not shown) in integrated circuit 100 via pathways 122-1 to 122-4, which are respectively connected to inputs 104-1 and 104-2 and bridge 110.

[0016] In the illustrated embodiment, input 104-1 is electrically connected to bottom electrode 112-1 via top electrode 118-1 and passage 122-5, which are adjacent to each other and electrically connected. Bottom electrode 112-1 is adjacent to and electrically connected to PCM unit 106-1, specifically to heater 114-1. Heater 114-1 is adjacent to and electrically connected to PCM material 116-1. PCM material 116-1 is adjacent to and electrically connected to top electrode 118-3. Top electrode 118-3 is adjacent to and electrically connected to output 108-1. Output 108-1 is adjacent to and electrically connected to bridge 110-2. Furthermore, input 104-2 is electrically connected to bottom electrode 112-2 via top electrode 118-2 and passage 122-6, which are adjacent to each other and electrically connected. Bottom electrode 112-2 is adjacent to and electrically connected to PCM unit 106-2, specifically to heater 114-2. Heater 114-2 is adjacent to and electrically connected to PCM material 116-2. PCM material 116-2 is adjacent to and electrically connected to the top electrode 118-4. Top electrode 118-4 is adjacent to and electrically connected to the output 108-2. Output 108-2 is adjacent to and electrically connected to the bridge 110-2. Furthermore, inputs 104-3 and 104-4 are adjacent to and electrically connected to the bridge 110-1. Input 104-3 is adjacent to and electrically connected to the bottom electrode 112-1, and input 104-4 is adjacent to and electrically connected to the bottom electrode 112-2. Additionally, the heater 114 is much narrower than the PCM material 116, therefore, in this example, the PCM unit 106 is "mushroom-shaped." However, other types of PCM units 106 may be used in other embodiments.

[0017] Input 104, output 108, and bridge 110 can be made of highly conductive materials, such as, for example, copper (Cu). Bottom electrode 112 and top electrode 118 are made of conductive materials, such as metals, such as titanium nitride (TiN) or tungsten (W). Heater 114 is an electrode composed of a high-resistivity metal, such as TiN, and having a relatively narrow cross-sectional area, which concentrates the current passing through PCM cell 106. This allows heater 114 to generate heat through resistance heating during electrical pulses, which can be used to selectively change the temperature of PCM material 116, for example, above its crystallization and melting temperatures. Furthermore, heater 114 can be made of a variety of different conductive materials that can be arranged in multiple layers.

[0018] PCM material 116 may be substantially composed of a phase change material, such as germanium-antimony-tellurium (GST), gallium-antimony-tellurium (GaST), or silver-iridium-antimony-telluride (AIST) materials, although other materials may be suitably used. Furthermore, PCM materials 116-1 and 116-2 are identical in some embodiments and different in others. The terms “substantially composed of” and “substantially constituted of” as used herein with respect to materials of different layers indicate that other materials (if present) do not substantially alter the fundamental properties of said material. For example, PCM material 116, substantially composed of GST material, does not include other materials that substantially alter the fundamental properties of the GST material.

[0019] In the illustrated embodiment, the PCM cell 106 can be written to and rewritten as an independent memory cell by delivering current pulses from heaters 114-1 and 114-2 to top electrodes 118-3 and 118-4, respectively. This can be done at various voltages to read or write values ​​on the PCM cell 106. More specifically, inputs 104-1 and 104-2 are configured to provide write current pulses, while inputs 104-3 and 104-4 are configured to provide read current pulses. For example, for writing, a high-voltage current (e.g., 1 volt (V) to 4V) can be used for a short period of time, which can cause the PCM material 116-1 to heat above its melting point. Once the current stops flowing, the PCM cell 106-1 can be rapidly cooled, forming region 124 in a process known as “reset”. Region 124 is a dome-shaped region of the PCM material 116 having an amorphous structure, although the remainder of the PCM material 116 outside region 124 remains polycrystalline. Typically, this amorphous structure lacks a defined structure. However, locally disjoint nuclei (i.e., small crystalline regions of PCM material 116) may exist within region 124. Creating region 124 can cause the resistance across PCM cell 106-1 to increase compared to a single polycrystalline structure (e.g., PCM cell 106-2). However, the resistance value of PCM cell 106 can be read as a single unit using a low voltage (e.g., 0.2V) current without altering the state of PCM material 116 or the resistance value of PCM cell 106. This may be because the read pulse begins at bridge 110-1 and ends at bridge 110-2.

[0020] Furthermore, PCM material 116-1 can be rewritten and returned to a separate polycrystalline structure by “setting” PCM cell 106-1. To rewrite PCM material 116-1, a high-voltage pulse (e.g., 1V to 4V) can be used for a short period (e.g., 10 nanoseconds (ns)), which can cause PCM material 116-1 to heat above its crystallization point but not to its melting point. Since the crystallization temperature is below the melting temperature, PCM material 116-1 can anneal and crystallize once the current stops flowing. This causes a decrease in resistance across PCM cell 106-1 compared to having amorphous region 124 (relative to PCM cell 106-2). This new resistance value can then be read using a low voltage (e.g., 0.2V) current without changing the state of PCM material 116-1 or the resistance value of PCM cell 106-1.

[0021] In some embodiments, the melting temperature of the PCM material 116 may be approximately 600 degrees Celsius (°C). In some embodiments, the crystallization temperature of the PCM material 116 may be approximately 180°C. Furthermore, the process of setting and resetting the PCM unit 106 may be repeated, and in some embodiments, different regions 124 with different resistances may be generated in the PCM material 116 (e.g., due to different sizes of the regions 124 and / or different amounts of crystal nuclei in the regions 124). This allows the PCM unit 106 to have various different resistances that can be generated by changing the reset parameters. Therefore, if the PCM unit 106 is considered to represent information digits, these digits may be non-binary (as opposed to conventional bits). However, in some embodiments, the PCM unit 106 may be used as a bit by having or not having uniform regions 124 in the PCM material 116, respectively. Therefore, the PCM unit 106 may have high resistance (also referred to as low voltage output or "0") or low resistance (also referred to as high voltage output or "1").

[0022] Furthermore, the arrangement of two parallel PCM cells 106 with two independent inputs 104-1 and 104-2 respectively allows the LGMD 102 to function as a reversible, rewritable, and / or programmable resistive memory device that can store the results of NAND logic operations performed by the LGMD 102. The logic results can be determined without using a silicon substrate and can be stored without consuming electrical power.

[0023] This operation of LGMD 102 is in Figures 2A-2H The image shows a series of cross-sectional views of the NAND LGMD 102 in different states. Figures 2A-2H They should be shown in pairs because the LGMD 102 operates in two phases. The first phase is write / programming (or non-write / programming if the input is "false") (e.g. Figure 2A, Figure 2C , Figure 2E and Figure 2G As shown), and the second stage is reading (as shown in the image). Figure 2B , Figure 2D , Figure 2F and Figure 2H (As shown).

[0024] Figure 2A The diagram shows LGMD 102 in a state where the PCM materials 116 are all crystalline (also known as set), so the resistance across the PCM cells 106 is low. This could be the initial state of LGMD 102, or it could be the result of a set current pulse being applied to both PCM materials 116, for example, after the logic gate result is no longer needed, to prepare LGMD 102 for a new operation. Subsequently, this state can be maintained with both inputs 104-1 and 104-2 given "false" (also known as 0) inputs, such that zero current is applied to reset the PCM materials 116.

[0025] Figure 2B The image shows the LGMD 102 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The reading indicates that due to the low resistance of the LGMD 102, there is a high voltage output through the LGMD 102 (also known as a low voltage drop). Therefore, a "true" (also known as a 1) result is returned.

[0026] Figure 2C The LGMD 102 is shown in a state where PCM material 116-1 includes an amorphous (also known as a reset) region 124-1, and PCM material 116-2 is crystalline. Therefore, the resistance across PCM cell 106-1 is high, but the resistance across PCM cell 106-2 is low. This could be a result of a "true" input at input 104-1, causing a reset current pulse to be applied to PCM material 116-1, but a "false" input at input 104-2.

[0027] Figure 2D The image shows LGMD 102 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The reading shows a high voltage output through LGMD 102 due to the low-resistance path through PCM cell 106-2. Therefore, a "true" result is returned.

[0028] Figure 2EThe LGMD 102 is shown in a state where PCM material 116-1 is crystalline and PCM material 116-2 includes amorphous regions 124-2. Therefore, the resistance across PCM cell 106-1 is low, but the resistance across PCM cell 106-2 is high. This could be a result of a "true" input at input 104-2, causing a reset current pulse to be applied to PCM material 116-2, but a "false" input at input 104-1.

[0029] Figure 2F The image shows LGMD 102 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The reading shows a high voltage output through LGMD 102 due to the low-resistance path through PCM cell 106-1. Therefore, a "true" result is returned.

[0030] Figure 2G The LGMD 102 is shown in a state where each of the PCM materials 116 includes an amorphous region 124, so the resistance across both PCM units 106 is high. This could be a result of "true" inputs at both inputs 104-1 and 104-2, causing a reset current pulse to be applied to both PCM materials 116.

[0031] Figure 2H The image shows LGMD 102 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The reading shows a low output voltage (also known as a high voltage drop) through LGMD 102 due to the high resistance of both paths through PCM cell 106. Therefore, a "false" result is returned.

[0032] Therefore, the LGMD 102 exhibits the characteristic response of a NAND gate:

[0033] ( Figure 2A and Figure 2B Input: 0+0; Output: 1

[0034] ( Figure 2C and Figure 2D Input: 1 + 0; Output: 1

[0035] ( Figure 2E and Figure 2F Input: 0+1; Output: 1

[0036] ( Figure 2G and Figure 2H Input: 1+1; Output: 0

[0037] Therefore, LGMD 102 can be used as a logic gate during the write phase using inputs 104-1 and 104-2. After this phase is complete, the result of the NAND logic operation can be stored in LGMD 102 without power. The result can then be retrieved by reading LGMD 102 using inputs 104-3 and 104-4 (e.g., via bridge 110-1).

[0038] Figure 3 This is a cross-sectional view of the NOR (Neutral) LGMD 202. In the illustrated embodiment, LGMD 202 and LGMD 102 ( Figure 1 The same as shown, except for two separate bottom electrodes 112. Figure 1 (As shown) has been assembled into a single bottom electrode 212. Therefore, the same reference numerals will be used for LGMD 202, where the corresponding components are the same as those in LGMD 102. However, for components in LGMD 202 that differ from those in LGMD 102, more than one hundred reference numerals are used.

[0039] The results of the differences between LGMD 202 and LGMD 102 are as follows: Figures 4A-4H As shown in the figures, these figures are a series of cross-sectional views of NOR LGMD202 in different states. Figure 4A The diagram shows LGMD 202 in a state where the PCM materials 116 are all crystalline (also known as set), so the resistance across the PCM cell 106 is low. This could be the initial state of LGMD 202, or it could be the result of a set current pulse being applied to both PCM materials 116, for example, after the logic gate result is no longer needed, to prepare LGMD 202 for a new operation. Subsequently, this state can be maintained with both inputs 104-1 and 104-2 given "false" (also known as 0) inputs, such that zero current is applied to reset the PCM materials 116.

[0040] Figure 4B The image shows the LGMD 202 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The result of the read is that due to the low resistance of the LGMD 202, there is a high voltage output through the LGMD 202 (also known as a low voltage drop). Therefore, a "true" (also known as a 1) result is returned.

[0041] Figure 4CThe LGMD 202 is shown in a state where each of the PCM materials 116 comprises an amorphous region 124. Therefore, the resistance across both PCM cells 106 is high. This could be a result of a "true" input at input 104-1 and a "false" input at input 104-2, since the bottom electrode 218 connects input 104-1 to both PCM cells 106. Therefore, a reset current pulse from input 104-1 can reset both PCM materials 116.

[0042] Figure 4D The image shows LGMD 202 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The reading shows a low voltage output through LGMD 202 due to the high resistance of both paths through PCM cell 106. Therefore, a "false" result is returned.

[0043] Figure 4E The LGMD 202 is shown in a state where each of the PCM materials 116 comprises an amorphous region 124. Therefore, the resistance across both PCM cells 106 is high. This could be a result of a "false" input at input 104-1 and a "true" input at input 104-2, since the bottom electrode 218 connects input 104-2 to both PCM cells 106. Therefore, a reset current pulse from input 104-2 can reset both PCM materials 116.

[0044] Figure 4F The image shows LGMD 202 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The reading shows a low voltage output through LGMD 202 due to the high resistance of both paths through PCM cell 106. Therefore, a "false" result is returned.

[0045] Figure 4G The LGMD 202 is shown in a state where each of the PCM materials 116 includes an amorphous region 124, and therefore the resistance across the two PCM units 106 is high. This could be a result of “true” inputs at inputs 104-1 and 104-2, causing a reset current pulse to be applied to both PCM materials 116.

[0046] Figure 4H The image shows LGMD 202 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The reading shows a low voltage output (also known as a high voltage drop) through LGMD 102 due to the high resistance of both paths through PCM cell 106. Therefore, a "false" result is returned.

[0047] Therefore, the LGMD 202 exhibits the characteristic response of a NOR gate:

[0048] ( Figure 4A and Figure 4B Input: 0+0; Output: 1

[0049] ( Figure 4C and Figure 4D Input: 1 + 0; Output: 0

[0050] ( Figure 4E and Figure 4F Input: 0+1; Output: 0

[0051] ( Figure 4G and Figure 4H Input: 1+1; Output: 0

[0052] Therefore, LGMD 202 can be used as a logic gate during the write phase using inputs 104-1 and 104-2. After this phase is complete, the result of the NOR logic operation can be stored in LGMD 202 without power. The result can then be retrieved by reading LGMD 202 using inputs 104-3 and 104-4 (e.g., via bridge 110-1).

[0053] Figures 5A-5D These are a series of cross-sectional views of the "NOT" LGMD 302 in various states. In the illustrated embodiment, LGMD 302 is compared with LGMD 202 ( Figure 3 The same as shown, except that it has only a single write input (i.e., input 104-1). Therefore, because there is no input 104-2, top electrode 118-2 and path 122-6 ( Figure 1 As shown in the figure, the bottom electrode 312 has been shortened. Therefore, the same reference numerals will be used for LGMD 302, where the corresponding parts are the same as those in LGMD 102 and 202. However, for parts in LGMD 302 that differ from those in LGMD 102 and 202, two or more reference numerals will be used respectively.

[0054] The results of the differences between LGMD 302 and LGMD102 and 202 are as follows: Figures 5A-5D As shown in the image. Figure 5AThe diagram shows the LGMD202 in a state where the PCM materials 116 are all crystalline (also known as set), so the resistance across the PCM cell 106 is low. This could be the initial state of the LGMD202, or it could be the result of a set current pulse being applied to both PCM materials 116, for example, after a logic gate result is no longer needed, to prepare the LGMD202 for a new operation. Subsequently, this state can be maintained with a "false" (also known as a 0) input at input 104-1, such that zero current is applied to reset the PCM materials 116.

[0055] Figure 5B The image shows the LGMD 202 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The result of the read is that due to the low resistance of the LGMD 202, there is a high voltage output through the LGMD 202 (also known as a low voltage drop). Therefore, a "true" (also known as a 1) result is returned.

[0056] Figure 5C The LGMD 202 is shown in a state where each of the PCM materials 116 comprises an amorphous region 124. Therefore, the resistance across both PCM cells 106 is high. This can be a result of a "true" input at input 104-1, since the bottom electrode 218 connects input 104-1 to both PCM cells 106. Therefore, a reset current pulse from input 104-1 can reset both PCM materials 116.

[0057] Figure 5D The image shows LGMD 202 being read, where the voltage drop from bridge 110-1 to bridge 110-2 is measured. The reading shows a low voltage output through LGMD 202 due to the high resistance of both paths through PCM cell 106. Therefore, a "false" result is returned.

[0058] Therefore, the LGMD 302 exhibits the characteristic response of a NOT gate:

[0059] ( Figure 5A and Figure 5B Input: 0; Output: 1

[0060] ( Figure 5C and Figure 5D Input: 1; Output: 0

[0061] Therefore, LGMD 302 can be used as a logic gate during the write phase using input 104-1. After this phase is complete, the result of the NOT logic operation can be stored in LGMD 302 without power. The result can then be retrieved by reading LGMD 302 using inputs 104-3 and 104-4 (e.g., via bridge 110-1). Furthermore, two parallel PCM cells 106 provide redundancy in LGMD 302. However, in some embodiments, PCM cell 106-2 may be absent (along with its corresponding connection features), and this LGMD 302 will still be able to function as a NOT logic gate memory device.

[0062] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0063] In a preferred embodiment of the present invention, a memory device for an integrated circuit is provided, comprising: a first phase-change memory (PCM) cell including a first electrical output; a second PCM cell including a second electrical output; a first electrical input electrically connected to the first PCM cell; a second electrical input electrically connected to the second PCM cell, wherein the second electrical input is independent of the first electrical input; and a bridge electrically connected to the first and second electrical outputs. Preferably, the memory device further comprises: a third electrical input electrically connected to the first PCM cell; and a fourth electrical input electrically connected to the second PCM cell; wherein the first and second electrical inputs are configured to provide write currents to the first and second PCM cells, respectively; and wherein the third and fourth electrical inputs are configured to provide read currents to the first and second PCM cells, respectively. Preferably, the integrated circuit comprises multiple layers; and preferably, the first and third electrical inputs are located in different layers of the multiple layers. Preferably, the second and fourth electrical inputs are located in different layers of the multiple layers, and the third and fourth electrical inputs are located on the same layer of the multiple layers. Preferably, the first electrical input is not electrically connected to the second PCM cell; and the second electrical input is not electrically connected to the first PCM cell, such that the logic gate memory device has a NAND configuration. Preferably, the first electrical input is electrically connected to the second PCM cell; and the second electrical input is also electrically connected to the first PCM cell, such that the logic gate memory device has a NOR configuration. Preferably, the first PCM cell includes: a first electrode; a heater adjacent to the first electrode; a phase change material adjacent to the heater; and a second electrode adjacent to the phase change material. Preferably, the integrated circuit includes multiple layers; and the bridge is located in a different layer than the first and second electrical outputs.

Claims

1. A memory device, comprising: The first phase-change memory (PCM) unit includes: First electrical input; and First phase change material; The second PCM unit includes: A second electrical input independent of the first electrical input; Second phase change materials; A first bridge electrically connected to the top of the first PCM unit and the top of the second PCM unit; and The bottom of the first PCM unit and the bottom of the second PCM unit are electrically connected to the second bridge of the first PCM unit and the second PCM unit.

2. The memory device according to claim 1, further comprising: The third electrical input is electrically connected to the first bottom electrode; as well as The fourth electrical input is electrically connected to the second bottom electrode; The first electrical input and the second electrical input are configured to provide write current to the first phase change material and the second phase change material, respectively. as well as The third electrical input and the fourth electrical input are configured to provide read current to the first phase change material and the second phase change material, respectively.

3. The memory device of claim 2, wherein the first bottom electrode is not electrically connected to the second bottom electrode, such that the memory device has a NAND configuration.

4. The memory device of claim 2, wherein the first bottom electrode is electrically connected to the second bottom electrode, such that the memory device has a NOR configuration.

5. The memory device of claim 2, wherein the third electrical input is independent of the first electrical input, and the fourth electrical input is independent of the second electrical input, and the second bridge is electrically connected to the third electrical input and the fourth electrical input.

6. The memory device according to claim 1, further comprising: The third electrical input is electrically connected to the first bottom electrode; The first electrical input and the second electrical input are configured to provide read current to the first phase change material and the second phase change material, respectively. The third electrical input is configured to provide a write current to the first phase change material and the second phase change material; as well as The first bottom electrode is electrically connected to the second bottom electrode, thereby enabling the memory device to have a NOT configuration.

7. The memory device of claim 1, wherein the first phase change material is selected from the group consisting of germanium-antimony-tellurium (GST), gallium-antimony-tellurium (GaST), and silver-iridium-antimony-telluride (AIST).

8. The memory device according to claim 1, wherein: The first PCM unit further includes: The first bottom electrode is electrically connected to the first electrical input; A first heater electrically connected to the first bottom electrode; The first top electrode is electrically connected to the first phase change material; and A first electrical output electrically connected to the first top electrode; The second PCM unit further includes: The second bottom electrode is electrically connected to the second electrical input; A second heater electrically connected to the second bottom electrode; The second top electrode is electrically connected to the second phase change material; and A second electrical output electrically connected to the second top electrode; The first phase change material is electrically connected to the first heater; The second phase change material is electrically connected to the second heater; and The first bridge is electrically connected to the first electrical output and the second electrical output.

9. A method of using a memory device, the memory device comprising a first PCM cell having a first input and a first phase change memory (PCM) material, a second PCM cell having a second input independent of the first input and a second PCM material, and a bridge electrically connecting a first output of the first PCM cell and a second output of the second PCM cell, the method comprising: A first current pulse from the first input is transmitted to the first PCM material to generate a first amorphous region in the first PCM unit; The voltage drop across the first PCM unit and the second PCM unit is measured using a third input electrically connected to the first PCM unit and a second input electrically connected to the second PCM unit. as well as The voltage drop is used to determine whether the memory device is storing a true result or a false result.

10. The method of claim 9, wherein the first current pulse transmitted from the first input generates a second amorphous region in the second PCM cell.

11. The method of claim 9, further comprising: A second current pulse from the first input is delivered to the first PCM material to set the first PCM material in the first amorphous region of the first PCM unit.

12. The method according to claim 9, further comprising: A third current pulse from the first input is transmitted to the first PCM material to generate a third amorphous region in the first PCM unit; A fourth current pulse from the second input is delivered to the first PCM material to generate a fourth amorphous region in the second PCM unit; Measure the voltage drop across the first PCM unit and the second PCM unit; as well as The high voltage drop indicates that the memory device is storing a false value.

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