A free asynchronous single-photon avalanche focal plane readout circuit and photodetector

Abstract

This invention discloses a free-asynchronous single-photon avalanche focal plane readout circuit and photodetector, comprising a plurality of photosensitive pixel modules, an input clock pin for receiving an input clock signal, a reset pin for receiving a reset signal to reset the voltage of the photosensitive element to the operating voltage, a reset enable pin for receiving a reset enable signal to trigger the reset signal, a reference voltage input pin for receiving a reference voltage, a configuration pin for receiving a configuration data signal, a configuration clock signal, and a configuration enable signal, and a plurality of output pins electrically connected to the photosensitive pixel modules one-to-one for outputting pixels. Compared with the prior art, this invention can effectively improve the customizability of the device, enabling it to better meet application scenarios requiring high-speed optical response, full-field-of-view tracking, and low-power high-frame-rate readout.

Description

Technical Field

[0001] This invention relates to the field of photodetector technology, and in particular to a free asynchronous single-photon avalanche focal plane readout circuit and a photodetector. Background Technology

[0002] InGaAs free-asynchronous single-photon avalanche focal plane array is a focal plane array that performs continuous high-speed sampling and timing of photons. It mainly consists of an InGaAs APD photosensitive element array, a free-asynchronous readout circuit, and a cooling and heat dissipation package. It features multi-photon event timing and high photon flux, and is suitable for applications such as free-space optical communication and laser detection of non-cooperative targets. Typical application scenarios include inter-satellite laser communication interconnection, long-range laser communication for weapon systems, and high-speed long-range laser detection at distances of over 100 kilometers.

[0003] In a free asynchronous single-photon focal plane array, the free asynchronous readout circuit includes modules such as a pixel array, clock control, and data readout. The pixels operate in free mode, with all pixels starting to work asynchronously. When any avalanche event is detected, the pixels stop working and wait for a period of time (i.e., dead time) before resuming asynchronous work. The timing circuit and data readout module operate in synchronous mode, with a readout period shorter than the dead time, ensuring that all photosensitive avalanche events can be read.

[0004] However, existing free-asynchronous single-photon focal plane arrays, besides the readout circuit, are limited in their application by the detector's performance. First, spurious counting caused by detector backpulses results in a longer dead time, limiting the receiving rate. Excessive backpulses also increase noise and bit error rate. Second, fabrication process variations affect the photoelectric performance of photosensitive elements and generate excessive parasitic parameters, leading to high-biased photosensitive element array response and abnormal photosensitive element reset, thus affecting the consistency of individual photosensitive elements. Third, the readout power consumption is closely related to the readout rate and the amount of data read. Increased readout power consumption leads to larger chip power supplies and component cooling designs, thus hindering the development of devices towards higher frame rates, miniaturization, and integration. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a free asynchronous single-photon avalanche focal plane readout circuit and photodetector to solve the problems in the prior art, such as low receiving rate and high device noise due to excessive dead time caused by after-pulse pseudo-counting, excessive response deviation of photosensitive element array due to photosensitive element and parasitic parameter problems, abnormal photosensitive element reset, and limitations on miniaturization and integration.

[0006] To achieve the above objectives, one technical solution of the present invention provides a free asynchronous single-photon avalanche focal plane readout circuit, comprising a plurality of photosensitive pixel modules for connection to photosensitive elements, an input clock pin for receiving an input clock signal, a reset pin for receiving a reset signal to reset the voltage of the photosensitive element to the operating voltage, a reset enable pin for receiving a reset enable signal to trigger the reset signal, a reference voltage input pin for receiving a reference voltage, and a configuration pin for receiving a configuration data signal, a configuration clock signal, and a configuration enable signal, and a plurality of output pins electrically connected to each of the photosensitive pixel modules and for outputting pixels; the photosensitive pixel modules are also connected to an analog power input pin for receiving analog power and a digital power input pin for receiving digital power.

[0007] Furthermore, the photosensitive pixel module includes a quench / reset unit and a configuration register unit electrically connected to the quench / reset unit. The quench / reset unit is connected to the input clock pin, reset pin, reset enable pin, reference voltage input pin, analog power input pin, digital power input pin, and output pin. The quench / reset unit is used to compare the response voltage corresponding to the current generated by the response with the threshold correction voltage when the photosensitive element responds, and output a reset level after waiting for a preset dead time based on the comparison result. Then, the reset level is converted and output according to a preset pulse width to reset the photosensitive element. The configuration register unit is connected to the configuration pin and is used to configure the threshold correction voltage, preset dead time, and preset pulse width of the quench / reset unit according to the configuration data signal, configuration clock signal, and configuration enable signal.

[0008] Furthermore, the quenching / reset unit includes a quenching sub-circuit for quenching the photosensitive element based on the current flow generated by the photosensitive element's response, a limiting sub-circuit for maintaining the response voltage below the digital power supply, a detection sub-circuit for comparing the response voltage with a threshold correction circuit and outputting the comparison result, a first level conversion sub-circuit for level conversion of the comparison result and feeding it back to the quenching sub-circuit, a drive voltage correction sub-circuit for outputting a threshold correction voltage and a reset reference voltage based on a reference voltage, a photosensitive element dead time adjustment sub-circuit for waiting for the preset dead time based on the comparison result of the detection sub-circuit and then outputting a reset level, a pulse width modulation sub-circuit for pulse width modulation of the reset level according to a preset pulse width and outputting a reset pulse, a second level conversion sub-circuit for level conversion of the reset pulse, and a reset sub-circuit for resetting the photosensitive element based on the reset reference voltage and the reset pulse.

[0009] The quenching subcircuit and the second level conversion subcircuit are both connected to the analog power input pin. The quenching subcircuit is also connected to the reset enable pin. The detection subcircuit and the limiting subcircuit are both connected to the digital power input pin. The detection subcircuit is also connected to the output pin. The drive voltage correction subcircuit is connected to the reference voltage input pin. The photosensitive element dead time adjustment subcircuit is connected to the input clock pin. The reset subcircuit is connected to the reset pin. The drive voltage correction subcircuit, the photosensitive element dead time adjustment subcircuit, and the pulse width modulation subcircuit are all connected to the configuration register unit.

[0010] Furthermore, the quenching sub-circuit includes a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is connected to the reset enable pin. The source of the first MOS transistor is connected to the source of the second MOS transistor and then connected to the analog power input pin. The drain of the first MOS transistor is connected to the drain of the second MOS transistor and then connected to the photosensitive element. The drains of the first MOS transistor and the drain of the second MOS transistor are also connected to both the limiting sub-circuit and the reset sub-circuit. The gate of the second MOS transistor is connected to the first level conversion sub-circuit.

[0011] Furthermore, the configuration register unit is also used to output several register A group values ​​for configuring the threshold correction voltage;

[0012] The driving voltage correction sub-circuit includes several third MOS transistors connected in parallel, a fourth MOS transistor connected in series with the third MOS transistors, and a follower connected to the third and fourth MOS transistors. The drain of each third MOS transistor is connected to the reference voltage input pin. The gate of each third MOS transistor is connected to the configuration register unit and is connected to the value of register group A. The source of each third MOS transistor is connected to the drain of the fourth MOS transistor. The source of the third MOS transistor is also connected to the detection sub-circuit. The source and gate of the fourth MOS transistor are both grounded. The source of each third MOS transistor and the drain of the fourth MOS transistor are also connected to the non-inverting input terminal of the follower. The inverting input terminal of the follower is connected to the output terminal of the follower and then connected to the reset sub-circuit.

[0013] Furthermore, the configuration register unit is also used to output several register group B values ​​for configuring a preset dead time;

[0014] The photosensitive element dead time adjustment sub-circuit includes a first combinational logic unit and an N-bit counter connected to the first combinational logic unit. The input terminal of the register B group value of the first combinational logic unit is electrically connected to the configuration register unit and receives the values ​​of the plurality of register B groups. The clock signal input terminal of the N-bit counter is connected to the input clock pin. The counting signal output terminal of the N-bit counter is electrically connected to the counting signal input terminal of the first combinational logic unit. The reset level output terminal of the first combinational logic unit is electrically connected to the pulse width modulation sub-circuit. The N-bit counter is used to count according to the input clock signal. The first combinational logic unit is used to perform Boolean operation on the register B group value according to the count of the N-bit counter to determine the preset dead time and output the reset level to the pulse width modulation sub-circuit according to the comparison result of the detection sub-circuit.

[0015] Furthermore, the configuration register unit is also used to output several register C group values ​​for configuring a preset pulse width;

[0016] The pulse width modulation sub-circuit includes a second combinational logic unit, a plurality of fifth MOS transistors connected to the second combinational logic unit, an inverter connected to each of the fifth MOS transistors, and a NAND gate. The register C value input terminal of the second combinational logic unit is electrically connected to the configuration register unit and receives the values ​​of the plurality of register C groups. The second combinational logic unit has a second combinational logic value output terminal corresponding to each of the fifth MOS transistors. Each combinational logic value output terminal is electrically connected to the gate of each fifth MOS transistor. The source of each fifth MOS transistor is connected to a digital power input pin. The drain of each fifth MOS transistor is connected to the first control terminal of the inverter. The second control terminal of the inverter is grounded. The plurality of inverters are connected in series. The input terminal of the first inverter is connected to the photosensitive element dead time adjustment sub-circuit to receive the reset level, and the output terminal of the last inverter is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is connected to the photosensitive element dead time adjustment sub-circuit to receive the reset level. The output terminal of the NAND gate is connected to the second level conversion sub-circuit to output a reset pulse.

[0017] Furthermore, the reset sub-circuit includes a sixth MOS transistor and a seventh MOS transistor. The gate of the sixth MOS transistor is connected to the reset pin. The drains of the sixth and seventh MOS transistors are connected and then connected to the quenching sub-circuit. The sources of the sixth and seventh MOS transistors are connected and then connected to the drive voltage correction sub-circuit. The gate of the seventh MOS transistor is connected to the second level conversion sub-circuit.

[0018] Furthermore, the configuration pins include a configuration enable pin, a configuration data pin, and a configuration clock pin, and the configuration register unit has a register reset pin;

[0019] The configuration register unit includes a first multiplexer and a second multiplexer connected in sequence, a consistency configuration sub-circuit connected to the drive voltage correction sub-circuit, a dead time configuration sub-circuit connected to the photosensitive element dead time adjustment sub-circuit, and a pulse width configuration sub-circuit connected to the pulse width modulation sub-circuit. The enable terminals of the first multiplexer and the second multiplexer are both connected to the configuration enable terminal. The input terminal of the first multiplexer is connected to the configuration data terminal. The first output terminal of the first multiplexer is connected to the input terminal of the second multiplexer. The second output terminal of the first multiplexer is connected to the consistency configuration sub-circuit. The first output terminal of the second multiplexer is connected to the pulse width configuration sub-circuit. The second output terminal of the second multiplexer is connected to the dead time configuration sub-circuit. The consistency configuration sub-circuit, the dead time configuration sub-circuit, and the pulse width configuration sub-circuit are all connected to the configuration start and end terminals and the register reset pin.

[0020] To achieve the above objectives, another technical solution of the present invention provides a photodetector, including the free asynchronous single-photon avalanche focal plane readout circuit described above.

[0021] This invention reduces afterpulse by setting a low-threshold quenching sub-circuit and a photosensitive element dead time adjustment sub-circuit to achieve ultra-low afterpulse performance and thus improve the frame rate of the device. It also addresses the reset voltage signal by setting a threshold correction voltage generated by a drive voltage correction sub-circuit and a reset pulse generated by a pulse width modulation sub-circuit to achieve consistency adjustment and reset, thereby solving the reset anomaly problem caused by differences in photoelectric performance between photosensitive elements and excessive parasitic parameters due to diffusion inconsistency. Furthermore, by setting input clock pins, reset pins, and reset enable pins to connect input clock, reset, and enable signals to the photosensitive element pixel module, the voltage at both ends of the photosensitive element is reset when the enable signal is set to logic true under the drive of the corresponding clock signal. This allows the photons of the reset photosensitive element to be responded to, and the readout rate is controlled by controlling the readout channel, thereby achieving data volume and power consumption adjustment. This solves the problem of the inability to reduce the size and weight due to the number of pin interfaces and cooling heat dissipation in miniaturization, thus better meeting the application scenarios requiring high-speed optical response, full-field tracking, and low-power high-frame-rate readout. Attached Figure Description

[0022] Figure 1 This is a control block diagram of a free asynchronous single-photon avalanche focal plane readout circuit according to an embodiment of the present invention.

[0023] Figure 2 This is the control block diagram for the photosensitive pixel module.

[0024] Figure 3 This is the circuit schematic of the photosensitive pixel module.

[0025] Figure 4This is the circuit diagram of the dead time regulator circuit for the photosensitive element.

[0026] Figure 5 This is the circuit schematic of the pulse width modulation sub-circuit.

[0027] Figure 6 This is the timing diagram for the operation of the photosensitive pixel module.

[0028] Figure 7 This is a configuration diagram for the threshold correction voltage.

[0029] Figure 8 Configuration diagram for setting the dead time for photosensitive elements.

[0030] The diagrams in the instruction manual are labeled as follows:

[0031] Photosensitive element 1;

[0032] Photosensitive pixel module 2;

[0033] Quenching / Reset Unit 3, Quenching Sub-circuit 31, Limiting Sub-circuit 32, Limiter 321, Detection Sub-circuit 33, First Level Conversion Sub-circuit 34, Drive Voltage Correction Sub-circuit 35, Photosensitive Element Dead Time Adjustment Sub-circuit 36, First Combinational Logic Unit 361, N-bit Counter 362, Pulse Width Control Sub-circuit 37, Second Combinational Logic Unit 371, Inverter 372, NAND Gate 373, Second Level Conversion Sub-circuit 38, Reset Sub-circuit 39;

[0034] Configuration register unit 4, consistency configuration sub-circuit 41, dead time configuration sub-circuit 42, pulse width configuration sub-circuit 43. Detailed Implementation

[0035] The following detailed description illustrates the specific implementation method:

[0036] Example

[0037] Please refer to Figure 1 This is a control block diagram of a free-asynchronous single-photon avalanche focal plane readout circuit according to an embodiment of the present invention. The free-asynchronous single-photon avalanche focal plane readout circuit of this embodiment includes several photosensitive pixel modules 2 connected to photosensitive elements 1, and input clock pins, reset pins, reset enable pins, reference voltage input pins, configuration pins, and output pins connected to the photosensitive pixel modules 2. Each photosensitive pixel module 2 is correspondingly connected to an independent photosensitive element 1, so that when light shines on the photosensitive element 1 and causes photons in the photosensitive element 1 to respond and generate photogenerated signal charges, the photogenerated signal charges can be converted and read out. The output pins are configured one-to-one with the photosensitive pixel modules 2 to transmit the converted pixels from each photosensitive pixel module 2 to the outside of the readout circuit.

[0038] Each photosensitive pixel module 2 shares the same input clock pin, reset pin, reset enable pin, reference voltage input pin, and configuration pin. The input clock pin is used to receive an input clock signal to provide a clock signal for pixel readout. In this embodiment, the input clock signal acts on all photosensitive pixel modules 2 within the readout circuit, and can be configured using existing clock trees or driver networks. The reset pin is used to receive a reset signal to reset the voltage across photosensitive element 1 to its operating voltage. The reset enable pin is used to receive a reset enable signal to trigger a reset signal. In this embodiment, when the reset enable signal is set to logic "true," the reset signal is valid, thereby triggering the reset signal to act on photosensitive element 1, resetting the voltage across photosensitive element 1 to its operating voltage. The reference voltage input pin is used to receive a reference voltage for setting the reset signal. The configuration pin is used to access the configuration data signal, configuration clock signal, and configuration enable signal. In this embodiment, when the configuration enable signal is set to logic "true", the configuration data signal and configuration clock signal are valid, and data is serially written to each photosensitive pixel module 2, so that the photosensitive pixel module 2 can configure the threshold correction voltage, preset dead time, and preset pulse width.

[0039] In this embodiment, the photosensitive pixel module 2 is also connected to an analog power input pin and a digital power input pin for powering the photosensitive pixel module 2. Each photosensitive pixel module 2 shares the same analog power input pin and digital power input pin. The analog power input pin is used to input analog power to the photosensitive pixel module 2, and the digital power input pin is used to input digital power to the photosensitive pixel module 2, ensuring the normal operation of the photosensitive pixel module 2. Preferably, the readout circuit is also connected to an IO power input pin to power each output pin, ensuring that each output pin can read out the pixel.

[0040] Please refer to Figure 2The photosensitive pixel module 2 includes a quench / reset unit and a configuration register unit 4 electrically connected to the quench / reset unit. The quench / reset unit is connected to the photosensitive element 1 and is used to quench the after-pulse of the photosensitive element 1 and reset the voltage at both ends of the photosensitive element 1. The configuration register unit 4 is used to configure the operating parameters of the quench / reset unit (including threshold correction voltage, preset dead time, and preset pulse width, etc.) to realize the customization of the device. Specifically, the quenching / reset unit is connected to the input clock pin, reset pin, reset enable pin, reference voltage input pin, analog power input pin, digital power input pin, and output pin. When photosensitive element 1 receives a photon signal and generates a corresponding current flow, the quenching / reset unit compares the response voltage corresponding to the current generated by photosensitive element 1 with the configured threshold correction voltage. Based on the comparison result, it waits for a preset dead time and then outputs a reset level. The reset level is then converted and output according to a preset pulse width to reset photosensitive element 1. The configuration register unit 4 is connected to the configuration pin. The configuration register unit 4 is used to configure the threshold correction voltage, preset dead time, and preset pulse width of the quenching / reset unit according to the configuration data signal, configuration clock signal, and configuration enable signal.

[0041] The quenching / reset unit includes a quenching sub-circuit 31, a limiting sub-circuit 32, a detection sub-circuit 33, a first level conversion sub-circuit 34, a driving voltage correction sub-circuit 35, a photosensitive element dead time adjustment sub-circuit 36, a pulse width modulation sub-circuit 37, a second level conversion sub-circuit 38, and a reset sub-circuit 39. The driving voltage correction sub-circuit 35, the photosensitive element dead time adjustment sub-circuit 36, and the pulse width modulation sub-circuit 37 are all connected to the configuration register unit 4, so that when the configuration enable signal is set to logic "true", the configuration register unit 4 can serially write data to the driving voltage correction sub-circuit 35, the photosensitive element dead time adjustment sub-circuit 36, and the pulse width modulation sub-circuit 37 under the action of the configuration data signal and the configuration clock signal, thereby configuring the threshold driving voltage of the driving voltage correction sub-circuit 35, the preset dead time of the photosensitive element dead time adjustment sub-circuit 36, and the preset pulse width of the pulse width modulation sub-circuit 37. In this embodiment, the configuration register unit 4 can output several register A group values ​​to the drive voltage correction sub-circuit 35 to configure the threshold correction voltage, output several register B group values ​​to the photosensitive element dead time adjustment sub-circuit 36 ​​to configure the preset dead time, and output several register C group values ​​to the pulse width modulation sub-circuit 37 to configure the preset pulse width.

[0042] The quenching sub-circuit 31 is connected to the photosensitive element 1, and both the analog power input pin and the reset enable pin act on the quenching sub-circuit 31. The quenching sub-circuit 31 is used to quench the photosensitive element 1 according to the current flow generated by the response of the photosensitive element 1 when the reset enable pin is set to logic "true", so that the response voltage in the quenching sub-circuit 31 changes.

[0043] The limiting sub-circuit 32 is connected to the quenching sub-circuit 31, and the digital power input pin acts on the limiting sub-circuit 32. The limiting sub-circuit 32 is used for limiting the voltage between the quenching sub-circuit 31 and the photosensitive element 1 (i.e., the response voltage of the quenching sub-circuit 31) below the digital power supply. In this embodiment, the limiting sub-circuit 32 is implemented using electronic components, functional circuits, or modules with clamping capabilities, such as clampers, limiters 321, etc. These electronic components, functional circuits, and modules can all be implemented using existing technologies, and will not be described in detail in this embodiment.

[0044] The detection subcircuit 33 is connected to the limiting circuit, and its digital power input and output pins act on it. Simultaneously, the detection subcircuit 33 is also connected to the drive voltage correction subcircuit 35, with its reference voltage input pin acting on it. The drive voltage correction subcircuit 35 outputs a threshold correction voltage and a reset reference voltage based on the reference voltage, which are applied to the detection subcircuit 33 and the reset subcircuit 39, respectively. The detection subcircuit 33 compares the response voltage (i.e., the output voltage after limiting by the limiting subcircuit 32) with the threshold correction voltage generated by the drive voltage correction subcircuit 35, outputs the comparison result, and then outputs the result as either a digital power supply level indicating "true" or a threshold correction voltage level indicating "false" to the output pin and the photosensitive element dead time adjustment subcircuit 36 ​​to ensure accurate pixel readout. In this embodiment, the detection subcircuit 33 is implemented using a functional circuit or module capable of level comparison and outputting the comparison result as a logical "true" or "false" signal, such as a comparator or multiplexer.

[0045] The first level conversion sub-circuit 34 is connected between the detection sub-circuit 33 and the quenching sub-circuit 31. The first level conversion sub-circuit 34 is used to convert the comparison result of the detection sub-circuit 33 and feed it back to the quenching sub-circuit 31, thereby continuously triggering the quenching sub-circuit 31 to quench the photosensitive element 1 during the operation of the readout circuit. In this embodiment, the first level conversion sub-circuit 34 is implemented by a functional circuit or module capable of converting the level signal between two different voltage domains (such as high level, low level, etc.), such as a diode level conversion circuit, a transistor level conversion circuit, a level conversion chip, etc. These electronic components, functional circuits and modules can all be implemented using existing technologies, and will not be described in detail in this embodiment.

[0046] The photosensitive element dead time adjustment sub-circuit 36 ​​is connected to the detection sub-circuit 33 and the input clock pin is applied to the photosensitive element dead time adjustment sub-circuit 36. The photosensitive element dead time adjustment sub-circuit 36 ​​is used to wait for the preset dead time according to the comparison result of the detection sub-circuit 33 and then output a reset level to ensure that the subsequent pulse is lower than the specified value.

[0047] The pulse width modulation sub-circuit 37 is connected to the photosensitive element dead time adjustment sub-circuit 36. The pulse width modulation sub-circuit 37 is used to adjust the reset level output by the photosensitive element dead time adjustment sub-circuit 36 ​​according to the preset pulse width and output a reset pulse to reset the voltage at both ends of the photosensitive element 1.

[0048] The second level conversion sub-circuit 38 is connected between the pulse width modulation sub-circuit 37 and the reset sub-circuit 39, and the analog power input pin is applied to the second level conversion sub-circuit 38. The second level conversion sub-circuit 38 is used to convert the level of the reset pulse output by the pulse width modulation sub-circuit 37 and send it to the reset sub-circuit 39. In this embodiment, the second level conversion sub-circuit 38 is implemented using a functional circuit or module capable of converting level signals between two different voltage domains (such as high level, low level, etc.), such as a diode level conversion circuit, a transistor level conversion circuit, a level conversion chip, etc. These electronic components, functional circuits, and modules can all be implemented using existing technologies, and will not be described in detail in this embodiment.

[0049] The reset sub-circuit 39 is connected to the second level conversion sub-circuit 38, the quenching sub-circuit 31, and the driving voltage correction sub-circuit 35, and the reset pin acts on the reset sub-circuit 39. The photosensitive element 1 is connected between the reset sub-circuit 39 and the quenching sub-circuit 31. The reset sub-circuit 39 is used to reset the photosensitive element 1 according to the reset reference voltage generated by the driving voltage correction sub-circuit 35 and the reset pulse converted by the second level conversion sub-circuit 38, so that the voltage across the photosensitive element 1 is reset to the working voltage.

[0050] Please refer to Figure 3The quenching sub-circuit 31 includes a first MOSFET M1 and a second MOSFET M2. The gate of the first MOSFET M1 is connected to a reset enable pin, so that when the readout circuit starts working, the quenching sub-circuit 31 is triggered to start working by an externally input reset enable signal. The source of the first MOSFET M1 is connected to the source of the second MOSFET M2 and then connected to an analog power input pin to supply analog power to the first MOSFET M1 and the second MOSFET M2. The drain of the first MOSFET M1 is connected to the drain of the second MOSFET M2 and then connected to the photosensitive element 1. The drains of the first MOSFET M1 and the second MOSFET M2 are also connected to the limiting sub-circuit 32 and the reset sub-circuit 39. When the reset enable signal is set to logic "true", the photosensitive element 1 responds and generates current flow, which will cause the response voltage generated by the drains of the first MOSFET M1 and the second MOSFET M2 to change. The limiting sub-circuit 32 can limit the response voltage of the drains of the first MOSFET M1 and the second MOSFET M2, so that the response voltage is kept below the digital power supply voltage. The gate of the second MOSFET M2 is connected to the first level conversion sub-circuit 34. The first level conversion sub-circuit 34 can feed back the detection result of the detection sub-circuit 33 to the gate of the second MOSFET M2. During the operation of the readout circuit, the signal fed back to the gate of the second MOSFET M2 replaces the initial reset enable signal to trigger the quenching sub-circuit 31 to continue working. It is understood that in some other embodiments, the quenching sub-circuit 31 can also be implemented using other functional circuits or modules with pull-up capabilities.

[0051] The limiting sub-circuit 32 is preferably implemented using a limiter 321. The limiting sub-circuit 32 has a response voltage input terminal connected to the second MOS transistor M2 and a limiting voltage output terminal connected to the detection sub-circuit 33. Under the action of the digital power supply, the input response voltage is maintained below the digital power supply voltage and then output to the detection sub-circuit 33 via the limiting voltage output terminal. It is understood that in other embodiments, the limiting sub-circuit 32 may also be implemented using other electronic components, functional circuits, or modules with level clamping capabilities.

[0052] The detection sub-circuit 33 is preferably implemented using an output comparator A1, with a digital power supply applied to power it. The inverting input of the output comparator A1 is connected to the limiting voltage output of the limiter 321 to receive the response voltage; the non-inverting input of the output comparator A1 is connected to the driving voltage correction sub-circuit 35 to receive the threshold reference voltage; the output of the output comparator A1 is connected to the output pin, the first level conversion sub-circuit 34, and the photosensitive element dead time adjustment sub-circuit 36, enabling the output comparator A1 to compare the response voltage with the threshold correction circuit and output the comparison result. The comparison result is then output to the output pin and the photosensitive element dead time adjustment sub-circuit 36 ​​at the level of the digital power supply indicating a logical "true" value or the level of the threshold correction voltage indicating a logical "false" value. It is understood that in other embodiments, the detection sub-circuit 33 can also be implemented using other functional circuits or modules capable of level comparison and outputting the comparison result as a logical "true" or "false" value via an electrical signal.

[0053] The driving voltage correction sub-circuit 35 includes several third MOSFETs M3 connected in parallel, a fourth MOSFET M4 connected in series with the third MOSFETs M3, and a follower A2 connected to the third MOSFETs M3 and the fourth MOSFETs M4. The drain of each third MOSFET M3 is connected to the reference voltage input pin. The gate of each third MOSFET M3 is connected to the configuration register unit 4 and correspondingly connected to the values ​​in register group A, so as to set the threshold correction voltage and the reset reference voltage according to the reference voltage and the connected values ​​in register group A. The source of each third MOSFET M3 is connected to the drain of the fourth MOSFET M4. The source and gate of the fourth MOSFET M4 are both grounded. The source of each third MOSFET M3 is connected to the detection sub-circuit 33 (specifically, the non-inverting input of the output comparator A1) to output the threshold correction voltage to the detection sub-circuit 33. The source of each third MOSFET M3 is also connected to the reset sub-circuit 39 through the source follower A2 to output the reset reference voltage to the reset sub-circuit 39. Specifically, the source of each third MOS transistor M3 and the drain of the fourth MOS transistor M4 are connected to the non-inverting input of the follower A2. The inverting input of the follower A2 is connected to the output of the follower A2 and then connected to the reset circuit 39 to achieve voltage following, thereby transmitting the reset reference voltage to the reset circuit 39.

[0054] Please refer to Figure 4The photosensitive element dead time adjustment sub-circuit 36 ​​includes a first combinational logic unit 361 and an N-bit counter 362 connected to the first combinational logic unit 361. The register B group value input terminal of the first combinational logic unit 361 is electrically connected to the configuration register unit 4 and receives the values ​​of several register B groups. The first combinational logic unit 361 performs logical operations on each register B group value to obtain the corresponding reset level. The reset level output terminal of the first combinational logic unit 361 is electrically connected to the pulse width modulation sub-circuit 37 to transmit the reset low level to the pulse width modulation sub-circuit 37. The clock signal input terminal of the N-bit counter 362 is connected to the input clock pin to receive the input clock signal. The counting signal output terminal of the N-bit counter 362 is electrically connected to the counting signal input terminal of the first combinational logic unit 361 to count according to the input clock signal. Under the control of the input clock signal, the first combinational logic unit 361 can perform Boolean operations on the register B group values ​​to determine the preset dead time and output the reset level to the pulse width modulation sub-circuit 37 based on the comparison result of the detection sub-circuit 33. In this embodiment, the first combinational logic unit 361 is implemented using a circuit or module with Boolean operation functionality; the N-bit counter 362 is implemented using synchronous, asynchronous, digital, and analog counter function circuits and modules with clock input control.

[0055] Please refer to Figure 5The pulse width modulation sub-circuit 37 includes a second combinational logic unit 371, a plurality of fifth MOS transistors M5 connected to the second combinational logic unit 371, an inverter 372 connected to each of the fifth MOS transistors M5, and a NAND gate 373. The register C value input terminal of the second combinational logic unit 371 is electrically connected to the configuration register unit 4 and receives the values ​​of the plurality of register C groups. The second combinational logic unit 371 has a second combinational logic value output terminal corresponding to each of the fifth MOS transistors M5, and each combinational logic value output terminal is electrically connected to the gate of the fifth MOS transistor M5. The second combinational logic unit 371 is used to perform logical operations on the values ​​of the plurality of register C groups and output them to the corresponding fifth MOS transistor M5. The source of each fifth MOSFET M5 is connected to the digital power input pin, and the drain of each fifth MOSFET M5 is connected to the first control terminal of the inverter 372. The second control terminal of the inverter 372 is grounded. Several inverters 372 are connected in series, and the input terminal of the first inverter 372 is connected to the photosensitive element dead time adjustment sub-circuit 36 ​​to access the reset level. The output terminal of the last inverter 372 is connected to the first input terminal of the NAND gate 373. The second input terminal of the NAND gate 373 is connected to the photosensitive element dead time adjustment sub-circuit 36 ​​to access the reset level. The output terminal of the NAND gate 373 is connected to the second level conversion sub-circuit 38 to output the reset pulse. After the second combinational logic unit 371 performs combinational logic operations on the input register C group values, it outputs corresponding combinational logic values ​​to adjust the gate voltage of the fifth MOSFET M5. Furthermore, by turning the fifth MOSFET M5 on and off, it controls the current flowing through each stage of the inverters 372 to adjust the delay of the signal edge, thereby achieving the conversion from a reset level signal to a pulse output and the control of the pulse width. In this embodiment, the second combinational logic unit 371 is implemented using a circuit or module with Boolean operation functionality.

[0056] Please return to the reference. Figure 3The reset sub-circuit 39 includes a sixth MOSFET M6 and a seventh MOSFET M7. The gate of the sixth MOSFET M6 is connected to a reset pin so that when the readout circuit starts working, an externally input reset signal triggers the reset sub-circuit 39 to reset the voltage across the photosensitive element 1 to the operating voltage. The drains of the sixth MOSFET M6 and the seventh MOSFET M7 are connected to the quenching sub-circuit 31 (specifically, the drains of the first MOSFET M1 and the second MOSFET M2). The sources of the sixth MOSFET M6 and the seventh MOSFET M7 are connected to the drive voltage correction sub-circuit 35 (specifically, the output of the follower A2). The drive voltage correction sub-circuit 35 sets the source voltages of the sixth MOSFET M6 and the seventh MOSFET M7 to the reset reference voltage, thereby making the drain voltages of the sixth MOSFET M6 and the seventh MOSFET M7 equal to their own source voltages under the action of the reset signal, thus realizing the reset of the photosensitive element 1. The gate of the seventh MOS transistor M7 is connected to the second level conversion sub-circuit 38, so that the reset pulse output by the pulse width modulation sub-circuit 37 is pulse-width modulated and applied to the gate of the seventh MOS transistor M7. Then, during the operation of the readout circuit, the signal fed back to the gate of the seventh MOS transistor M7 replaces the initial reset signal to reset the voltage across the photosensitive element 1. It is understood that in some other embodiments, the reset sub-circuit 39 can also be implemented using other functional circuits or modules with pull-down capabilities.

[0057] The configuration pins include a configuration enable pin, a configuration data pin, and a configuration clock pin, which are used to connect the configuration enable signal, the configuration data signal, and the configuration clock signal to the configuration register unit 4, respectively; the configuration register unit 4 has a register reset pin, which is used to connect the register reset signal to the configuration register unit 4.

[0058] The configuration register unit 4 includes a first multiplexer D1 and a second multiplexer D2 connected in sequence, a consistency configuration sub-circuit 41 connected to the drive voltage correction sub-circuit 35, a dead time configuration sub-circuit 42 connected to the photosensitive element dead time adjustment sub-circuit 36, and a pulse width configuration sub-circuit 43 connected to the pulse width modulation sub-circuit 37. The first multiplexer D1 and the second multiplexer D2 are used to select the corresponding consistency configuration sub-circuit 41, dead time configuration sub-circuit 42, and pulse width configuration sub-circuit 43 based on the configuration clock signal when the configuration enable signal at the configuration enable terminal is set to logic "true" to input configuration data signals into the consistency configuration sub-circuit 41, dead time configuration sub-circuit 42, and pulse width configuration sub-circuit 43.

[0059] Specifically, the enable terminals (i.e., the input terminals of the first multiplexer D1 and the second multiplexer D2) are both connected to the configuration enable terminal to receive the configuration enable signal. The input terminal of the first multiplexer D1 is connected to the configuration data terminal, the first output terminal of the first multiplexer D1 is connected to the input terminal of the second multiplexer D2, the second output terminal of the first multiplexer D1 is connected to the consistency configuration sub-circuit 41, the first output terminal of the second multiplexer D2 is connected to the pulse width configuration sub-circuit 43, and the second output terminal of the second multiplexer D2 is connected to the dead time configuration sub-circuit 42, so as to input configuration data into the consistency configuration sub-circuit 41, the dead time configuration sub-circuit 42, and the pulse width configuration sub-circuit 43 when the configuration enable signal is logically "true". The consistency configuration sub-circuit 41, dead time configuration sub-circuit 42, and pulse width configuration sub-circuit 43 are all connected to the configuration start and end terminals and the register reset pin, so as to reset the consistency configuration sub-circuit 41, dead time configuration sub-circuit 42, and pulse width configuration sub-circuit 43 when an external register reset signal is applied.

[0060] In this embodiment, the consistency configuration sub-circuit 41 includes several first registers R1 arranged in parallel. The Clk pin of each first register R1 is connected to the configuration clock terminal, and the Reset pin is connected to the register reset pin, so as to input the configuration clock signal and the register reset signal to each first register R1. The number of first registers R1 is the same as the number of third MOS transistors M3. The data of each first register R1 corresponds to the output of a register A group value to the corresponding third MOS transistor M3, so as to configure the drive voltage correction sub-circuit 35. Specifically, the input D pin of the first register R1 at the beginning is connected to the "1" output terminal of the first multiplexer D1 (i.e., the second output terminal of the first multiplexer D1), and the output Q pin of the first register R1 is connected to the gate of the third MOS transistor M3 at the beginning of the drive voltage correction circuit 35 to output a register A group value to the corresponding third MOS transistor M3. At the same time, the output Q pin of the first register R1 at the beginning is also connected to the input D pin of the next first register R1 (the second first register R1), and the output Q pin of the second first register R1 is connected to the gate of the second third MOS transistor M3 of the drive voltage correction circuit 35 to output a register A group value to the corresponding third MOS transistor M3. At the same time, the output Q pin of the second first register R1 is also connected to the input D pin of the next first register R1 (i.e., the third first register R1), and so on.

[0061] The dead time configuration sub-circuit 42 includes several second registers R2 arranged in parallel. The Clk pin of each second register R2 is connected to the configuration clock terminal, and the Reset pin is connected to the register reset pin, so as to input the configuration clock signal and the register reset signal to each second register R2. The second registers R2 are connected to the first combinational logic 361. The data of each second register R2 corresponds to the output of a register B group value to the first combinational logic 361 to configure the photosensitive element dead time adjustment sub-circuit 36. Specifically, the input D pin of the first-end second register R2 is connected to the "1" output of the second multiplexer D2 (i.e., the second output of the second multiplexer D2), and the output Q pin of the second register R2 is connected to the first combinational logic 361 of the photosensitive element dead time adjustment sub-circuit 36 ​​to output a register B group value to the first combinational logic 361. At the same time, the output Q pin of the first-end second register R2 is also connected to the input D pin of the next second register R2 (the second second register R2), and the output Q pin of the second second register R2 is connected to the first combinational logic 361 to output a register B group value to the first combinational logic 361. At the same time, the output Q pin of the second second register R2 is also connected to the input D pin of the next second second register R2 (i.e., the third second register R2), and so on.

[0062] The pulse width configuration sub-circuit 43 includes several third registers R3 arranged in parallel. The Clk pin of each third register R3 is connected to the configuration clock terminal, and the Reset pin is connected to the register reset pin, so as to input the configuration clock signal and the register reset signal to each third register R3. The third registers R3 are connected to the second combinational logic 371. The data of each third register R3 corresponds to the output of a register C group value to the second combinational logic 371 to configure the pulse width control sub-circuit 37. Specifically, the input D pin of the first-end third register R3 is connected to the "0" output of the second multiplexer D2 (i.e., the first output of the second multiplexer D2), and the output Q pin of the third register R3 is connected to the second combinational logic 371 of the pulse width modulation sub-circuit 37 to output a register C group value to the second combinational logic 371. At the same time, the output Q pin of the first-end third register R3 is also connected to the input D pin of the next third register R3 (the second third register R3), and the output Q pin of the second third register R3 is connected to the second combinational logic 371 to output a register C group value to the second combinational logic 371. At the same time, the output Q pin of the second third register R3 is also connected to the input D pin of the next third register R3 (i.e., the third third register R3), and so on.

[0063] The working principle of this embodiment:

[0064] Please refer to Figures 6 to 8 In this embodiment, the free asynchronous single-photon avalanche focal plane readout circuit, according to the working timing of the readout circuit, under the control of the configuration enable signal vector at the configuration enable terminal <0:m>, writes the configuration data signal and configuration clock signal into the first register R1 to configure the drive voltage correction sub-circuit 35, writes them into the second register R2 to configure the photosensitive element dead time adjustment sub-circuit 36, and writes them into the third register R3 to configure the pulse width modulation sub-circuit 37, thereby completing the configuration of the threshold correction voltage, reset reference voltage, preset dead time, and preset pulse width.

[0065] After configuration, each of the third MOSFETs M3 simultaneously sets the source voltages of the sixth MOSFET M6 and the seventh MOSFET M7, as well as the voltage at the reference voltage port (i.e., the non-inverting input) of the output comparator A1, based on the reference voltage and the value of register group A. A reset enable signal is input to the reset enable pin, causing the circuit to start working. At this time, the photosensitive element 1 responds, generating current flow that changes the drain voltage of the first MOSFET M1 to produce a response voltage. The limiter 321 limits the response voltage, keeping the drain voltage of the second MOSFET M4 below the digital power supply voltage and outputting it to the output comparator A1. The output comparator A1 compares the output voltage of the limiter 321 with the threshold correction voltage, and outputs the comparison result as either a digital power supply level representing logic "true" or a threshold correction voltage representing logic "false". The output is sent to the output pin and the photosensitive element dead time adjustment sub-circuit 36. When the photosensitive element dead time adjustment sub-circuit 36 ​​receives the logic "true" signal representing the response of photosensitive element 1, it generates a reset level after a preset dead time and transmits it to the pulse width adjustment sub-circuit. After receiving the reset level, the pulse width adjustment sub-circuit 37 adjusts the reset level with a preset pulse width and outputs a reset pulse. After being converted by the second level conversion sub-circuit 38, the pulse pulse is output to the gate of the seventh MOS transistor M7, so that the source voltage and drain voltage of the seventh MOS transistor M7 are equal, thereby completing the reset of photosensitive element 1.

[0066] This embodiment of the free-asynchronous single-photon avalanche focal plane readout circuit proposes a low-afterpulse customizable free-asynchronous single-photon avalanche focal plane readout circuit. By setting a low-threshold quenching sub-circuit 31 and a photosensitive element dead-time adjustment sub-circuit 36, it solves the device performance and reliability problems caused by detector inconsistency in practical applications of free-asynchronous single-photon focal planes. It addresses the issues of dead-time-frame-frequency mutual constraints, data readout-power balance, threshold correction voltage generated by the driving voltage correction sub-circuit 35, and reset pulse generated by the pulse width modulation sub-circuit 37, which are all addressed by setting input clock pins, reset pins, and reset enable pins to connect input clock, reset signals, and enable signals to the photosensitive element pixel module 2.

[0067] To achieve the above objectives, another embodiment of the present invention provides a photodetector, which includes the free asynchronous single-photon avalanche focal plane readout circuit described above, to realize the reset of photosensitive element 1. Of course, it is understood that the photodetector also includes other necessary structures such as a photosensitive region and a transfer register, all of which can be implemented using existing technologies and will not be elaborated upon in this embodiment.

Claims

1. A free asynchronous single-photon avalanche focal plane readout circuit, characterized in that, The system includes several photosensitive pixel modules for connection to photosensitive elements, an input clock pin for receiving an input clock signal, a reset pin for receiving a reset signal to reset the voltage of the photosensitive element to the operating voltage, a reset enable pin for receiving a reset enable signal to trigger the reset signal, a reference voltage input pin for receiving a reference voltage, and a configuration pin for receiving a configuration data signal, a configuration clock signal, and a configuration enable signal, as well as several output pins electrically connected to each photosensitive pixel module for outputting pixels. Each photosensitive pixel module is also connected to an analog power input pin for receiving analog power and a digital power input pin for receiving digital power. The photosensitive pixel module includes a quench / reset unit and a configuration register unit electrically connected to the quench / reset unit. The quench / reset unit is connected to the input clock pin, reset pin, reset enable pin, reference voltage input pin, analog power input pin, digital power input pin, and output pin. The quench / reset unit is used to compare the response voltage corresponding to the current generated by the photosensitive element with the threshold correction voltage when the photosensitive element responds, and output a reset level after waiting for a preset dead time based on the comparison result. Then, the reset level is converted and output according to a preset pulse width to reset the photosensitive element. The configuration register unit is connected to the configuration pin and is used to configure the threshold correction voltage, preset dead time, and preset pulse width of the quench / reset unit according to the configuration data signal, configuration clock signal, and configuration enable signal. The quenching / reset unit includes a quenching sub-circuit for quenching the photosensitive element based on the current flow generated by the photosensitive element's response, a limiting sub-circuit for maintaining the response voltage below the digital power supply, a detection sub-circuit for comparing the response voltage with a threshold correction voltage and outputting the comparison result, a first level conversion sub-circuit for level conversion of the comparison result and feeding it back to the quenching sub-circuit, a drive voltage correction sub-circuit for outputting a threshold correction voltage and a reset reference voltage based on a reference voltage, a photosensitive element dead time adjustment sub-circuit for waiting for the preset dead time based on the comparison result of the detection sub-circuit and then outputting a reset level, a pulse width modulation sub-circuit for pulse width modulation of the reset level according to a preset pulse width and outputting a reset pulse, a second level conversion sub-circuit for level conversion of the reset pulse, and a reset sub-circuit for resetting the photosensitive element based on the reset reference voltage and the reset pulse. The quenching subcircuit and the second level conversion subcircuit are both connected to the analog power input pin. The quenching subcircuit is also connected to the reset enable pin. The detection subcircuit and the limiting subcircuit are both connected to the digital power input pin. The detection subcircuit is also connected to the output pin. The drive voltage correction subcircuit is connected to the reference voltage input pin. The photosensitive element dead time adjustment subcircuit is connected to the input clock pin. The reset subcircuit is connected to the reset pin. The drive voltage correction subcircuit, the photosensitive element dead time adjustment subcircuit, and the pulse width modulation subcircuit are all connected to the configuration register unit.

2. The free asynchronous single-photon avalanche focal plane readout circuit according to claim 1, characterized in that, The quenching sub-circuit includes a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is connected to the reset enable pin. The source of the first MOS transistor is connected to the source of the second MOS transistor and then connected to the analog power input pin. The drain of the first MOS transistor is connected to the drain of the second MOS transistor and then connected to the photosensitive element. The drains of the first MOS transistor and the drain of the second MOS transistor are also connected to both the limiting sub-circuit and the reset sub-circuit. The gate of the second MOS transistor is connected to the first level conversion sub-circuit.

3. The free asynchronous single-photon avalanche focal plane readout circuit according to claim 1, characterized in that, The configuration register unit is also used to output several register A group values ​​for configuring the threshold correction voltage; The driving voltage correction sub-circuit includes several third MOS transistors connected in parallel, a fourth MOS transistor connected in series with the third MOS transistors, and a follower connected to the third and fourth MOS transistors. The drain of each third MOS transistor is connected to the reference voltage input pin. The gate of each third MOS transistor is connected to the configuration register unit and is connected to the value of register group A. The source of each third MOS transistor is connected to the drain of the fourth MOS transistor. The source of the third MOS transistor is also connected to the detection sub-circuit. The source and gate of the fourth MOS transistor are both grounded. The source of each third MOS transistor and the drain of the fourth MOS transistor are also connected to the non-inverting input terminal of the follower. The inverting input terminal of the follower is connected to the output terminal of the follower and then connected to the reset sub-circuit.

4. The free asynchronous single-photon avalanche focal plane readout circuit according to claim 1, characterized in that, The configuration register unit is also used to output several register group B values ​​for configuring preset dead time; The photosensitive element dead time adjustment sub-circuit includes a first combinational logic unit and an N-bit counter connected to the first combinational logic unit. The input terminal of the register B group value of the first combinational logic unit is electrically connected to the configuration register unit and receives the values ​​of the plurality of register B groups. The clock signal input terminal of the N-bit counter is connected to the input clock pin. The counting signal output terminal of the N-bit counter is electrically connected to the counting signal input terminal of the first combinational logic unit. The reset level output terminal of the first combinational logic unit is electrically connected to the pulse width modulation sub-circuit. The N-bit counter is used to count according to the input clock signal. The first combinational logic unit is used to perform Boolean operation on the register B group value according to the count of the N-bit counter to determine the preset dead time and output the reset level to the pulse width modulation sub-circuit according to the comparison result of the detection sub-circuit.

5. The free asynchronous single-photon avalanche focal plane readout circuit according to claim 1, characterized in that, The configuration register unit is also used to output several register C group values ​​for configuring the preset pulse width; The pulse width modulation sub-circuit includes a second combinational logic unit, a plurality of fifth MOS transistors connected to the second combinational logic unit, an inverter connected to each of the fifth MOS transistors, and a NAND gate. The register C value input terminal of the second combinational logic unit is electrically connected to the configuration register unit and receives the values ​​of the plurality of register C groups. The second combinational logic unit has a second combinational logic value output terminal corresponding to each of the fifth MOS transistors. Each combinational logic value output terminal is electrically connected to the gate of each fifth MOS transistor. The source of each fifth MOS transistor is connected to a digital power input pin. The drain of each fifth MOS transistor is connected to the first control terminal of the inverter. The second control terminal of the inverter is grounded. The plurality of inverters are connected in series. The input terminal of the first inverter is connected to the photosensitive element dead time adjustment sub-circuit to receive the reset level, and the output terminal of the last inverter is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is connected to the photosensitive element dead time adjustment sub-circuit to receive the reset level. The output terminal of the NAND gate is connected to the second level conversion sub-circuit to output a reset pulse.

6. The free asynchronous single-photon avalanche focal plane readout circuit according to claim 1, characterized in that, The reset sub-circuit includes a sixth MOS transistor and a seventh MOS transistor. The gate of the sixth MOS transistor is connected to the reset pin. The drains of the sixth and seventh MOS transistors are connected and then connected to the quenching sub-circuit. The sources of the sixth and seventh MOS transistors are connected and then connected to the drive voltage correction sub-circuit. The gate of the seventh MOS transistor is connected to the second level conversion sub-circuit.

7. The free asynchronous single-photon avalanche focal plane readout circuit according to claim 1, characterized in that, The configuration pins include a configuration enable pin, a configuration data pin, and a configuration clock pin; the configuration register unit has a register reset pin. The configuration register unit includes a first multiplexer and a second multiplexer connected in sequence, a consistency configuration sub-circuit connected to the drive voltage correction sub-circuit, a dead time configuration sub-circuit connected to the photosensitive element dead time adjustment sub-circuit, and a pulse width configuration sub-circuit connected to the pulse width modulation sub-circuit. The enable terminals of the first multiplexer and the second multiplexer are both connected to the configuration enable terminal. The input terminal of the first multiplexer is connected to the configuration data terminal. The first output terminal of the first multiplexer is connected to the input terminal of the second multiplexer. The second output terminal of the first multiplexer is connected to the consistency configuration sub-circuit. The first output terminal of the second multiplexer is connected to the pulse width configuration sub-circuit. The second output terminal of the second multiplexer is connected to the dead time configuration sub-circuit. The consistency configuration sub-circuit, the dead time configuration sub-circuit, and the pulse width configuration sub-circuit are all connected to the configuration clock terminal and the register reset pin.

8. A photodetector, characterized in that, Includes the free asynchronous single-photon avalanche focal plane readout circuit as described in any one of claims 1 to 7.

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