A frequency detection circuit and electronic device

Abstract

This application discloses a frequency detection circuit and an electronic device. The frequency detection circuit includes a control signal generation circuit, a charging / discharging circuit, and a detection voltage generation circuit. The control signal generation circuit generates a first control signal corresponding to the clock signal to be detected and a second control signal delayed relative to the first control signal. The charging / discharging circuit charges and discharges under the control of the second control signal, wherein the charging / discharging circuit discharges during the pulse width when the second control signal is high and charges during the pulse width when the second control signal is low. The detection voltage generation circuit samples the voltage at the output terminal of the charging / discharging circuit before discharge during the pulse width when the first control signal is high, and outputs the corresponding first voltage signal. Through this method, the frequency of a clock signal can be detected.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a frequency detection circuit and electronic device. Background Technology

[0002] Clock signals are frequently used in electronic devices. They are typically used in synchronization circuits, acting as timers to ensure that related electronic components operate synchronously. In some applications, frequency detection of the clock signal is required. Generally, to accurately detect the specific frequency value of the clock signal, a relatively complex circuit design is necessary.

[0003] However, in other application scenarios, it is often not necessary to detect a specific frequency value, but rather to detect changes in the frequency of the clock signal. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a frequency detection circuit and electronic device capable of detecting the frequency of a clock signal.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a frequency detection circuit, the frequency detection circuit comprising: a control signal generation circuit, the control signal generation circuit being used to receive a clock signal to be detected, and to generate a first control signal corresponding to the clock signal to be detected and a second control signal delayed relative to the first control signal; a charging and discharging circuit, the charging and discharging circuit being coupled to the control signal generation circuit, and charging and discharging under the control of the second control signal, wherein the charging and discharging circuit discharges during the pulse width when the second control signal is at a high level, and charges during the pulse width when the second control signal is at a low level; and a detection voltage generation circuit, the detection voltage generation circuit being coupled to the output terminal of the charging and discharging circuit and the control signal generation circuit, wherein during the pulse width when the first control signal is at a high level, the voltage at the output terminal of the charging and discharging circuit is sampled to the voltage value before discharge, so as to output a corresponding first voltage signal.

[0006] Among them, the lower the frequency of the clock signal to be detected, the higher the voltage value of the first voltage signal.

[0007] The frequency of the second control signal is the same as the frequency of the clock signal to be detected, and the pulse width of the second control signal remains unchanged when it is high.

[0008] The charging and discharging circuit includes: a power supply; a first capacitor, the first end of which is coupled to the power supply and the second end of which is grounded; and a first switch, the first end of which is coupled to the first end of the first capacitor and the second end of which is grounded, and the control terminal of the first switch receives a second control signal.

[0009] The voltage generation circuit further includes: a second switch, the first end of which is coupled to the first end of the first capacitor, and the control end of the second switch receives a first control signal; and a second capacitor, the first end of which is coupled to the second end of the second switch and is used to output a first voltage signal, and the second end of the second capacitor is grounded.

[0010] The voltage generation circuit further includes: a third switch, the first end of which is coupled to the first end of the second capacitor, and the control end of the third switch receives a second control signal; and a third capacitor, the first end of which is coupled to the second end of the third switch and is used to output a first voltage signal, and the second end of the third capacitor is grounded.

[0011] The first switch, the second switch, and the third switch are implemented using nMOS transistors, or transmission gates composed of nMOS transistors and pMOS transistors.

[0012] The control signal generation circuit includes: a first delay unit, the input of which is used to receive the clock signal to be detected; a first inverting unit, the input of which is coupled to the output of the first delay unit; an AND gate unit, the first input of which is used to receive the clock signal to be detected, the second input of which is coupled to the output of the first inverting unit, and the output of which outputs a first control signal; and a second delay unit, the input of which is coupled to the output of the AND gate unit, and the output of which outputs a second control signal.

[0013] The frequency detection circuit further includes a comparison circuit coupled to a detection voltage generation circuit, used to compare the first voltage signal with at least one preset reference voltage signal to obtain a corresponding comparison result signal.

[0014] The frequency detection circuit further includes a low-dropout linear regulator, which is coupled to the output of the comparison circuit and is used to generate a matching second voltage signal based on the comparison result signal.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide an electronic device, which includes the frequency detection circuit as described above.

[0016] The beneficial effects of this application are as follows: Unlike the prior art, the frequency detection circuit provided in this application includes a control signal generation circuit, a charging / discharging circuit, and a detection voltage generation circuit. The control signal generation circuit is used to receive the clock signal to be detected and generate a first control signal corresponding to the clock signal to be detected and a second control signal delayed relative to the first control signal. The charging / discharging circuit is coupled to the control signal generation circuit and charges and discharges under the control of the second control signal. During the pulse width when the second control signal is high, the charging / discharging circuit discharges and charges when the second control signal is low. The detection voltage generation circuit is coupled to the output terminal of the charging / discharging circuit and the control signal generation circuit. During the pulse width when the first control signal is high, the voltage at the output terminal of the charging / discharging circuit is sampled to the voltage value before discharge to output a corresponding first voltage signal. In this embodiment, the corresponding voltage signal is generated based on the frequency of the input clock so that the frequency of the clock signal can be determined by detecting the voltage value of the voltage signal. Furthermore, in scenarios where it is not necessary to obtain the precise frequency of the clock signal but only to determine its frequency, judging the magnitude of the generated voltage signal can intuitively reflect the frequency of the clock signal. Moreover, the voltage signal can be directly used as the input of subsequent circuits to represent the clock signal frequency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the structure of the first embodiment of the frequency detection circuit provided in this application; Figure 2 This is a schematic diagram of the structure of the second embodiment of the frequency detection circuit provided in this application; Figure 3 This is a waveform diagram of the signals at each node in the second embodiment; Figure 4 This is a schematic diagram of the structure of the third embodiment of the frequency detection circuit provided in this application; Figure 5 This is a waveform diagram of the signals at each node in the third embodiment; Figure 6 This is a schematic diagram of the structure of the fourth embodiment of the frequency detection circuit provided in this application; Figure 7 This is a waveform diagram of the signals at each node in the fourth embodiment; Figure 8 This is a schematic diagram of the duty cycle adjustment circuit in one embodiment; Figure 9 This is a schematic diagram of the duty cycle adjustment circuit in another embodiment; Figure 10 It is a graph showing the relationship between the on-resistance of the transmission gate and the voltage at the control terminal. Figure 11 This is a schematic diagram of the fifth embodiment of the frequency detection circuit provided in this application; Figure 12 This is a schematic diagram of the structure of a delay-locked loop circuit in one embodiment; Figure 13 This is a schematic diagram of the delay circuit 910 in one embodiment; Figure 14 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] See Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the frequency detection circuit provided in this application. The frequency detection circuit 100 includes a control signal generation circuit 110, a charging and discharging circuit 120, and a detection voltage generation circuit 130.

[0020] The control signal generation circuit 110 is used to receive the clock signal CK to be detected. in Generate the clock signal CK to be detected. in The corresponding first control signal CK P and relative to the first control signal CK P Delayed second control signal CK PD .

[0021] The charging / discharging circuit 120 is coupled to the control signal generation circuit 110, and in the second control signal CK PD Under controlled charging and discharging, wherein: the second control signal CK PD During the high-level pulse width, the charging / discharging circuit 120 discharges, as indicated by the second control signal CK. PD During the low-level period, the charging / discharging circuit 120 is charged.

[0022] The voltage generation circuit 130 is coupled to the output terminal of the charge / discharge circuit 120 and the control signal generation circuit 110, and is connected to the first control signal CK. PDuring the high-level pulse width, the voltage signal ND1 at the output terminal of the charging / discharging circuit 120 is sampled to the voltage value before discharge, so as to output the first voltage signal V1.

[0023] In a further embodiment, the clock signal to be detected is CK in The lower the frequency, the greater the voltage value of the first voltage signal V1.

[0024] In a further embodiment, the second control signal CK PD The frequency and the clock signal CK to be detected in The frequencies are the same; the second control signal CK PD Since the pulse width remains unchanged at a high level, the charging / discharging circuit 120 operates in response to the second control signal CK. PD The discharge time within one clock cycle is fixed, while the charging time is determined by the second control signal CK. PD The length of the low-level signal is determined by the second control signal CK. PD The period length determines the second control signal CK. PD The lower the frequency and the longer the period, the longer the charging time of the charging and discharging circuit 120, and the higher the voltage of the output voltage signal ND1. Therefore, the voltage value of the output voltage signal ND1 of the charging and discharging circuit 120 can reflect the clock signal CK to be detected. in The frequency magnitude. Because the voltage signal ND1 at the output of the charging / discharging circuit 120 forms a sawtooth pattern due to the periodic charging and discharging of the charging / discharging circuit 120, the voltage generation circuit 130 further samples the voltage signal ND1. ND1 is determined by the first control signal CK. P During the high-level pulse width, the voltage signal ND1 is sampled, and the sampled voltage signal is output as the first voltage signal V1, due to the first control signal CK. P The high-level pulse ratio of the second control signal CK PD The high-level pulse is early, ensuring that the sampling time point is before the discharge operation of each cycle of the charging and discharging circuit 120. The sampled voltage signal reflects the voltage value reached in each charging operation and is output as the first voltage signal V1. Therefore, the magnitude of V1 reflects the second control signal CK. PD The length of the period (frequency) reflects the clock signal CK to be detected. in The frequency.

[0025] Unlike existing technologies, the frequency detection circuit provided in this embodiment includes a control signal generation circuit, a charging / discharging circuit, and a detection voltage generation circuit. The control signal generation circuit receives a clock signal to be detected and generates a first control signal corresponding to the clock signal and a second control signal delayed relative to the first control signal. The charging / discharging circuit is coupled to the control signal generation circuit and charges / discharges under the control of the second control signal. During the pulse width when the second control signal is high, the charging / discharging circuit discharges, and during the pulse width when the second control signal is low, the charging / discharging circuit charges. The detection voltage generation circuit is coupled to the output terminal of the charging / discharging circuit and the control signal generation circuit. During the pulse width when the first control signal is high, it samples the voltage at the output terminal of the charging / discharging circuit before discharge to output a corresponding first voltage signal. In this way, this embodiment generates a corresponding voltage signal based on the frequency of the input clock, so that the frequency of the clock signal can be determined by detecting the voltage value of the voltage signal. Furthermore, in scenarios where it is not necessary to obtain the precise frequency of the clock signal but only to determine its frequency, judging the magnitude of the generated voltage signal can intuitively reflect the frequency of the clock signal. Moreover, the voltage signal can be directly used as the input of subsequent circuits to represent the clock signal frequency.

[0026] See Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the frequency detection circuit provided in this application. The frequency detection circuit 100 includes a control signal generation circuit 110, a charging and discharging circuit 120, and a detection voltage generation circuit 130.

[0027] The control signal generation circuit 110 is used to receive the clock signal CK to be detected. in Generate the clock signal CK to be detected. in The corresponding first control signal CK P and relative to the first control signal CK P Delayed second control signal CK PD .

[0028] The charging / discharging circuit 120 is coupled to the control signal generation circuit 110, and in the second control signal CK PD Controlled charging and discharging: under the second control signal CK PD During the high-level pulse width, the charging / discharging circuit 120 discharges, as indicated by the second control signal CK. PD During the low-level period, the charging / discharging circuit 120 is charged.

[0029] The voltage generation circuit 130 is coupled to the output terminal of the charge / discharge circuit 120 and the control signal generation circuit 110, and is connected to the first control signal CK. PDuring the high-level pulse width, the voltage signal ND1 at the output terminal of the charging / discharging circuit 120 is sampled at its value before discharge to output the first voltage signal V1. The clock signal CK to be detected... in The lower the frequency, the greater the voltage value of the first voltage signal V1.

[0030] Specifically, in this embodiment, the charging and discharging circuit 120 further includes a power supply A, a first switch S1, and a first capacitor C1, wherein the first terminal of the first capacitor C1 is coupled to the power supply A, and the second terminal of the first capacitor C1 is grounded; the first terminal of the first switch S1 is coupled to the first terminal of the first capacitor C1, the second terminal of the first switch S1 is grounded, and the control terminal of the first switch S1 receives a second control signal CK. PD The voltage generation circuit 130 further includes a second switch S2 and a second capacitor C2, wherein the first terminal of the second switch S2 is coupled to the first terminal of the first capacitor C1 (i.e., the output terminal ND1 of the charging and discharging circuit 120), and the control terminal of the second switch S2 receives the first control signal CK. P The first terminal of the second capacitor C2 is coupled to the second terminal of the second switch S2 and is used to output the first voltage signal V1. The second terminal of the second capacitor C2 is grounded.

[0031] The following is combined with Figure 3 The working principle of the circuit in this embodiment will be explained. Figure 3 This is a waveform diagram of the signals at each node in the second embodiment. In this embodiment, the first switch S1 and the second switch S2 are turned on when the control terminal is at a logic high level "1" and turned off when the control terminal is at a logic low level "0".

[0032] First control signal CK P The logic level is high "1", and the second control signal CK is also high. PD When the logic level is low "0", the second switch S2 is turned on, the first switch S1 is turned off, power supply A charges the first capacitor C1 and the second capacitor C2, the voltage of the first node signal ND1 is pulled high, and the first voltage signal V1 is pulled high. In the first control signal CK... P The logic level is high "0", and the second control signal is CK. PD When the logic level is low "0", power supply A continues to charge the first capacitor C1. Therefore, the charging time of the first capacitor C1 is determined by the second control signal CK. PD The duration of the logic low level "0" is determined by the first and second control signals CK. P and CK PD The pulse width for the logic high level "1" is fixed (how to fix this pulse width will be explained in detail later), then the first and second control signals CK P and CK PDThe duration of the logic low level "0" is determined by the first and second control signals CK. P and CK PD The period length is determined by the first and second control signals CK. P and CK PD All are generated by the clock signal CK to be detected. in The processing generates the signal, therefore the period is always the same as the clock signal CK to be detected. in The charging time of the first capacitor C1 by power supply A is the same, therefore the charging time of the first capacitor C1 by the clock signal CK to be detected is determined. in The period (frequency) determines the clock signal CK to be detected. in The lower the frequency and the longer the period, the longer the charging time of the first capacitor C1 by power supply A. In the first control signal CK... P The logic level is low "0", and the second control signal CK is also low. PD When the logic level is high ("1"), the second switch S2 is off, the first switch S1 is on, the first capacitor C1 discharges, the second capacitor C2 remains on, the voltage of the first node signal ND1 is pulled low, and the first voltage signal V1 remains on. After several clock cycles, the first capacitor C1 is cyclically charged and discharged, the voltage of the first node signal ND1 exhibits a "sawtooth" pattern, the second capacitor C2 is charged multiple times, and the first voltage signal V1 is pulled high through the charge sharing between the second capacitor C2 and the first capacitor C1. This is achieved when the clock signal CK is detected... in Under the premise of stable frequency, a stable voltage value is finally reached. This voltage value can reflect the voltage reached by the first node signal ND1 in each charging cycle, and can also reflect the voltage reached by the second control signal CK. PD The length of the period, i.e., the clock signal CK to be detected. in The frequency magnitude.

[0033] See Figure 4 , Figure 4 This is a schematic diagram of the structure of the third embodiment of the frequency detection circuit provided in this application. The frequency detection circuit 100 includes a control signal generation circuit 110, a charging and discharging circuit 120, and a detection voltage generation circuit 130.

[0034] The control signal generation circuit 110 is used to receive the clock signal CK to be detected. in Generate the clock signal CK to be detected. in The corresponding first control signal CK P and relative to the first control signal CK P Delayed second control signal CK PD .

[0035] The charging / discharging circuit 120 is coupled to the control signal generation circuit 110, and in the second control signal CK PD Controlled charging and discharging: under the second control signal CKPD During the high-level pulse width, the charging / discharging circuit 120 discharges, as indicated by the second control signal CK. PD During the low-level period, the charging / discharging circuit 120 is charged.

[0036] The voltage generation circuit 130 is coupled to the output terminal of the charge / discharge circuit 120 and the control signal generation circuit 110, and is connected to the first control signal CK. P During the high-level pulse width, the voltage signal ND1 at the output terminal of the charging / discharging circuit 120 is sampled at its value before discharge to output the first voltage signal V1. The clock signal CK to be detected... in The lower the frequency, the greater the voltage value of the first voltage signal V1.

[0037] Specifically, in this embodiment, the charging and discharging circuit 120 further includes a power supply A, a first switch S1, and a first capacitor C1, wherein the first terminal of the first capacitor C1 is coupled to the power supply A, and the second terminal of the first capacitor C1 is grounded; the first terminal of the first switch S1 is coupled to the first terminal of the first capacitor C1, the second terminal of the first switch S1 is grounded, and the control terminal of the first switch S1 receives a second control signal CK. PD The voltage generation circuit 130 further includes a second switch S2, a second capacitor C2, a third switch S3, and a third capacitor C3. The first terminal of the second switch S2 is coupled to the first terminal of the first capacitor C1 (i.e., the output terminal ND1 of the charging / discharging circuit 120). The control terminal of the second switch S2 receives the first control signal CK. P The first terminal of the second capacitor C2 is coupled to the second terminal of the second switch S2, and the second terminal of the second capacitor C2 is grounded. The first terminal of the third switch S3 is coupled to the first terminal of the second capacitor C2, and the control terminal of the third switch S3 receives the second control signal CK. PD The first terminal of the third capacitor C3 is coupled to the second terminal of the third switch S3 and is used to output the first voltage signal V1. The second terminal of the third capacitor C3 is grounded.

[0038] Unlike the above embodiments, this embodiment adds a third switch S3 and a third capacitor C3, and uses the first terminal of the third capacitor C3 as the output terminal of the first voltage signal V1.

[0039] The following is combined with Figure 5 The working principle of the circuit in this embodiment will be explained. Figure 5 This is a waveform diagram of the signals at each node in the third embodiment. In this embodiment, the first switch S1, the second switch S2, and the third switch S3 are turned on when the control terminal is at a logic high level "1" and turned off when the control terminal is at a logic low level "0".

[0040] First control signal CK PThe logic level is high "1", and the second control signal CK is also high. PD When the logic level is low "0", the second switch S2 is turned on, the first switch S1 and the third switch S3 are turned off, power supply A charges the first capacitor C1 and the second capacitor C2, and the voltages of the first node signal ND1 and the second node signal ND2 are pulled high. In the first control signal CK... P The logic level is high "0", and the second control signal is CK. PD When the logic level is low "0", power supply A continues to charge the first capacitor C1. Therefore, the charging time of the first capacitor C1 is determined by the second control signal CK. PD The duration of the logic low level "0" is determined by the first and second control signals CK. P and CK PD The pulse width for the logic high level "1" is fixed (how to fix this pulse width will be explained in detail later), then the first and second control signals CK P and CK PD The duration of the logic low level "0" is determined by the first and second control signals CK. P and CK PD The period length is determined by the first and second control signals CK. P and CK PD All are generated by the clock signal CK to be detected. in The processing generates the signal, therefore the period is always the same as the clock signal CK to be detected. in The charging time of the first capacitor C1 by power supply A is the same, therefore the charging time of the first capacitor C1 by the clock signal CK to be detected is determined. in The period (frequency) determines the clock signal CK to be detected. in The lower the frequency and the longer the period, the longer the charging time of the first capacitor C1 by power supply A. In the first control signal CK... P The logic level is low "0", and the second control signal CK is also low. PD When the logic level is high ("1"), the second switch S2 is off, the first switch S1 and the third switch S3 are on, the first capacitor C1 discharges, the second capacitor C2 remains on, the third capacitor C3 is charged, the voltage of the first node signal ND1 is pulled low, the voltage of the second node signal ND2 remains on, and the first voltage signal V1 is pulled high. After several clock cycles, the first capacitor C1 is cyclically charged and discharged, and the voltage of the first node signal ND1 exhibits a "sawtooth" pattern. The second capacitor C2 is charged multiple times, and the voltage of the second node signal ND2 is pulled high through the charge sharing between the second capacitor C2 and the first capacitor C1. The third capacitor C3 is charged multiple times, and the first voltage signal V1 is pulled high through the charge sharing between the third capacitor C3 and the second capacitor C2, finally reaching a stable voltage value (at the clock signal CK to be detected). inUnder the premise of stable frequency, this voltage value can reflect the voltage reached by the first node signal ND1 in each charging cycle, and can also reflect the voltage reached by the second control signal CK. PD The length of the period, i.e., the clock signal CK to be detected. in The frequency magnitude. However, unlike the above embodiment, although the second node signal ND2 is continuously pulled high, it still exhibits a "sawtooth" pattern, affecting the quality of the output voltage. Therefore, a third capacitor C3 is added based on the above embodiment. As can be seen from the image, the first voltage signal V1 has a better voltage effect than the second node signal ND2.

[0041] See Figure 6 , Figure 6 This is a schematic diagram of the fourth embodiment of the frequency detection circuit provided in this application. The frequency detection circuit 100 includes a control signal generation circuit 110, a charging and discharging circuit 120, and a detection voltage generation circuit 130.

[0042] The control signal generation circuit 110 includes a first AND gate unit A1, a first delay unit D1, a first inverting unit N1 (NOT gate unit), a second AND gate unit A2, and a second delay unit D2. The first input terminal of the first AND gate unit A1 receives the clock signal CK to be detected. in The second input terminal of the first AND gate unit A1 receives the enable signal EN (which is logic high level "1" during operation). The input terminal of the first delay unit D1 is coupled to the output terminal of the first AND gate unit A1. (In some embodiments, the control signal generation circuit 211 may not have the first AND gate unit A1, and the input terminal of the first delay unit D1 may be directly connected to the clock signal CK to be detected.) in The input of the first inverting unit N1 is coupled to the output of the first delay unit D1; the first input of the second AND gate unit A2 is coupled to the input of the first delay unit D1, the second input of the second AND gate unit A2 is coupled to the output of the first inverting unit N1, and the output of the second AND gate unit A2 outputs the first control signal CK. P The input of the second delay unit D2 is coupled to the output of the second AND gate unit A2, and the output of the second delay unit D2 outputs the second control signal CK. PD .

[0043] Specifically, in this embodiment, the charging and discharging circuit 120 further includes a power supply A, a first switch S1, and a first capacitor C1, wherein the first terminal of the first capacitor C1 is coupled to the power supply A, and the second terminal of the first capacitor C1 is grounded; the first terminal of the first switch S1 is coupled to the first terminal of the first capacitor C1, the second terminal of the first switch S1 is grounded, and the control terminal of the first switch S1 receives a second control signal CK. PDThe voltage generation circuit 130 further includes a second switch S2, a second capacitor C2, a third switch S3, and a third capacitor C3. The first terminal of the second switch S2 is coupled to the first terminal of the first capacitor C1 (i.e., the output terminal ND1 of the charging / discharging circuit 120). The control terminal of the second switch S2 receives the first control signal CK. P The first terminal of the second capacitor C2 is coupled to the second terminal of the second switch S2, and the second terminal of the second capacitor C2 is grounded. The first terminal of the third switch S3 is coupled to the first terminal of the second capacitor C2, and the control terminal of the third switch S3 receives the second control signal CK. PD The first terminal of the third capacitor C3 is coupled to the second terminal of the third switch S3 and is used to output the first voltage signal V1. The second terminal of the third capacitor C3 is grounded.

[0044] Optionally, the first switch S1, the second switch S2, and the third switch S3 described above can be implemented using an nMOS transistor or a transmission gate composed of an nMOS transistor and a pMOS transistor.

[0045] The following is combined with Figure 7 The working principle of the circuit in this embodiment will be explained. Figure 7 This is a waveform diagram of the signals at each node in the fourth embodiment. In this embodiment, the first switch S1, the second switch S2, and the third switch S3 are turned on when the control terminal is at a logic high level "1" and turned off when the control terminal is at a logic low level "0".

[0046] Clock signal CK to be detected in After processing by the first delay unit D1 and inverter N1, the obtained reference clock signal CK ref Compared to the clock signal CK to be detected in Conversely, it has a certain delay, and then the clock signal CK to be detected... in and reference clock signal CK ref Perform AND logic processing to obtain the first control signal CK. P Then, the first control signal CK P After processing by the second delay unit D2, the second control signal CK is obtained. PD In this way, the first control signal CK P Second control signal CK PD The period length is the same as that of the clock signal CK to be detected. in The same, and the first and second control signals CK P and CK PD The pulse width for a logic high level "1" is fixed and determined by the first delay unit D1.

[0047] First control signal CK P The logic level is high "1", and the second control signal CK is also high.PD When the logic level is low "0", the second switch S2 is turned on, the first switch S1 and the third switch S3 are turned off, power supply A charges the first capacitor C1 and the second capacitor C2, and the voltages of the first node signal ND1 and the second node signal ND2 are pulled high. In the first control signal CK... P The logic level is high "0", and the second control signal is CK. PD When the logic level is low "0", power supply A continues to charge the first capacitor C1. Therefore, the charging time of the first capacitor C1 is determined by the second control signal CK. PD The duration of the logic low level "0" is determined by the first and second control signals CK. P and CK PD If the pulse width of the logic high level "1" is fixed, then the first and second control signals CK P and CK PD The duration of the logic low level "0" is determined by the first and second control signals CK. P and CK PD The period length is determined by the first and second control signals CK. P and CK PD All are generated by the clock signal CK to be detected. in The processing generates the signal, therefore the period is always the same as the clock signal CK to be detected. in The charging time of the first capacitor C1 by power supply A is the same, therefore the charging time of the first capacitor C1 by the clock signal CK to be detected is determined. in The period (frequency) determines the clock signal CK to be detected. in The lower the frequency and the longer the period, the longer the charging time of the first capacitor C1 by power supply A. In the first control signal CK... P The logic level is low "0", and the second control signal CK is also low. PD When the logic level is high ("1"), the second switch S2 is off, the first switch S1 and the third switch S3 are on, the first capacitor C1 discharges, the second capacitor C2 remains on, the third capacitor C3 is charged, the voltage of the first node signal ND1 is pulled low, the voltage of the second node signal ND2 remains on, and the first voltage signal V1 is pulled high. After several clock cycles, the first capacitor C1 is cyclically charged and discharged, and the voltage of the first node signal ND1 exhibits a "sawtooth" pattern. The second capacitor C2 is charged multiple times, and the voltage of the second node signal ND2 is pulled high through the charge sharing between the second capacitor C2 and the first capacitor C1. The third capacitor C3 is charged multiple times, and the first voltage signal V1 is pulled high through the charge sharing between the third capacitor C3 and the first capacitor C2, finally reaching a stable voltage value (at the clock signal CK to be detected). in Under the premise of stable frequency, this voltage value can reflect the voltage reached by the first node signal ND1 in each charging cycle, and can also reflect the voltage reached by the second control signal CK. PDThe length of the period, i.e., the clock signal CK to be detected. in The frequency magnitude. However, unlike the above embodiment, although the second node signal ND2 is continuously pulled high, it still exhibits a "sawtooth" pattern, affecting the quality of the output voltage. Therefore, a third capacitor C3 is added based on the above embodiment. As can be seen from the image, the first voltage signal V1 has a better voltage effect than the second node signal ND2.

[0048] In combination with the above Figures 1-7 In the embodiments described above, the first voltage signal V1 output by the frequency detection circuit can be applied to many applications requiring the detection of the clock signal CK. in In applications involving frequency value changes, such as duty cycle adjustment circuits, see [reference needed]. Figure 8 , Figure 8 This is a schematic diagram of the duty cycle adjustment circuit in one embodiment. The duty cycle adjustment circuit 800 includes a filter circuit 810, an adjustable resistor device 820, a DC bias amplifier circuit 830, and a frequency detection circuit 100 as described in the above embodiment.

[0049] The first clock signal CK is input to the input terminal of the filter circuit 810. in The first terminal of the adjustable resistor 820 is coupled to the output terminal of the filter circuit 810, and the second terminal of the adjustable resistor 820 is coupled to the input terminal of the DC bias amplifier circuit 830. The output terminal of the DC bias amplifier circuit 830 outputs the second clock signal CK. out The larger the on-resistance of the adjustable resistor 820, the stronger the signal V at the input terminal of the DC bias amplifier circuit 830. out The smaller the DC component, the better; the input terminal of the frequency detection circuit 100 is coupled to the input terminal of the filter circuit 810, and the output terminal of the frequency detection circuit 100 is coupled to the control terminal of the adjustable resistor device 820.

[0050] The frequency detection circuit 100 is based on the first clock signal CK. in The frequency generates a corresponding first voltage signal V1, and the on-resistance of the adjustable resistor device 820 changes in response to the voltage value of the first voltage signal V1.

[0051] Specifically, in one embodiment, the first clock signal CK in The lower the frequency, the larger the voltage value of the first voltage signal V1 generated by the frequency detection circuit 100, the larger the on-resistance of the adjustable resistor device 820, and the greater the corresponding signal V1 output by the control filter circuit 810. in The greater the attenuation, the stronger the signal V at the input of the DC bias amplifier circuit 830. out The smaller the low-frequency DC component, the better. More specifically, due to the output signal V of the filter circuit 810... inThe signal V at the input terminal of the DC bias amplifier circuit 830 out The following relationship must be satisfied: ; Where R in R is the on-resistance value of the adjustable resistor device 820. out The total resistance of the N resistors connected in series with R0 in the DC bias amplifier circuit 830 (hereinafter referred to as R0) Figure 9 (To be detailed). First clock signal CK in The lower the frequency, the larger the voltage value V1 of the first voltage signal, and the greater the on-resistance R of the variable resistor. in The larger the value, the higher the signal V at the input terminal of the DC bias amplifier circuit 830. out The smaller the value, the better for the output signal V of the filter circuit 810. in The greater the attenuation amplitude, the better the first clock signal CK can be achieved. in At low frequencies, the duty cycle adjustment circuit 800 outputs a second clock signal CK. out Adjustment of duty cycle.

[0052] See Figure 9 , Figure 9 This is a schematic diagram of the duty cycle adjustment circuit in another embodiment. The duty cycle adjustment circuit 800 includes a filter circuit 810, an adjustable resistor device 820, a DC bias amplifier circuit 830, and a frequency detection circuit 100 as described in the above embodiment.

[0053] The first clock signal CK is input to the input terminal of the filter circuit 810. in The first terminal of the adjustable resistor 820 is coupled to the output terminal of the filter circuit 810, and the second terminal of the adjustable resistor 820 is coupled to the input terminal of the DC bias amplifier circuit 830. The output terminal of the DC bias amplifier circuit 830 outputs the second clock signal CK. out The larger the on-resistance of the adjustable resistor 820, the stronger the signal V at the input terminal of the DC bias amplifier circuit 830. out The smaller the DC component, the better; the input terminal of the frequency detection circuit 100 is coupled to the input terminal of the filter circuit 810, and the output terminal of the frequency detection circuit 100 is coupled to the control terminal of the adjustable resistor device 820.

[0054] In this embodiment, the adjustable resistor device 820 is a transmission gate unit, which includes an nMOS transistor and a pMOS transistor. The first terminal of the nMOS transistor is coupled to the output terminal of the filter circuit 810, the second terminal of the nMOS transistor is coupled to the input terminal of the DC bias amplifier circuit 830, and the control terminal of the nMOS transistor is coupled to the output terminal of the frequency detection circuit 100. The first terminal of the pMOS transistor is coupled to the output terminal of the filter circuit 810, the second terminal of the pMOS transistor is coupled to the input terminal of the DC bias amplifier circuit 830, and the control terminal of the pMOS transistor is coupled to the output terminal of the frequency detection circuit 100.

[0055] Further reading Figure 10 , Figure 10 This is a graph showing the relationship between the on-resistance of the transmission gate and the control terminal voltage. As can be seen from the graph, the resistance of the transmission gate is at its maximum when the control terminal voltage (i.e., the gate voltages of the nMOS and pMOS transistors) is the threshold voltage V0. As the control terminal voltage decreases or increases from V0, the resistance of the transmission gate gradually decreases. Therefore, in this embodiment, the variation range of the first voltage signal V1 output by the frequency detection circuit 100 can be controlled between 0 and V0, so that the resistance of the transmission gate increases as the first voltage signal V1 increases.

[0056] In one embodiment, the filter circuit 810 includes a low-pass filter circuit and a high-pass filter circuit, and the input terminal of the low-pass filter circuit is used to input the first clock signal CK. in The input of the high-pass filter circuit is coupled to the output of the low-pass filter circuit, and the output of the high-pass filter circuit is coupled to the input of the DC bias amplifier circuit 830.

[0057] Specifically, the low-pass filter circuit is used to filter low-frequency components in the signal. The low-pass filter circuit includes a first resistor R1 and a fourth capacitor C4. The first terminal of the first resistor R1 is used to input the first clock signal CK. in The first terminal of the fourth capacitor C4 is coupled to the second terminal of the first resistor R1, and the second terminal of the fourth capacitor C4 is grounded.

[0058] Specifically, the high-pass filter circuit is used to filter high-frequency components in the signal. The high-pass filter circuit includes a fifth capacitor C5 and a sixth capacitor C6. The first end of the fifth capacitor C5 is coupled to the second end of the fourth capacitor C4, and the second end of the fifth capacitor C5 is coupled to the input terminal of the DC bias amplifier circuit 830. The first end of the sixth capacitor C6 is coupled to the second end of the fifth capacitor C5, and the second end of the sixth capacitor C6 is grounded.

[0059] Optionally, in one embodiment, the DC bias amplifier circuit 830 includes an inverting unit group, a resistor group, and a capacitor group. The inverting unit group includes N inverting units N0, which are connected in series. The input terminal of the first inverting unit N0 is coupled to the output terminal of the filter circuit 810, and the output terminal of the last inverting unit N0 is used to output the second clock signal CK. out The resistor unit group includes N resistors R0, which are connected in series. The resistor unit group and the inverting unit group are connected in parallel. The capacitor group includes N-1 capacitors C0. The first terminal of the capacitor C0 in the N-1 capacitors C0 is coupled between every two adjacent resistors R0 in the N resistors. The second terminal of the capacitor C0 in the N-1 capacitors C0 is grounded. N is an odd number greater than 3.

[0060] This also includes a second inverting unit N2. The input of the second inverting unit N2 is coupled to the output of the last inverting unit N0 among the N inverting units N0. The output of the second inverting unit N2 is used to output the second clock signal CK. out .

[0061] Understandably, multiple inverting units are used for step-by-step phase reshaping, and multiple RC units (composed of R0 and C0) provide a DC bias point.

[0062] Optionally, in one embodiment, the duty cycle adjustment circuit 800 further includes a first buffer unit H1 and a second buffer unit H2, wherein the input terminal of the first buffer unit H1 is used to input the first clock signal CK. in The output of the first buffer unit H1 is coupled to the input of the filter circuit 810; the input of the second buffer unit H2 is coupled to the output of the DC bias amplifier circuit 830, and the output of the second buffer unit H2 is used to output the second clock signal CK. out .

[0063] See Figure 11 , Figure 11 This is a schematic diagram of the fifth embodiment of the frequency detection circuit provided in this application. The frequency detection circuit 100 includes a control signal generation circuit 110, a charging and discharging circuit 120, a detection voltage generation circuit 130, a comparison circuit 140, and a low dropout linear regulator 150.

[0064] The control signal generation circuit 110 is used to receive the clock signal CK to be detected. in Generate the clock signal CK to be detected. in The corresponding first control signal CK P and relative to the first control signal CK P Delayed second control signal CK PD The charging / discharging circuit 120 is coupled to the control signal generation circuit 110, and in the second control signal CK...PD Under controlled charging and discharging, wherein: the second control signal CK PD During the high-level pulse width, the charging / discharging circuit 120 discharges, as indicated by the second control signal CK. PD During the low-level period, the charging / discharging circuit 120 charges. A voltage detection circuit 130 is coupled to the output of the charging / discharging circuit 120 and the control signal generation circuit 110, and is activated by the first control signal CK. P During the high-level pulse width, the voltage signal ND1 at the output terminal of the charging / discharging circuit 120 is sampled at its value before discharge to output the first voltage signal V1. The clock signal CK to be detected... in The lower the frequency, the greater the voltage value of the first voltage signal V1.

[0065] In this embodiment, the comparison circuit 140 is coupled to the detection voltage generation circuit 130, and is used to compare the first voltage signal V1 with at least one preset reference voltage signal V. ref Voltage values ​​are compared to obtain the corresponding comparison result signal V. comp The low-dropout linear regulator 150 is used to adjust the voltage based on the comparison result signal V. comp A matching second voltage signal V2 is generated.

[0066] Optionally, in this embodiment, the first clock signal CK in The frequency value is negatively correlated with the voltage value of the first voltage signal V1, that is, the first clock signal CK in The smaller the frequency value, the larger the voltage value of the first voltage signal V1. The comparator circuit 140 can be a hysteresis comparator, with the reference voltage signal V1 input to the non-inverting input terminal of the hysteresis comparator. ref The inverting input of the hysteresis comparator receives the first voltage signal V1. Using a hysteresis comparator avoids the comparator circuit 140 being affected by the first clock signal CK. in The problem of frequency jitter can be addressed in other embodiments by using other types of comparators for the comparator circuit 140.

[0067] In combination with the above Figure 11 In the embodiments described above, the frequency detection circuit can be applied to a delay-locked loop circuit, see reference. Figure 12 , Figure 12 This is a schematic diagram of a delay phase-locked loop circuit 900 in one embodiment. The delay phase-locked loop circuit 900 includes a delay circuit 910, a phase detection circuit 920, a control circuit 930, and a frequency detection circuit 100 as described in the above embodiment.

[0068] Figure 13This is a schematic diagram of the delay circuit 910 in one embodiment. The delay circuit 910 includes delay lines. Each step of the delay circuit 910 is adjusted by changing the control signals D0, D1…Dn (for simplicity...). Figure 13 The diagram only shows the number of gate circuits connected to the delay lines (D0, D1) to adjust the second clock signal CK. out Relative to the first clock signal CK in The total delay is gradually adjusted until the edges of the two are aligned (i.e., locked). For example, initially the control signal D0 is 0, and the first clock signal CK... in The second clock signal CK is output through the first delay path, which consists of only the two leftmost NAND gates (NAND gates 1 and 2). out If locking fails, the second step is to change control signal D0 to 1 and D1 to 0, and the first clock signal CK... in The second delay path, consisting of four NAND gates (NAND gates 3, 4, 5, and 2), outputs the second clock signal CK. out ...and so on, by gradually changing the control signal to change the delay path until the total delay generated by the delay line causes the second clock signal CK to... out Relative to the first clock signal CK in Edge alignment (i.e., locking).

[0069] Figure 13 The schematic diagram of the delay line in the delay circuit 910 is only an example; the delay line can also be implemented using other gate circuits. Therefore, it can be seen that the adjustment amount (i.e., step size) of each delay step of the delay line is related to the delay generated by a single gate circuit, as mentioned above. Figure 12 One embodiment achieves the adjustment of the delay of a single gate circuit by adjusting the power supply voltage.

[0070] In other embodiments, however... Figure 11 The frequency detection circuit 100 may also omit the low-dropout linear regulator 150, instead using delay devices added to each delay node on each delay path of the delay line. These delay devices can be... Figure 13 The MOS capacitors 1 to n shown are for simplification. Figure 13 Only MOS capacitors 1 and 2 are shown in the diagram. The MOS capacitors respond to the comparison result signal V. comp The logic level is turned on or off to adjust the delay of each delay path in the delay line, that is, the delay (i.e., the step size) of each step adjustment of the delay line. Specifically, the first clock signal CK in When the value is below a set threshold, the comparison result signal V comp By controlling the MOS capacitors of each delay node to turn on, the delays of the first and second delay paths are increased accordingly, thereby increasing the delay (i.e., step size) of each delay line adjustment; the first clock signal CKin When the value is higher than the set threshold, the comparison result signal V comp By controlling the MOS capacitors of each delay node to turn off, the delays of both the first and second delay paths are reduced accordingly, thereby reducing the delay time (i.e., step size) of each delay line adjustment. The main principle of MOS transistors forming capacitors is to use the gate oxide layer between the gate and the channel as an insulating medium, with the gate as the upper electrode and the source, drain, and substrate shorted together to form the lower electrode.

[0071] See Figure 14 , Figure 14 This is a schematic diagram of an embodiment of the electronic device provided in this application. The electronic device 500 includes the frequency detection circuit 100 as described in the above embodiment. Of course, in conjunction with the above... Figure 8 and Figure 12 In some embodiments, the electronic device 500 may be a storage device, including the duty cycle adjustment circuit or phase-locked delay circuit described above. The storage device may be a dynamic random access memory (DRAM), such as DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random-Access Memory).

[0072] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0073] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A frequency detection circuit, characterized in that, The frequency detection circuit includes: A control signal generation circuit is used to receive a clock signal to be detected and generate a first control signal corresponding to the clock signal to be detected and a second control signal delayed relative to the first control signal. A charging / discharging circuit, coupled to the control signal generating circuit, and charging / discharging under the control of the second control signal, wherein the charging / discharging circuit discharges during the pulse width of a high-level pulse of the second control signal and charges during the low-level pulse of the second control signal; and A voltage generation circuit is coupled to the output terminal of the charging and discharging circuit and the control signal generation circuit. During the pulse width when the first control signal is high, the voltage at the output terminal of the charging and discharging circuit is sampled to the voltage value before discharging, so as to output the corresponding first voltage signal. Wherein, the lower the frequency of the clock signal to be detected, the higher the voltage value of the first voltage signal.

2. The frequency detection circuit according to claim 1, characterized in that, The frequency of the second control signal is the same as the frequency of the clock signal to be detected, and the pulse width of the second control signal at a high level remains unchanged.

3. The frequency detection circuit according to claim 1, characterized in that, The charging and discharging circuit includes: power supply; A first capacitor, wherein a first terminal of the first capacitor is coupled to the power supply, and a second terminal of the first capacitor is grounded; and A first switch, the first end of which is coupled to the first end of the first capacitor, the second end of which is grounded, and the control terminal of the first switch receives the second control signal.

4. The frequency detection circuit according to claim 3, characterized in that, The detection voltage generation circuit further includes: A second switch, the first terminal of which is coupled to the first terminal of the first capacitor, and the control terminal of the second switch receives the first control signal; and The second capacitor has its first terminal coupled to the second terminal of the second switch and used to output the first voltage signal, and its second terminal is grounded.

5. The frequency detection circuit according to claim 4, characterized in that, The detection voltage generation circuit further includes: The third switch has a first terminal coupled to the first terminal of the second capacitor, and the control terminal of the third switch receives the second control signal. The third capacitor has its first terminal coupled to the second terminal of the third switch and used to output the first voltage signal. The second terminal of the third capacitor is grounded.

6. The frequency detection circuit according to claim 5, characterized in that, The first switch, the second switch, and the third switch are implemented as a transmission gate composed of an nMOS transistor or a combination of an nMOS transistor and a pMOS transistor.

7. The frequency detection circuit according to claim 1, characterized in that, The control signal generation circuit includes: A first delay unit, wherein the input terminal of the first delay unit is used to receive the clock signal to be detected; The first inverting unit, wherein the input terminal of the first inverting unit is coupled to the output terminal of the first delay unit; An AND gate unit, wherein the first input terminal of the AND gate unit is used to receive the clock signal to be detected, the second input terminal of the AND gate unit is coupled to the output terminal of the first inverting unit, and the output terminal of the AND gate unit outputs the first control signal; The second delay unit has its input coupled to the output of the AND gate unit, and its output outputs the second control signal.

8. The frequency detection circuit according to claim 1, characterized in that, The frequency detection circuit further includes: A comparison circuit, coupled to the detection voltage generation circuit, is used to compare the first voltage signal with at least one preset reference voltage signal to obtain a corresponding comparison result signal.

9. The frequency detection circuit according to claim 8, characterized in that, The frequency detection circuit further includes: A low-dropout linear regulator, coupled to the output of the comparator circuit, is used to generate a matching second voltage signal based on the comparison result signal.

10. An electronic device, characterized in that, The electronic device includes a frequency detection circuit as described in any one of claims 1-9.

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