Board-level chip testing method and device, storage medium and electronic device

Abstract

The application discloses a kind of board-level chip testing method and device, storage medium and electronic device, the board-level chip testing method includes: control and the power supply device of the power input end of the board-level chip to be tested is connected with the output of preset test voltage, while, control the current value on the load device connected with the power output end of board-level chip reaches preset test current;Actual input voltage and actual input current on the power input end of board-level chip are acquired, while, the voltage value on the power output end of board-level chip is detected, and actual output voltage is obtained;Chip loss parameter, chip efficiency parameter and chip operating parameter of board-level chip are determined according to test current, actual input current, actual input voltage and actual output voltage, using the above technical solution, the problems, such as lower test efficiency of board-level chip in related art, are solved.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a method and apparatus for testing board-level chips, a storage medium, and an electronic device. Background Technology

[0002] Currently, server CPUs (Central Processing Units) have increasingly higher power consumption requirements, and high-power CPUs require the motherboard power supply circuitry to handle greater current. Board-level chips refer to integrated circuit chips embedded on the motherboard. As important components on the motherboard, they play a role in regulating voltage between the power supply and the electrical load.

[0003] Although board-level chips (BLPs) are usually labeled with a series of theoretical parameters, these parameters are typically theoretical values ​​without verification. For example, the chip loss parameters labeled on BLPs are generally derived through simulation or calculation based on the chip's impedance and the current flowing through it. However, after actual deployment, due to differences in the BLP's manufacturing process, motherboard routing, wiring, and heat dissipation, the actual parameters may not match the specifications. This can lead to server crashes, malfunctions, and abnormal restarts. Therefore, it is crucial to perform actual testing on the parameters of BLPs before deployment. However, BLPs have numerous theoretical parameters, and each parameter is tested individually. Testing each parameter requires soldering different test points and setting up a new test environment, which is time-consuming.

[0004] There is still no effective solution to the problem of low testing efficiency of board-level chips in related technologies. Summary of the Invention

[0005] This application provides a method and apparatus for testing board-level chips, a storage medium, and an electronic device, to at least solve the problems of low testing efficiency of board-level chips in related technologies.

[0006] According to one embodiment of this application, a method for testing board-level chips is provided, comprising: The system controls the power supply device connected to the power input terminal of the board-level chip under test to output a preset test voltage. Simultaneously, it controls the current value on the load device connected to the power output terminal of the board-level chip to reach a preset test current. The test voltage is greater than or equal to the minimum chip voltage and less than or equal to the maximum chip voltage, where the maximum chip voltage is the maximum voltage value allowed to be loaded on the board-level chip, and the minimum chip voltage is the minimum voltage value allowed to be loaded on the board-level chip. The test current is less than or equal to the maximum load current, where the maximum load current is the maximum current value allowed to be loaded by the load device. The actual input voltage and actual input current at the power input terminal of the board-level chip are obtained, and the voltage value at the power output terminal of the board-level chip is detected to obtain the actual output voltage. Based on the test current, the actual input current, the actual input voltage, and the actual output voltage, the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip are determined, wherein the chip loss parameters are used to indicate the power loss of the board-level chip, the chip efficiency parameters are used to indicate the power efficiency of the board-level chip, and the chip operating parameters are used to indicate the operating status of the board-level chip.

[0007] Optionally, the power supply device connected to the power input terminal of the board-level chip under test outputs a preset test voltage, including: A reference test voltage is obtained from a set of reference test voltages as the test voltage, wherein the set of reference test voltages includes one or more of the reference test voltages; The power supply device connected to the power input terminal of the board-level chip under test outputs the test voltage.

[0008] Optionally, before obtaining a reference test voltage from the set of reference test voltages as the test voltage, the method further includes: Obtain the normal operating voltage corresponding to the board-level chip, wherein the normal operating voltage is the voltage that the board-level chip is allowed to apply when it is working normally; One or more reference test voltages are generated based on the normal operating voltage and the first preset ratio to obtain the reference test voltage set.

[0009] Optionally, the step of generating one or more reference test voltages based on the normal operating voltage and the first preset ratio includes at least one of the following: The normal operating voltage and the first target voltage amplitude are added together to obtain the maximum chip voltage; the maximum chip voltage is determined as the reference test voltage, wherein the first target voltage amplitude is the product of the normal operating voltage and the first preset ratio; The minimum chip voltage is obtained by subtracting the normal operating voltage from the first target voltage amplitude; the minimum chip voltage is determined as the reference test voltage, wherein the first target voltage amplitude is the product of the normal operating voltage and the first preset ratio; The normal operating voltage is determined as the reference test voltage.

[0010] Optionally, determining the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip based on the test current, the actual input current, the actual input voltage, and the actual output voltage includes: The difference between the actual input voltage and the actual output voltage is determined as the first difference; the product of the actual input current and the first difference is determined as the chip loss parameter. The product of the test current and the actual output voltage is determined as a first value; the product of the actual input current and the actual input voltage is determined as a second value; the ratio of the first value and the second value is determined as the chip efficiency parameter. A target voltage range is generated based on the test voltage and a second preset ratio, wherein the second preset ratio is less than the first preset ratio. When the actual input voltage falls within the target voltage range, the chip operating parameter is determined as a first operating parameter, wherein the chip operating parameter is the first operating parameter used to indicate that the board-level chip is operating normally. When the actual input voltage does not fall within the target voltage range, the chip operating parameter is determined as a second operating parameter, wherein the chip operating parameter is the second operating parameter used to indicate that the board-level chip is operating abnormally.

[0011] Optionally, generating the target voltage range based on the test voltage and the second preset ratio includes: The test voltage and the second target voltage amplitude are added together to obtain the first target voltage, wherein the second target voltage amplitude is the product of the test voltage and the second preset ratio; The test voltage and the second target voltage amplitude are subtracted to obtain the second target voltage, wherein the second target voltage amplitude is the product of the test voltage and the second preset ratio; The target voltage range is generated based on the first target voltage and the second target voltage, wherein the upper limit of the target voltage range is the first target voltage and the lower limit of the target voltage range is the second target voltage.

[0012] Optionally, controlling the current value on the load device connected to the power output terminal of the board-level chip to reach a preset test current includes: A reference test current is sequentially obtained from a set of reference test currents as the test current, wherein the set of reference test currents includes one or more of the reference test currents; The current value on the load device connected to the power output terminal of the board-level chip is controlled to reach the test current.

[0013] Optionally, before obtaining a reference test current from the set of reference test currents as the test current, the method further includes: Obtain the maximum load current; N reference test currents are generated based on the maximum load current and a preset percentage sequence to obtain the reference test current set. The percentage sequence includes N percentages, is an arithmetic sequence, the percentage of the largest term in the percentage sequence is 100%, the percentage of the smallest term in the percentage sequence is 0%, and N is a positive integer greater than 2.

[0014] Optionally, generating N reference test currents based on the maximum load current and a preset percentage sequence includes: The maximum load current is multiplied sequentially by each percentage in the percentage series to obtain N reference test currents.

[0015] According to another embodiment of the present application, a board-level chip testing apparatus is also provided, comprising: The control module is used to control the power supply device connected to the power input terminal of the board-level chip under test to output a preset test voltage, and simultaneously control the current value on the load device connected to the power output terminal of the board-level chip to reach a preset test current. The test voltage is greater than or equal to the minimum chip voltage and less than or equal to the maximum chip voltage, where the maximum chip voltage is the maximum voltage value allowed to be loaded on the board-level chip, the minimum chip voltage is the minimum voltage value allowed to be loaded on the board-level chip, and the test current is less than or equal to the maximum load current, where the maximum load current is the maximum current value allowed to be loaded by the load device. The first acquisition module is used to acquire the actual input voltage and actual input current at the power input terminal of the board-level chip, and at the same time, detect the voltage value at the power output terminal of the board-level chip to obtain the actual output voltage. The determination module is used to determine the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip based on the test current, the actual input current, the actual input voltage, and the actual output voltage. The chip loss parameters are used to indicate the power loss of the board-level chip, the chip efficiency parameters are used to indicate the power efficiency of the board-level chip, and the chip operating parameters are used to indicate the operating status of the board-level chip.

[0016] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, which is configured to execute the above-described board-level chip testing method when running.

[0017] According to another aspect of the embodiments of this application, an electronic device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the above-described board-level chip testing method through the computer program.

[0018] In this embodiment, the power supply device connected to the power input terminal of the board-level chip outputs a preset test voltage. Simultaneously, the current value on the load device connected to the power output terminal of the board-level chip reaches a preset test current. The test voltage is allowed to fluctuate between the minimum and maximum chip voltage, and the test current is allowed to fluctuate between 0 and the maximum load current. Then, the actual input voltage and actual input current at the power input terminal of the board-level chip, as well as the voltage value at the power output terminal, are obtained to obtain the actual output voltage. Finally, based on the test current, actual input current, actual input voltage, and actual output voltage, the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip can be determined simultaneously. This eliminates the need to solder different test points or reassemble a new test environment, significantly reducing the testing time for the board-level chip. By adopting the above technical solution, the problem of low testing efficiency of board-level chips in related technologies is solved, achieving the technical effect of improving the testing efficiency of board-level chips. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the hardware environment for a board-level chip testing method according to an embodiment of this application; Figure 2 This is a flowchart of a board-level chip testing method according to an embodiment of this application; Figure 3 This is a schematic diagram of a board-level chip testing device according to an embodiment of this application; Figure 4 This is a schematic diagram of a board-level chip being tested at its maximum chip voltage according to an embodiment of this application; Figure 5 This is a schematic diagram of a board-level chip being tested under normal operating voltage according to an embodiment of this application; Figure 6 This is a schematic diagram of a board-level chip being tested at the minimum chip voltage according to an embodiment of this application; Figure 7 This is a schematic diagram of a board-level chip testing process according to an embodiment of this application; Figure 8 This is a schematic diagram of a board-level chip testing software according to an embodiment of this application; Figure 9 This is a structural block diagram of a board-level chip testing device according to an embodiment of this application. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] The methods and embodiments provided in this application can be executed on a computer terminal, device terminal, or similar computing device. Taking running on a computer terminal as an example, Figure 1 This is a schematic diagram of the hardware environment for a board-level chip testing method according to an embodiment of this application. For example... Figure 1 As shown, a computer terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. In one exemplary embodiment, the computer terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 1 The more or fewer components shown, or having the same Figure 1 Equivalent functions or ratios shown Figure 1 The functions shown have more different configurations.

[0025] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the board-level chip testing method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0026] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0027] The terms used in the embodiments of this application are explained as follows: DC Source: DC power supply; Vin_Max: Max Vin Voltage, the maximum input voltage, i.e., the maximum chip voltage; Vin_Nom: Normal Vin Voltage, normal input voltage; Vin_Min: Min Vin Voltage, the minimum input voltage, i.e., the minimum chip voltage.

[0028] This embodiment provides a board-level chip testing method, applied to the aforementioned computer terminal. Figure 2 This is a flowchart of a board-level chip testing method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps: Step S202: Control the power supply device connected to the power input terminal of the board-level chip under test to output a preset test voltage. At the same time, control the current value on the load device connected to the power output terminal of the board-level chip to reach a preset test current. The test voltage is greater than or equal to the minimum chip voltage and less than or equal to the maximum chip voltage. The maximum chip voltage is the maximum voltage value allowed to be loaded on the board-level chip, and the minimum chip voltage is the minimum voltage value allowed to be loaded on the board-level chip. The test current is less than or equal to the maximum load current. The maximum load current is the maximum current value allowed to be loaded by the load device. Step S204: Obtain the actual input voltage and actual input current at the power input terminal of the board-level chip; simultaneously, detect the voltage value at the power output terminal of the board-level chip to obtain the actual output voltage. Step S206: Determine the chip loss parameter, chip efficiency parameter, and chip operating parameter of the board-level chip based on the test current, the actual input current, the actual input voltage, and the actual output voltage. The chip loss parameter indicates the power loss of the board-level chip, the chip efficiency parameter indicates the power efficiency of the board-level chip, and the chip operating parameter indicates the operating status of the board-level chip.

[0029] Through the above steps, the power supply device connected to the power input terminal of the board-level chip outputs a preset test voltage. Simultaneously, the current value on the load device connected to the power output terminal of the board-level chip reaches a preset test current. The test voltage is allowed to fluctuate between the minimum and maximum chip voltage, and the test current is allowed to fluctuate between 0 and the maximum load current. Then, the actual input voltage and actual input current at the power input terminal of the board-level chip, as well as the voltage value at the power output terminal, are obtained to obtain the actual output voltage. Finally, based on the test current, actual input current, actual input voltage, and actual output voltage, the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip can be determined simultaneously. This eliminates the need to solder different test points or reassemble a new test environment, significantly reducing the testing time for board-level chips. This technical solution solves the problem of low testing efficiency for board-level chips in related technologies, achieving the technical effect of improving the testing efficiency of board-level chips.

[0030] In the technical solution provided in step S202 above, Figure 3 This is a schematic diagram of a board-level chip testing device according to an embodiment of this application, as shown below. Figure 3 As shown, a board-level chip can be deployed on a motherboard to convert the voltage output from a DC power supply (i.e., a power supply device) and provide the converted voltage to an electronic load. The test equipment for this board-level chip aims to test the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip under different voltages or currents. The power supply device is used to simulate the voltage received by the board-level chip after actual deployment, while the electronic load is used to simulate the load current required in the actual deployment scenario of the board-level chip, thereby determining whether the board-level chip can meet the server's requirements after actual deployment in the server.

[0031] The structure of the board-level chip testing equipment is described below. The board-level chip testing equipment includes: a power supply (e.g., a DC power supply), a load device (e.g., an electronic load), a data detection device (e.g., multimeters 1 and 2), and a data processing device (e.g., a PC). The power input terminal of the board-level chip under test is connected to the power supply, and the power output terminal is connected to the load device. Multimeter 1 in the data detection device is connected to the power input terminal of the board-level chip, and multimeter 2 in the data detection device is connected to the power output terminal. The power supply (DC power supply), the load device (electronic load), and the data detection devices (multimeters 1 and 2) constitute an automated equipment set. Automation software is installed on the data processing device (PC), which controls the automated equipment set via GPIB (General-Purpose Interface Bus) and connects to the PC via a USB (Universal Serial Bus) to GPIB converter cable. Signal lines are soldered to the input and output capacitors of the chip and connected to a multimeter. A DC source (direct current power supply, i.e., power supply device) is connected to the chip input to power the board-level chip. The current displayed on the DC source is the test current. An electronic load is connected to the chip output to add test current to the chip.

[0032] The data processing device is used to control the power supply device connected to the power input terminal of the board-level chip under test to output a preset test voltage, and at the same time, control the current value on the load device connected to the power output terminal of the board-level chip to reach a preset test current. A data detection device is used to acquire the actual input voltage and actual input current at the power input terminal of the board-level chip, and simultaneously detect the voltage value at the power output terminal of the board-level chip to obtain the actual output voltage. The data processing device is further configured to determine the chip loss parameter, chip efficiency parameter, and chip operating parameter of the board-level chip based on the test current, the actual input current, the actual input voltage, and the actual output voltage, wherein the chip loss parameter is used to indicate the power loss of the board-level chip, the chip efficiency parameter is used to indicate the power efficiency of the board-level chip, and the chip operating parameter is used to indicate the operating status of the board-level chip.

[0033] By using the above method, the power supply device (DC power supply), load device (electronic load), and data detection device (universal power supply 1 and universal power supply 2) are combined into an automated equipment set, which allows the test points of multiple tests to be merged. The chip loss parameters, chip efficiency parameters, and chip operating parameters can be obtained through a single test, which greatly improves the testing efficiency.

[0034] In one exemplary embodiment, the power supply device connected to the power input terminal of the board-level chip under test may be controlled to output a preset test voltage in the following manner, but not limited to: obtaining a reference test voltage from a set of reference test voltages as the test voltage, wherein the set of reference test voltages includes one or more of the reference test voltages; and controlling the power supply device connected to the power input terminal of the board-level chip under test to output the test voltage.

[0035] Optionally, in this embodiment, there may be, but is not limited to, multiple test voltages, and the test voltage may be, but is not limited to, any one obtained from the reference test voltage set.

[0036] In one exemplary embodiment, before obtaining a reference test voltage from the set of reference test voltages as the test voltage, the normal operating voltage corresponding to the board-level chip may be obtained in the following manner, including but not limited to: the normal operating voltage being the voltage allowed to be applied when the board-level chip is operating normally; one or more reference test voltages are generated according to the normal operating voltage and a first preset ratio to obtain the set of reference test voltages.

[0037] Optionally, in this embodiment, each board-level chip corresponds to a normal operating voltage, which is the voltage that the board-level chip is allowed to apply when it is working normally. Under normal circumstances, the board-level chip can operate even without applying a normal operating voltage. However, when the board-level chip is at its voltage limit, its stability is the worst, and its losses will be greater. This application can select different test voltages to test the losses of the board-level chip under various voltage scenarios.

[0038] In one exemplary embodiment, generating one or more reference test voltages based on the normal operating voltage and the first preset ratio can be achieved, but is not limited to, by at least one of the following methods: The normal operating voltage and the first target voltage amplitude are added together to obtain the maximum chip voltage; the maximum chip voltage is determined as the reference test voltage, wherein the first target voltage amplitude is the product of the normal operating voltage and the first preset ratio; The minimum chip voltage is obtained by subtracting the normal operating voltage from the first target voltage amplitude; the minimum chip voltage is determined as the reference test voltage, wherein the first target voltage amplitude is the product of the normal operating voltage and the first preset ratio; The normal operating voltage is determined as the reference test voltage.

[0039] Optionally, in this embodiment, taking a normal operating voltage of 12V and a first preset ratio of 5% as an example, the method of generating a test voltage based on the normal operating voltage and the first preset ratio is explained. The first target voltage amplitude is the product of the normal operating voltage and the first preset ratio, i.e., 0.6V.

[0040] Method 1 Figure 4 This is a schematic diagram illustrating the testing of a board-level chip at its maximum chip voltage according to an embodiment of this application, as shown below. Figure 4 As shown, the maximum chip voltage is obtained by adding the first target voltage amplitude to the normal operating voltage; the maximum chip voltage is determined as the test voltage, that is, the maximum chip voltage of 12.6V is used as the test voltage; Method 2 Figure 5 This is a schematic diagram illustrating the testing of a board-level chip under normal operating voltage according to an embodiment of this application, as shown below. Figure 5 As shown, the minimum chip voltage is obtained by subtracting the first target voltage amplitude from the normal operating voltage; the minimum chip voltage is determined as the test voltage, that is, the maximum chip voltage of 11.4V is used as the test voltage; Method 3 Figure 6 This is a schematic diagram illustrating the testing of a board-level chip at its minimum chip voltage according to an embodiment of this application, as shown below. Figure 6 As shown, the normal operating voltage of 12V is determined as the test voltage.

[0041] In one exemplary embodiment, the current value on the load device connected to the power output terminal of the board-level chip can be controlled to reach a preset test current by, but is not limited to, obtaining a reference test current from a set of reference test currents in sequence as the test current, wherein the set of reference test currents includes one or more of the reference test currents; and controlling the current value on the load device connected to the power output terminal of the board-level chip to reach the test current.

[0042] Optionally, in this embodiment, there may be, but is not limited to, multiple test currents, and the test current may be, but is not limited to, any one obtained from the set of reference test currents.

[0043] In one exemplary embodiment, before obtaining a reference test current from the set of reference test currents as the test current, the method may include, but is not limited to, the following: obtaining the maximum load current; generating N reference test currents based on the maximum load current and a preset percentage sequence to obtain the set of reference test currents, wherein the percentage sequence includes N percentages, the percentage sequence is an arithmetic sequence, the percentage of the largest term in the percentage sequence is 100%, the percentage of the smallest term in the percentage sequence is 0%, and N is a positive integer greater than 2.

[0044] Optionally, in this embodiment, taking N as 10 and the maximum load current as Imax as an example, such as... Figure 4 , Figure 5 , Figure 6 As shown, the N percentages are 0%, 10%, ..., 100% in ascending order.

[0045] In one exemplary embodiment, N reference test currents may be generated based on the maximum load current and a preset percentage sequence in the following manner: the maximum load current is multiplied sequentially by each of the percentages in the percentage sequence to obtain the N reference test currents.

[0046] Optionally, in this embodiment, such as Figure 4 , Figure 5 , Figure 6 As shown, the N percentages in the percentage series are 0%, 10%, ..., 100% in ascending order. The maximum load current is sequentially multiplied by each percentage in the percentage series to obtain a reference current set. For example, multiplying the maximum load current by 0% yields a test current of 0; multiplying the maximum load current by 10% yields a test current of 10%Imax; and multiplying the maximum load current by 100% yields a test current of Imax. This ultimately results in the reference current set.

[0047] In the technical solution provided in step S204 above, the actual input voltage, actual input current, and actual output voltage need to be obtained through actual measurement, such as... Figure 4 , Figure 5 , Figure 6 As shown, the actual input voltage corresponds to Vin, the actual output voltage corresponds to Vout, and the actual input current corresponds to Iin. The actual input voltage is determined by... Figure 3 The actual output voltage measured by multimeter 1 shown is obtained through... Figure 3 The actual input current measured by multimeter 2 is shown in the figure. Figure 3 The DC power supply shown can be displayed.

[0048] In the technical solution provided in step S206 above, the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip can be determined simultaneously by testing the current, actual input current, actual input voltage, and actual output voltage.

[0049] In one exemplary embodiment, the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip can be determined, but are not limited to, based on the test current, the actual input current, the actual input voltage, and the actual output voltage, in the following manner: The difference between the actual input voltage and the actual output voltage is determined as the first difference; the product of the actual input current and the first difference is determined as the chip loss parameter. The product of the test current and the actual output voltage is determined as a first value; the product of the actual input current and the actual input voltage is determined as a second value; the ratio of the first value and the second value is determined as the chip efficiency parameter. A target voltage range is generated based on the test voltage and a second preset ratio, wherein the second preset ratio is less than the first preset ratio. When the actual input voltage falls within the target voltage range, the chip operating parameter is determined as a first operating parameter, wherein the chip operating parameter is the first operating parameter used to indicate that the board-level chip is operating normally. When the actual input voltage does not fall within the target voltage range, the chip operating parameter is determined as a second operating parameter, wherein the chip operating parameter is the second operating parameter used to indicate that the board-level chip is operating abnormally.

[0050] Optionally, in this embodiment, the actual input current, actual input voltage, and actual output voltage can be calculated using, but are not limited to, the chip loss parameters using the following formula: Chip loss parameters = actual input current (Actual input voltage - actual output voltage); Optionally, in this embodiment, the chip efficiency parameters are calculated using, but not limited to, the actual output voltage, test current, actual input voltage, and actual input current through the following formula: Chip efficiency parameter = (actual output voltage) (Test current) / (Actual input voltage) Actual input current); Optionally, in this embodiment, the calculation method of the chip loss parameter is described as follows: when the actual input voltage falls within the target voltage range, the chip operating parameter is determined as the first operating parameter, which indicates that the board-level chip is operating normally; when the actual input voltage does not fall within the target voltage range, the chip operating parameter is determined as the second operating parameter, which indicates that the board-level chip is operating abnormally.

[0051] In one exemplary embodiment, a target voltage range may be generated based on the test voltage and a second preset ratio in the following manner, but not limited to: performing an addition operation on the test voltage and the amplitude of the second target voltage to obtain a first target voltage, wherein the amplitude of the second target voltage is the product of the test voltage and the second preset ratio; performing a subtraction operation on the test voltage and the amplitude of the second target voltage to obtain a second target voltage, wherein the amplitude of the second target voltage is the product of the test voltage and the second preset ratio; generating the target voltage range based on the first target voltage and the second target voltage, wherein the upper limit of the target voltage range is the first target voltage, and the lower limit of the target voltage range is the second target voltage.

[0052] Optionally, in this embodiment, taking a second preset ratio of 3% as an example, such as... Figure 4 As shown, the test voltage is 12.6V, then the amplitude of the second target voltage is 0.378, the first target voltage is 12.222V, the second target voltage is 12.978V, and the target voltage range is 12.222V to 12.978V.

[0053] To better understand the testing process of the board-level chip described above, the testing procedure of the board-level chip will be further described below with reference to optional embodiments, but this is not intended to limit the technical solution of the embodiments of this application.

[0054] This embodiment provides a method for testing board-level chips. Figure 7 This is a schematic diagram of a board-level chip testing process according to an embodiment of this application, such as... Figure 7 As shown, the main steps include the following: Step S701: Set up this modular power loss test environment, connect the positive and negative terminals of the chip output terminals of the motherboard under test to the positive and negative terminals of the electronic load respectively, use a DC source (or power supply device) to power the motherboard, install the integrated test automation software on the PC, call the program, and ensure that the software can control all devices; Step S702: Call the test software, set test parameters such as test voltage and test current, and control the DC Source to power on the motherboard to ensure accurate multimeter measurements. Then, set the DC Source input voltage to Vin_max (maximum chip voltage), set the electronic load current (i.e., test current) to 0A, and control the multimeter. Measure the input voltage, output voltage, and input current, and automatically record them in the test report. The report automatically judges the test results. Step S703: Determine whether the current being loaded is Imax (maximum load current). If not, adjust the current being loaded so that it increases by 10% per cycle. Each time it increases, automatically measure and record the input voltage, output voltage, and input current to the report until Imax is reached. Step S704: Determine whether the three scenarios of input voltage Vin_Max (maximum chip voltage), Vin_Nom (normal operating voltage), and Vin_Min (minimum chip voltage) have been verified. Each input voltage is tested using the same automated method until the test is completed. Based on the test results captured from the integration report, import the formulas (chip loss parameter calculation formula, chip efficiency parameter calculation formula) to automatically obtain the actual tested chip loss parameters and chip efficiency parameters. At the same time, automatically compare (compare the actual input current and the target voltage range) to determine whether the board-level chip is within the normal operating range at this time.

[0055] It should be noted that, Figure 8 This is a schematic diagram of a board-level chip testing software according to an embodiment of this application, such as... Figure 8 As shown, the test software's user interface can be rapidly and standardizedly developed based on the graphical programming capabilities of PyQt5 QtDesigner, facilitating later maintenance.

[0056] The system architecture of the testing software is built on the QThread standard library under PyQt5, which gives the automated testing system multi-threading capabilities and ensures the smoothness of the user interface. The system architecture implements user interrupt requests based on the Windows system API, which enables the automated testing system to be compatible with all Windows platforms and achieve millisecond-level suspension and resumption of test task threads.

[0057] The test software's resource access is based on the pyvisa standard library to connect to instrument resources. At the same time, the resource access session is managed globally and uniformly to solve the problems of resource access conflicts in multi-threaded systems and the reclamation of instrument resources.

[0058] Data processing of the test software: After the test is completed, the test data (such as test current, actual input current, actual input voltage and actual output voltage) is automatically acquired and compared with the test SPEC (target voltage range) to obtain the test results.

[0059] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0060] Figure 9 This is a structural block diagram of a board-level chip testing apparatus according to an embodiment of this application; as shown... Figure 9 As shown, it includes: The control module 902 is used to control the power supply device connected to the power input terminal of the board-level chip under test to output a preset test voltage, and simultaneously control the current value on the load device connected to the power output terminal of the board-level chip to reach a preset test current. The test voltage is greater than or equal to the minimum chip voltage and less than or equal to the maximum chip voltage, where the maximum chip voltage is the maximum voltage value allowed to be loaded on the board-level chip, the minimum chip voltage is the minimum voltage value allowed to be loaded on the board-level chip, and the test current is less than or equal to the maximum load current, where the maximum load current is the maximum current value allowed to be loaded by the load device. The first acquisition module 904 is used to acquire the actual input voltage and actual input current at the power input terminal of the board-level chip, and at the same time, detect the voltage value at the power output terminal of the board-level chip to obtain the actual output voltage. The determining module 906 is used to determine the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip based on the test current, the actual input current, the actual input voltage, and the actual output voltage. The chip loss parameters are used to indicate the power loss of the board-level chip, the chip efficiency parameters are used to indicate the power efficiency of the board-level chip, and the chip operating parameters are used to indicate the operating status of the board-level chip.

[0061] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0062] In this embodiment, the power supply device connected to the power input terminal of the board-level chip outputs a preset test voltage. Simultaneously, the current value on the load device connected to the power output terminal of the board-level chip reaches a preset test current. The test voltage is allowed to fluctuate between the minimum and maximum chip voltage, and the test current is allowed to fluctuate between 0 and the maximum load current. Then, the actual input voltage and actual input current at the power input terminal of the board-level chip, as well as the voltage value at the power output terminal, are obtained to obtain the actual output voltage. Finally, based on the test current, actual input current, actual input voltage, and actual output voltage, the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip can be determined simultaneously. This eliminates the need to solder different test points or reassemble a new test environment, significantly reducing the testing time for the board-level chip. By adopting the above technical solution, the problem of low testing efficiency of board-level chips in related technologies is solved, achieving the technical effect of improving the testing efficiency of board-level chips.

[0063] In one exemplary embodiment, the control module includes: The first acquisition unit is configured to acquire a reference test voltage from a set of reference test voltages as the test voltage, wherein the set of reference test voltages includes one or more of the reference test voltages; The first control unit is used to control the power supply device connected to the power input terminal of the board-level chip under test to output the test voltage.

[0064] In one exemplary embodiment, the apparatus further includes: The second acquisition module is used to acquire the normal operating voltage corresponding to the board-level chip before acquiring a reference test voltage from the reference test voltage set as the test voltage, wherein the normal operating voltage is the voltage that the board-level chip is allowed to be loaded when it is working normally; The first generation module is used to generate one or more reference test voltages based on the normal operating voltage and the first preset ratio, thereby obtaining the reference test voltage set.

[0065] In one exemplary embodiment, the first generation module includes at least one of the following: The first execution unit is configured to perform an addition operation on the normal operating voltage and the first target voltage amplitude to obtain the maximum chip voltage; and to determine the maximum chip voltage as the reference test voltage, wherein the first target voltage amplitude is the product of the normal operating voltage and the first preset ratio; The second execution unit is used to perform a subtraction operation on the normal operating voltage and the first target voltage amplitude to obtain the minimum chip voltage; and to determine the minimum chip voltage as the reference test voltage, wherein the first target voltage amplitude is the product of the normal operating voltage and the first preset ratio; The first determining unit is used to determine the normal operating voltage as the reference test voltage.

[0066] In one exemplary embodiment, the determining module includes: The second determining unit is used to determine the difference between the actual input voltage and the actual output voltage as a first difference; and to determine the product of the actual input current and the first difference as the chip loss parameter. The third determining unit is used to determine the product of the test current and the actual output voltage as a first value; to determine the product of the actual input current and the actual input voltage as a second value; and to determine the ratio of the first value and the second value as the chip efficiency parameter. A generation unit is configured to generate a target voltage range based on the test voltage and a second preset ratio, wherein the second preset ratio is less than the first preset ratio; when the actual input voltage falls within the target voltage range, the chip operating parameter is determined as a first operating parameter, wherein the chip operating parameter is the first operating parameter used to indicate that the board-level chip is operating normally; when the actual input voltage does not fall within the target voltage range, the chip operating parameter is determined as a second operating parameter, wherein the chip operating parameter is the second operating parameter used to indicate that the board-level chip is operating abnormally.

[0067] In one exemplary embodiment, the generating unit is further configured to: The test voltage and the second target voltage amplitude are added together to obtain the first target voltage, wherein the second target voltage amplitude is the product of the test voltage and the second preset ratio; The test voltage and the second target voltage amplitude are subtracted to obtain the second target voltage, wherein the second target voltage amplitude is the product of the test voltage and the second preset ratio; The target voltage range is generated based on the first target voltage and the second target voltage, wherein the upper limit of the target voltage range is the first target voltage and the lower limit of the target voltage range is the second target voltage.

[0068] In one exemplary embodiment, the control module includes: The second acquisition unit is used to sequentially acquire a reference test current from the reference test current set as the test current, wherein the reference test current set includes one or more reference test currents; The second control unit is used to control the current value on the load device connected to the power output terminal of the board-level chip to reach the test current.

[0069] In one exemplary embodiment, the apparatus further includes: The third acquisition module is used to acquire the maximum load current before acquiring a reference test current from the set of reference test currents as the test current; The second generation module is used to generate N reference test currents based on the maximum load current and a preset percentage sequence to obtain the reference test current set. The percentage sequence includes N percentages, is an arithmetic sequence, the percentage of the largest term in the percentage sequence is 100%, the percentage of the smallest term in the percentage sequence is 0%, and N is a positive integer greater than 2.

[0070] In one exemplary embodiment, the second generation module includes: The multiplication unit is used to sequentially multiply the maximum load current by each of the percentages in the percentage series to obtain N reference test currents.

[0071] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0072] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0073] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0074] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0075] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0076] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0077] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for testing board-level chips, characterized in that, include: Obtain a reference test voltage from the reference test voltage set as the test voltage, and repeat the following steps until the maximum chip voltage, normal operating voltage, and minimum chip voltage included in the reference test voltage set have all been used as test voltages. The maximum chip voltage is the maximum voltage value allowed to be applied to the board-level chip under test, the minimum chip voltage is the minimum voltage value allowed to be applied to the board-level chip, and the normal operating voltage is the voltage allowed to be applied when the board-level chip is operating normally. The following steps are repeated until one or more of the reference test currents in the reference test current set have been used as the test current, wherein one or more of the reference test currents are less than or equal to the maximum load current, which is the maximum current value allowed to be loaded by the load device connected to the power output terminal of the board-level chip; the power supply device connected to the power input terminal of the board-level chip is controlled to output the test voltage, and the current value on the load device is controlled to reach the test current; the actual input voltage and actual input current of the power input terminal under the test voltage and the test current are obtained, and the actual output voltage of the power output terminal is obtained; the next reference test current is obtained from the reference test current set as the test current; the next reference test voltage is obtained from the reference test voltage set as the test voltage; Based on the test current, the actual input current, the actual input voltage, and the actual output voltage, the chip loss parameter, chip efficiency parameter, and chip operating parameter of the board-level chip are determined, wherein the chip loss parameter is used to indicate the power loss of the board-level chip, the chip efficiency parameter is used to indicate the power efficiency of the board-level chip, and the chip operating parameter is used to indicate the operating status of the board-level chip. The chip operating parameters are determined based on the test current, the actual input current, the actual input voltage, and the actual output voltage, including: A target voltage range is generated based on the test voltage and a second preset ratio, wherein the second preset ratio is less than a first preset ratio. The maximum chip voltage and the minimum chip voltage are generated based on the normal operating voltage and the first preset ratio. If the actual input voltage falls within the target voltage range, the chip operating parameter is determined as a first operating parameter, which indicates that the board-level chip is operating normally. If the actual input voltage does not fall within the target voltage range, the chip operating parameter is determined as a second operating parameter.

2. The method according to claim 1, characterized in that, Before obtaining a reference test voltage from the set of reference test voltages as the test voltage, the method further includes: Obtain the normal operating voltage; One or more reference test voltages are generated based on the normal operating voltage and the first preset ratio to obtain the reference test voltage set.

3. The method according to claim 2, characterized in that, The step of generating one or more reference test voltages based on the normal operating voltage and the first preset ratio includes at least one of the following: The normal operating voltage and the first target voltage amplitude are added together to obtain the maximum chip voltage; the maximum chip voltage is determined as the reference test voltage, wherein the first target voltage amplitude is the product of the normal operating voltage and the first preset ratio; The minimum chip voltage is obtained by subtracting the normal operating voltage from the first target voltage amplitude; the minimum chip voltage is determined as the reference test voltage, wherein the first target voltage amplitude is the product of the normal operating voltage and the first preset ratio; The normal operating voltage is determined as the reference test voltage.

4. The method according to claim 2, characterized in that, The chip loss parameters and chip efficiency parameters are determined based on the test current, the actual input current, the actual input voltage, and the actual output voltage, including: The difference between the actual input voltage and the actual output voltage is determined as the first difference; the product of the actual input current and the first difference is determined as the chip loss parameter. The product of the test current and the actual output voltage is determined as a first value; the product of the actual input current and the actual input voltage is determined as a second value; the ratio of the first value and the second value is determined as the chip efficiency parameter. The chip operating parameters are the second operating parameters used to indicate that the operating status of the board-level chip is abnormal.

5. The method according to claim 1, characterized in that, The step of generating the target voltage range based on the test voltage and the second preset ratio includes: The test voltage and the second target voltage amplitude are added together to obtain the first target voltage, wherein the second target voltage amplitude is the product of the test voltage and the second preset ratio; The second target voltage is obtained by subtracting the test voltage and the amplitude of the second target voltage. The target voltage range is generated based on the first target voltage and the second target voltage, wherein the upper limit of the target voltage range is the first target voltage and the lower limit of the target voltage range is the second target voltage.

6. The method according to claim 1, characterized in that, Before sequentially obtaining a reference test current from the set of reference test currents as the test current, the method further includes: Obtain the maximum load current; N reference test currents are generated based on the maximum load current and a preset percentage sequence to obtain the reference test current set. The percentage sequence includes N percentages, is an arithmetic sequence, the percentage of the largest term in the percentage sequence is 100%, the percentage of the smallest term in the percentage sequence is 0%, and N is a positive integer greater than 2.

7. The method according to claim 6, characterized in that, The process of generating N reference test currents based on the maximum load current and a preset percentage sequence includes: The maximum load current is multiplied sequentially by each percentage in the percentage series to obtain N reference test currents.

8. A board-level chip testing device, characterized in that, include: The control module is configured to: obtain a reference test voltage from a set of reference test voltages as the test voltage, and repeat the following steps until the maximum chip voltage, normal operating voltage, and minimum chip voltage included in the set of reference test voltages have all been used as the test voltages, wherein the maximum chip voltage is the maximum voltage value allowed to be applied on the board-level chip under test, the minimum chip voltage is the minimum voltage value allowed to be applied on the board-level chip, and the normal operating voltage is the voltage allowed to be applied when the board-level chip is operating normally; and sequentially obtain a reference test current from a set of reference test currents as the test current, and repeat the following steps until one or more of the reference test currents included in the set of reference test currents have all been used as the test voltages. The test current is applied, wherein one or more of the reference test currents are less than or equal to the maximum load current, the maximum load current being the maximum current value allowed to be loaded by the load device connected to the power output terminal of the board-level chip; the power supply device connected to the power input terminal of the board-level chip is controlled to output the test voltage, and simultaneously, the current value on the load device is controlled to reach the test current; the actual input voltage and actual input current of the power input terminal under the test voltage and the test current are obtained, and the actual output voltage on the power output terminal is also obtained; the next reference test current is obtained from the set of reference test currents as the test current; the next reference test voltage is obtained from the set of reference test voltages as the test voltage; The determination module is used to determine the chip loss parameters, chip efficiency parameters, and chip operating parameters of the board-level chip based on the test current, the actual input current, the actual input voltage, and the actual output voltage, wherein the chip loss parameters are used to indicate the power loss of the board-level chip, the chip efficiency parameters are used to indicate the power efficiency of the board-level chip, and the chip operating parameters are used to indicate the operating status of the board-level chip. The determining module includes: a generation unit, configured to generate a target voltage range based on the test voltage and a second preset ratio, wherein the second preset ratio is less than a first preset ratio, wherein the maximum chip voltage and the minimum chip voltage are generated based on the normal operating voltage and the first preset ratio; when the actual input voltage falls within the target voltage range, the chip operating parameter is determined as a first operating parameter, wherein the chip operating parameter is the first operating parameter used to indicate that the board-level chip is operating normally; when the actual input voltage does not fall within the target voltage range, the chip operating parameter is determined as a second operating parameter.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein the program, when executed, performs the method of any one of claims 1 to 7.

10. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to execute the method of any one of claims 1 to 7 through the computer program.

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