A system and method for achieving dual-path interconnection based on Loongson processor and backplane

Abstract

This invention discloses a system for dual-path interconnection based on a Loongson processor and a backplane, comprising two communication sub-modules and two interconnected motherboards corresponding to the two communication sub-modules. Each communication sub-module includes a processor, a bridge chip, a power module, and an embedded controller (EC) connected in sequence. Each communication sub-module also includes a baseboard management controller (BMC), which is connected to the processor, bridge chip, and embedded controller (EC). The BMC is used to acquire the access status of the two processors in the two communication sub-modules with their respective motherboards, and to control the configuration mode of the processors in their respective communication sub-modules based on the processor access status, thereby achieving single-path configuration or dual-path interconnection configuration. This invention solves the problem of multi-path interconnection in ruggedized servers due to limited motherboard space, and realizes the requirement for multi-path concurrent operation between processors in the ruggedized field.

Description

Technical Field

[0001] This invention belongs to the field of computer science, specifically relating to a system and method for achieving dual-path interconnection based on a Loongson processor and a backplane. Background Technology

[0002] With strong support from relevant national policies, secure computers based on domestically produced CPUs have developed rapidly. As one of the core components of a server, the CPU (Central Processing Unit) is responsible for performing computational tasks and processing data. To enhance the processor's processing power, CPUs are typically interconnected to improve multi-processor concurrent computing capabilities. Taking the existing domestically produced Loongson 3C5000 CPU as an example, dual-processor interconnection in rack-mount servers is mainly achieved by placing two 3C5000 CPU chips on a single server motherboard and interconnecting them via a high-speed bus. This solution has become a mature and mature approach.

[0003] However, its application in the field of ruggedized servers is relatively limited. The main reason is that the server motherboard in ruggedized servers is a standard 6U VPX module, while the existing CPU chips have a large package size. Therefore, a standard 6U VPX module cannot simultaneously accommodate two Loongson 3C5000 CPUs for interconnection between processors. Summary of the Invention

[0004] This invention addresses the problems of existing technologies by proposing a system and method for achieving dual-path interconnection based on a Loongson processor and a backplane. It interconnects two 6U VPX modules with a single multi-core Loongson processor via a backplane. During application, the BMC automatically identifies whether the other Loongson 3C5000 module is present in the dual-path interconnection slot on the backplane and automatically interconnects it, thereby achieving dual-path interconnection in ruggedized applications, enabling multi-path concurrent operation, and ultimately improving the overall performance of the server.

[0005] This invention is achieved through the following technical solution:

[0006] A system based on a Loongson processor and a backplane to achieve dual-path interconnection includes two communication sub-modules and two interconnected motherboards corresponding to the two communication sub-modules. Each communication sub-module includes a processor, a bridge chip, a power module, and an embedded controller (EC) connected in sequence. Each communication sub-module also includes a baseboard management controller (BMC). The baseboard management controller (BMC) is connected to the processor, the bridge chip, and the embedded controller (EC) respectively. The baseboard management controller (BMC) is used to obtain the access status of the two processors in the two communication sub-modules with their respective corresponding motherboards, and control the configuration mode of the processors in their respective communication sub-modules based on the processor access status to achieve single-path configuration or dual-path interconnection configuration.

[0007] Preferably, it also includes a backplate, which has two interconnect slots for connecting to the two motherboards, and each interconnect slot has a slot identifier.

[0008] Preferably, the Baseboard Management Controller (BMC) specifically controls the configuration mode of the processors in their respective communication sub-modules and the bus connecting the processors to the motherboard based on the processor access status, so as to realize single-channel configuration or dual-channel interconnection configuration.

[0009] Preferably, when the access state is a single board insertion, the Baseboard Management Controller (BMC) will control the CPU_DEV_CONFIG9 pin, CPU_CHIP_CONFIG2 pin, CPU_CHIP_CONFIG3 pin, CPU_ICCC_EN pin, and CPU_CHID_ID0 pin of the processor corresponding to the accessed motherboard to be at a low level, the bus HT0 to be enabled, and the bus HT1 to be disabled.

[0010] Preferably, when the access state is dual board insertion, the baseboard management controller (BMC) determines whether the communication submodule connected to each interconnect slot is a master communication submodule or a slave communication submodule based on the slot identifier, and performs dual-path interconnection configuration based on the master-slave relationship.

[0011] Preferably, the dual-path interconnection configuration specifically includes:

[0012] When the connected communication submodule is the main communication submodule: configure the CPU_DEV_CONFIG9 pin, CPU_CHIP_CONFIG2 pin, CPU_CHIP_CONFIG3 pin, CPU_ICCC_EN pin, and CPU_CHID_ID0 pin of the processor corresponding to the main communication submodule to a high level, and enable the bus HT0 and disable the bus HT1.

[0013] When the accessed communication submodule is a slave communication submodule: the CPU_DEV_CONFIG9 pin, CPU_CHIP_CONFIG2 pin, CPU_CHIP_CONFIG3 pin, CPU_ICCC_EN pin, and CPU_CHID_ID0 pin of the processor corresponding to the slave communication submodule are configured to be high, bus HT0 is disabled, and bus HT1 is enabled.

[0014] A method for implementing dual-path interconnection based on a Loongson processor and a backplane includes the following steps:

[0015] S1. Obtain the connection status of the two processors and their respective motherboards in the two communication submodules;

[0016] S2. Based on the processor access status in the two communication submodules, control the configuration mode of the processor in each corresponding communication submodule to achieve single-path configuration or dual-path interconnection configuration.

[0017] Preferably, in step S2, when the access state is single-board insertion, the processor is configured for single-path operation; when the access state is dual-board insertion, the processor is configured for dual-path interconnection.

[0018] Preferably, the dual-path interconnection configuration specifically includes:

[0019] When two boards are inserted, the connected communication submodule is identified and determined to be either the master or slave communication submodule, and dual-path interconnection configuration is performed based on the master-slave relationship.

[0020] The system and method for achieving dual-path interconnection based on Loongson processor and backplane described above have the following advantages and significant effects compared with existing technologies:

[0021] I. This invention solves the problem of multi-processor interconnection in ruggedized servers due to limited motherboard space, and realizes the multi-processor concurrent operation requirements in the field of ruggedization; at the same time, the processor can be modularly replaced or repaired.

[0022] Second, this invention achieves dual-path interconnection through two identical boards, avoiding the problems of managing and using multiple boards in a confusing manner. At the same time, it creatively opens up two working modes. It can continue to work when a single motherboard is inserted into the interconnection slot, which satisfies both single-card requirements and dual-card interconnection, thereby improving the overall performance of the server.

[0023] Third, this invention identifies the master-slave relationship between two boards by setting the BMC (Block Controller) configuration based on the interconnect slot, and configures the corresponding boards to achieve the master-slave status setting and realize multi-path concurrent function. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a cascaded block diagram of a system based on a Loongson processor and a backplane to achieve dual-path interconnection according to the present invention;

[0026] Figure 2 This is a flowchart of a method for achieving dual-path interconnection based on a Loongson processor and a backplane according to the present invention;

[0027] Example 1:

[0028] A system based on a Loongson processor and a backplane to achieve dual-path interconnection includes a backplane and two motherboards. The backplane has two interconnection slots, each marked with a slot identifier, designated as the master interconnection slot and the slave interconnection slot, respectively. The two motherboards have two communication submodules interconnected via the interconnection slots. Each communication submodule includes a processor, a bridge chip, a power module, and an embedded controller (EC) connected sequentially. The interconnection submodule also includes a storage device and a memory subunit connected to the processor.

[0029] Specifically, such as Figure 1 As shown, both motherboards are standard 6U VPX motherboards, both processors are Loongson LS3C5000 chipsets, and the bridge chip is an LS7A2000 model. The storage device is an mSATA electronic disk, connected to the LS7A2000 bridge chip via a SATA interface, used to store the operating system; the memory subunit includes FLASH memory for caching boot firmware and 4-channel DDR memory, used to store the boot firmware for initializing the operating system.

[0030] When the system initially boots up, the firmware is loaded into memory and then executed. The main task of this stage is to initialize the hardware devices in the system and prepare other software hierarchies. The firmware also provides interfaces with the operating system and applications so that they can communicate correctly with the hardware. Therefore, this invention is based on implementing a multi-path interconnect configuration between processors in this application scenario.

[0031] In the specific interconnect configuration, this invention is mainly implemented through the Baseboard Management Controller (BMC). Taking one of the two communication sub-modules (left) as an example, the Baseboard Management Controller (BMC1) is connected to the processor CPU1, bridge chip 1 (LS7A2000), and embedded controller EC. The Baseboard Management Controller (BMC1) is also connected to the interconnect slots via the IPMB (Intelligent Platform Management Bus), specifically using two IPMBs. The IPMB provides reliable point-to-point communication, supporting multiple slave devices connected to the master controller. Simultaneously, the interconnect signals in this system are defined as high-speed HT3.0 digital signals. Both the motherboard and backplane use high-speed connectors. The two interconnect slots (master interconnect slot and slave interconnect slot) between the processor and the motherboard both adopt the Loongson 3C5000 HT bus standard for signal transmission and interconnection. Specifically, the HT bus includes HT0 and HT1 buses.

[0032] The Baseboard Management Controller (BMC) controls the configuration mode of the processors in their respective communication submodules and the bus connecting the processors to the motherboard based on the processor access status, thereby achieving single-channel configuration or dual-channel interconnection configuration. When the system is powered on, the BMC determines the motherboard access status, including single-board insertion and dual-board insertion. When a single board is inserted, the corresponding communication mode is single-channel; when two boards are inserted, the corresponding communication mode is dual-channel.

[0033] 1. When the access status is single board insertion, corresponding to single-channel mode (taking the left motherboard insertion as an example): The baseboard management controller BMC1 sets the processor configuration pin to single-channel mode. The specific configuration signal process is as follows:

[0034] A. Configure the CPU_DEV_CONFIG9 pin of CPU1 to a low level to disable the dual-chip interconnect structure;

[0035] B. Configure the CPU_CHIP_CONFIG2 pin of CPU1 to a low level to disable address flattening mode;

[0036] C. Configure the CPU_CHIP_CONFIG3 pin of CPU1 to a high level to enable local boot mode;

[0037] D. Configure the CPU_ICCC_EN pin of CPU1 to a low level to use single-chip mode;

[0038] E. Configure the CPU_CHID_ID0 pin of CPU1 to a low level and configure the chip ID to 0;

[0039] F. Configure both the HT0_LO_LDT_STOPN bus and the HT0_LO_RSTN bus to high level to enable the HT0 bus;

[0040] G. Configure the HT1_LO_LDT_STOPN bus and the HT1_LO_RSTN bus to low level, and turn off the HT1 bus;

[0041] H. Inform EC1 via BMC1's GPIO / serial port that it is currently in single-channel mode, and EC1 will control the power supply to power on.

[0042] I. Power on and enter single-channel mode.

[0043] Since the left and right modules are exactly the same, the same applies if the motherboard on the right is connected to the slot on the right, so I will not go into details.

[0044] II. When the access status is dual-board insertion, specifically: By identifying the slot identifiers set at the interconnect slots, the Baseboard Management Controller (BMC) determines whether the motherboards on both interconnect slots are plugged into the interconnect slots through communication with the interconnect slots. At this time, the transmission adopts a master-slave architecture. The master controller sends commands, and the slave device executes the corresponding operations according to the commands and returns a response. Therefore, the Baseboard Management Controller (BMC) determines whether the communication submodule connected to each interconnect slot is a master or slave communication submodule based on the slot identifiers, and performs dual-path interconnection configuration based on the master-slave relationship.

[0045] The left-hand module is the primary configuration, and the right-hand module is the secondary configuration, as follows:

[0046] 1. The processor configuration corresponding to the main communication submodule is as follows:

[0047] A. Configure CPU1's CPU_DEV_CONFIG9 to high level and use a dual-chip interconnect structure;

[0048] B. Configure CPU1's CPU_CHIP_CONFIG2 to high level and use address flattening mode;

[0049] C. Configure CPU1's CPU_CHIP_CONFIG3 to high level and use local boot mode;

[0050] D. Configure CPU1's CPU_ICCC_EN to high level for multi-chip coherent interconnection mode;

[0051] E. Configure the CPU_CHID_ID0 pin of CPU1 to a low level and configure the chip ID to 0;

[0052] F. Configure the HT0_LO_LDT_STOPN and HT0_LO_RSTN buses to high level to enable the HT0 bus;

[0053] G. Configure the HT1_LO_LDT_STOPN and HT1_LO_RSTN buses to high level to enable the HT1 bus;

[0054] H. Inform EC1 that it is currently in motherboard card mode via BMC1's GPIO / serial port, and EC1 will control the power supply to power on.

[0055] 2. The communication processor is configured as follows:

[0056] A. Configure CPU2's DEV_CONFIG9 to high level and use a dual-chip interconnect structure;

[0057] B. Configure CPU2's CHIP_CONFIG2 to high level and use address flattening mode;

[0058] C. Configure CPU2's CHIP_CONFIG3 to high level to use local boot mode;

[0059] D. Configure CPU2's ICCC_EN to high level and use multi-chip coherent interconnect mode;

[0060] E. Configure the CHID_ID of CPU2 to a high level;

[0061] F. Connect the HT0_LO_LDT_STOPN and HT0_LO_RSTN buses to CPU2.

[0062] Configure to low level to disable the HTO bus;

[0063] G. Configure the processor (right side) and HT1_LO_LDT_STOPN and HT1_LO_RSTN of the interconnect slot to high level to enable the HT1 bus;

[0064] H. Inform EC2 that it is currently in motherboard mode via BMC2's GPIO / serial port, and EC2 will control the power supply to power on.

[0065] Simultaneously, clock synchronization settings are configured for the main communication processor and the slave communication processor to achieve a dual-channel cascaded synchronization mode.

[0066] A. Design the CPU CLK of CPU1 and CPU2 to be of the same source, and use the motherboard card clock to provide the clock to CPU1 and CPU2 respectively through the backplane to achieve the effect of clock coherence.

[0067] B. Configure the LS7A2000 connected to CPU1, specifically by resetting CPU1 and CPU2 via its PLT_RST pin;

[0068] C. Connect the output of GPIO12 pin of CPU1 to GPIO13 pin of CPU1 and GPIO13 pin of CPU2 to reset the processor and stabilize the clock count.

[0069] Through the master-slave configuration and synchronization timing design described above, dual-path cascading was completed.

[0070] Example 2:

[0071] A method for achieving dual-path interconnection based on a Loongson processor and a backplane, based on the system for achieving dual-path interconnection based on a Loongson processor and a backplane described in Embodiment 1, includes the following steps:

[0072] S1. Obtain the connection status of the two processors and their respective motherboards in the two communication submodules;

[0073] S2. Based on the processor access status in the two communication submodules, control the configuration mode of the processor in each corresponding communication submodule to achieve single-path configuration or dual-path interconnection configuration.

[0074] Specifically, the configuration mode of the processor and the bus connecting the processor and the motherboard in the corresponding communication submodule is controlled based on the processor access status to achieve single-channel configuration or dual-channel interconnection configuration.

[0075] ① When the access status is single-board insertion, the processor is configured as a single channel, as follows:

[0076] A. Configure CPU_DEV_CONFIG9 to low level to disable the dual-chip interconnect structure;

[0077] B. Use BMC to configure CPU_CHIP_CONFIG2 to low level to disable address flattening mode;

[0078] C. Use BMC to configure CPU_CHIP_CONFIG3 to high level to enable local boot mode;

[0079] D. Use BMC to configure CPU_ICCC_EN to low level and use single-chip mode;

[0080] E. Use BMC to configure CPU_CHID_ID0 to low level and configure chip ID to 0;

[0081] F. Use BMC to configure HT0_LO_LDT_STOPN and HT0_LO_RSTN to high level to enable the HT0 bus;

[0082] G. Use BMC to configure HT1_LO_LDT_STOPN and HT1_LO_RSTN to low level to turn off the HT1 bus;

[0083] H. Inform EC1 via BMC1's GPIO / serial port that it is currently in single-channel mode, and EC1 will control the power supply to power on.

[0084] I. Power on and enter single-channel mode.

[0085] ② When two boards are inserted, the connected communication submodule is also identified and determined to be either the master or slave communication submodule. Based on the master-slave relationship, dual-path interconnection is configured, as follows:

[0086] The processor corresponding to the main interconnect slot:

[0087] A. Use BMC to configure CPU1's CPU_DEV_CONFIG9 to a high level, and use a dual-chip interconnect structure;

[0088] B. Use BMC to configure CPU1's CPU_CHIP_CONFIG2 to high level, using address flattening mode;

[0089] C. Use BMC to configure CPU1's CPU_CHIP_CONFIG3 to high level and use local boot mode;

[0090] D. Use BMC to configure CPU1's CPU_ICCC_EN to high level and use multi-chip coherent interconnect mode;

[0091] E. Use BMC to set CPU1's CPU_CHID_ID0 to low level, and configure the chip ID to 0.

[0092] F. Use BMC to configure the HT0_LO_LDT_STOPN and HT0_LO_RSTN buses of CPU1 to high level, and enable the HT0 bus;

[0093] G. Use BMC to configure HT1_LO_LDT_STOPN and HT1_LO_RSTN of CPU1 to high level to enable the HT1 bus;

[0094] H. Inform the EC that it is currently in motherboard card mode via the BMC's GPIO / serial port, and the EC will control the power supply to turn on the device.

[0095] From the processor corresponding to the interconnect slot:

[0096] A. Use BMC to configure CPU2's CPU's DEV_CONFIG9 to a high level, and use a dual-chip interconnect structure.

[0097] B. Use BMC to configure CPU2's CHIP_CONFIG2 to a high level and use address flattening mode;

[0098] C. Use BMC to configure the CPU2's CHIP_CONFIG3 to a high level and use the local boot mode;

[0099] D. Use BMC to configure the CPU2's CPU ICCC_EN to high level and use the multi-chip coherent interconnect mode;

[0100] E. Use BMC to configure CPU2's CPU_CHID_ID0 to high level, and configure the chip ID to 1.

[0101] F. Use BMC to configure the HT0_LO_LDT_STOPN and HT0_LO_RSTN main lines of CPU2 to low level, and turn off the HT0 bus;

[0102] G. Use BMC to configure HT1_LO_LDT_STOPN and HT1_LO_RSTN of CPU2 to high level, enabling the HT1 bus.

[0103] H. Inform the EC that it is currently in slave mode via the BMC's GPIO serial port, and the EC will control the power supply to turn on the device.

[0104] Simultaneously, a dual-path cascade synchronization mode is configured for the master and slave processors:

[0105] A. Design the CPU CLK of CPU1 and CPU2 to be of the same source, and use the motherboard card clock to provide the clock to CPU1 and CPU2 respectively through the backplane to achieve clock coherence.

[0106] B. Configure the PLT_RST of the 7A2000 bridge chip of CPU1 to reset the processors corresponding to the main interconnect slot and the processors corresponding to the slave interconnect slot;

[0107] C. Connect the GPIO12 output pin of the processor corresponding to the main interconnect slot to the GPIO13 pin of the processor corresponding to the main interconnect slot and the processor corresponding to the slave interconnect slot to reset the stable clock count of the processor core.

[0108] Through the master-slave configuration and synchronization timing design described above, dual-path cascading was completed.

[0109] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope of the present invention.

Claims

1. A system for dual-path interconnection based on a Loongson processor and a backplane, characterized in that, The system includes two communication submodules and two interconnected motherboards corresponding to the two communication submodules. Each communication submodule includes a processor, a bridge chip, a power module, and an embedded controller (EC) connected in sequence. Each communication submodule also includes a baseboard management controller (BMC). The baseboard management controller (BMC) is connected to the processor, the bridge chip, and the embedded controller (EC). The baseboard management controller (BMC) is used to obtain the access status of the two processors in the two communication submodules and their respective corresponding motherboards, and to control the configuration mode of the processors in their respective communication submodules based on the processor access status, so as to realize single-channel configuration or dual-channel interconnection configuration.

2. The system for dual-path interconnection based on a Loongson processor and backplane according to claim 1, characterized in that, It also includes a backplate, which has two interconnect slots for connecting to the two motherboards, and each interconnect slot has a slot identifier.

3. The system for dual-path interconnection based on a Loongson processor and backplane according to claim 1, characterized in that, Specifically, the Baseboard Management Controller (BMC) controls the configuration mode of the processors in their respective communication sub-modules and the bus connecting the processors to the motherboard based on the processor access status, so as to achieve single-channel configuration or dual-channel interconnection configuration.

4. A system for dual-path interconnection based on a Loongson processor and backplane according to claim 3, characterized in that, When the access state is a single board insertion, the Baseboard Management Controller (BMC) will control the CPU_DEV_CONFIG9 pin, CPU_CHIP_CONFIG2 pin, CPU_CHIP_CONFIG3 pin, CPU_ICCC_EN pin, and CPU_CHID_ID0 pin of the processor corresponding to the accessed motherboard to be at a low level, the bus HT0 to be enabled, and the bus HT1 to be disabled.

5. A system for dual-path interconnection based on a Loongson processor and a backplane according to claim 2 or 4, characterized in that, When the access state is dual board insertion, the Baseboard Management Controller (BMC) determines whether the communication submodule connected to each interconnect slot is a master communication submodule or a slave communication submodule based on the slot identifier, and performs dual-path interconnection configuration based on the master-slave relationship.

6. A system for dual-path interconnection based on a Loongson processor and backplane according to claim 5, characterized in that, The dual-path interconnection configuration is specifically as follows: When the accessed communication submodule is the main communication submodule: configure the CPU_DEV_CONFIG9 pin, CPU_CHIP_CONFIG2 pin, CPU_CHIP_CONFIG3 pin, CPU_ICCC_EN pin, and CPU_CHID_ID0 pin of the processor corresponding to the main communication submodule to a high level, and enable bus HT0 and disable bus HT1; When the accessed communication submodule is a slave communication submodule: the CPU_DEV_CONFIG9 pin, CPU_CHIP_CONFIG2 pin, CPU_CHIP_CONFIG3 pin, CPU_ICCC_EN pin, and CPU_CHID_ID0 pin of the processor corresponding to the slave communication submodule are configured to be high, bus HT0 is disabled, and bus HT1 is enabled.

7. A method for achieving dual-path interconnection based on a Loongson processor and a backplane, based on the system for achieving dual-path interconnection based on a Loongson processor and a backplane as described in any one of claims 1 to 6, characterized in that, Including the following steps: S1. Obtain the connection status of the two processors and their respective motherboards in the two communication submodules; S2. Based on the processor access status in the two communication submodules, control the configuration mode of the processor in each corresponding communication submodule to achieve single-path configuration or dual-path interconnection configuration.

8. The method for achieving dual-path interconnection based on a Loongson processor and a backplane according to claim 7, characterized in that, Step S2 specifically includes: Based on the processor access status control, the configuration mode of the processor in each corresponding communication submodule and the bus used to connect the processor and the motherboard can be controlled to achieve single-channel configuration or dual-channel interconnection configuration.

9. A method for implementing dual-path interconnection based on a Loongson processor and a backplane according to claim 8, characterized in that, In step S2, when the access state is single-board insertion, the processor is configured for single-path operation; when the access state is dual-board insertion, the processor is configured for dual-path interconnection.

10. A method for implementing dual-path interconnection based on a Loongson processor and a backplane according to claim 9, characterized in that, The dual-path interconnection configuration is specifically as follows: When two boards are inserted, the connected communication submodule is identified and determined to be either the master or slave communication submodule, and dual-path interconnection configuration is performed based on the master-slave relationship.

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