Block management method, memory storage device, and memory controller

Abstract

The application provides a block management method, a memory storage device and a memory controller for controlling a memory module, wherein the memory module comprises a plurality of physical groups, each physical group comprises a plurality of physical blocks belonging to different memory planes, each physical block comprises a plurality of physical pages, the block management method comprises obtaining the number of valid data of each physical block in each physical group, and obtaining the total number of valid data of each physical group according to the number of valid data of each physical block; when performing a garbage collection operation, obtaining a target physical group according to the total number of valid data; judging whether to perform a replacement operation on a first physical block in the target physical group according to whether the valid data proportion of the first physical block is greater than a threshold value; and in response to the valid data proportion of the first physical block being greater than the threshold value, replacing the first physical block with an empty physical block of another physical group in the plurality of physical groups.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a block management method, a memory storage device, and a memory controller. Background Technology

[0002] Solid State Drive (SSD) is a hard drive made of solid-state electronic storage chip arrays. The storage unit of an SSD consists of flash memory blocks, and a flash memory block can be divided into several data pages.

[0003] During SSD use, new data is constantly generated. In this process, the existing data needs to be updated accordingly. The old data automatically becomes garbage data, and the updated data becomes valid data. The page containing the valid data is called the valid data page. When the available space on the SSD is insufficient, old flash memory blocks need to be reclaimed. This involves moving the valid data pages from the old flash memory blocks to new flash memory blocks. After the valid data migration is complete, the entire old flash memory block is erased, freeing it up for writing new data.

[0004] Currently, the garbage collection process for old flash memory blocks first involves traversing the data across all flash memory blocks to find the valid data pages in each block, moving the valid data from those pages to other flash memory blocks, and then erasing one of the aforementioned flash memory blocks. This garbage collection process consumes significant resources and impacts system performance. Summary of the Invention

[0005] This invention provides a block management method, a memory storage device, and a memory controller, which can reduce write amplification during the garbage collection process of the memory storage device, thereby extending the service life of the memory storage device.

[0006] Embodiments of the present invention provide a block management method, wherein the method is used to control a memory module, wherein the memory module includes multiple entity groups, each entity group includes multiple entity blocks belonging to different memory planes, each entity block includes multiple entity pages, and the block management method includes obtaining the number of valid data in each entity block in each entity group, and obtaining the total number of valid data in each entity group based on the number of valid data in each entity block; when performing a garbage collection operation, obtaining a target entity group based on the total number of valid data; determining whether to perform a replacement operation on the first entity block based on whether the percentage of valid data in the first entity block in the target entity group is greater than a threshold; and in response to the percentage of valid data in the first entity block being greater than the threshold, replacing the first entity block with an empty entity block in another entity group among the multiple entity groups.

[0007] Embodiments of the present invention provide a memory storage device, including a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory module includes multiple entity groups, each entity group including multiple entity blocks belonging to different memory planes, and each entity block including multiple entity pages. The memory controller is connected to the connection interface and the memory module, wherein the memory controller is used to obtain the number of valid data in each entity block in each entity group, and to obtain the total number of valid data in each entity group based on the number of valid data in each entity block. During garbage collection, the memory controller is used to obtain a target entity group based on the total number of valid data. The memory controller is used to determine whether to perform a replacement operation on the first entity block based on whether the percentage of valid data in the first entity block in the target entity group is greater than a threshold. In response to the percentage of valid data in the first entity block being greater than the threshold, the memory controller is used to replace the first entity block with an empty entity block in another entity group among the multiple entity groups.

[0008] Embodiments of the present invention provide a memory controller, comprising a host interface, a memory interface, an error checking and correction circuit, and a memory control circuit. The host interface is used to connect to a host system. The memory interface is used to connect to a memory module, wherein the memory module includes multiple entity groups, each entity group includes multiple entity blocks belonging to different memory planes, and each entity block includes multiple entity pages. The memory control circuit is connected to the host interface, the memory interface, and the error checking and correction circuit, wherein the memory control circuit is used to obtain the number of valid data entries in each entity block within each entity group, and to obtain the total number of valid data entries in each entity group based on the number of valid data entries in each entity block. During garbage collection, the memory control circuit obtains a target entity group based on the total number of valid data entries; the memory control circuit determines whether to perform a replacement operation on the first entity block based on whether the percentage of valid data entries in the first entity block of the target entity group is greater than a threshold; in response to the percentage of valid data entries in the first entity block being greater than the threshold, the memory control circuit replaces the first entity block with an empty entity block in another entity group among the multiple entity groups.

[0009] Based on the above, the present invention provides a block management method, a memory storage device, and a memory controller. During the garbage collection process, a first entity block containing valid data in a target entity group is replaced with an empty entity block without valid data in another entity group. Valid data stored in other entity blocks in the target entity group is then moved to entity blocks in other entity groups, and the target entity group is erased. This reduces write amplification during the garbage collection process, thereby extending the lifespan of the memory storage device.

[0010] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0012] Figure 1 This is a schematic diagram of a memory storage device according to an embodiment of the present invention;

[0013] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0014] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0015] Figure 4 This is a schematic diagram of an entity group according to an embodiment of the present invention;

[0016] Figure 5 This is a schematic diagram of a VC table according to an embodiment of the present invention;

[0017] Figure 6 This is a schematic diagram of a three-level page table paging according to an embodiment of the present invention;

[0018] Figure 7 This is a schematic diagram of a RUT table according to an embodiment of the present invention;

[0019] Figure 8 This is a flowchart illustrating a block management method according to an embodiment of the present invention;

[0020] Figure 9 This is a flowchart illustrating the use of a RUT table to perform a replacement operation on a first entity block according to an embodiment of the present invention. Detailed Implementation

[0021] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0022] Figure 1 This is a schematic diagram of a memory storage device according to an embodiment of the present invention. Please refer to... Figure 1The memory storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 can be any type of computer system. For example, the host system 11 can be a laptop computer, desktop computer, smartphone, tablet computer, industrial computer, etc. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 may include a solid-state drive, USB flash drive, or other types of non-volatile storage devices. The host system 11 can be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCI Express), Universal Serial Bus (USB), or other types of connection interfaces. Therefore, the host system 11 can store data to and / or read data from the memory storage device 12.

[0023] The memory storage device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 may support connection interface standards such as SATA, PCI Express, or USB. The memory storage device 12 can communicate with the host system 11 via the connection interface 121.

[0024] Memory module 122 is used to store data. Memory module 122 may include a rewritable non-volatile memory module. Memory module 122 includes a memory cell array. The memory cells in memory module 122 store data in the form of voltage. For example, memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quadruple-level cell (QLC) NAND flash memory module, a 3D NAND flash memory module (which may have multiple triple-level or quadruple-level memory cells), or other memory modules with similar characteristics.

[0025] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be used to control memory storage device 12. For example, memory controller 123 can control connection interface 121 and memory module 122 for data access and data management. For example, memory controller 123 may include a central processing unit (CPU), graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices.

[0026] In one embodiment, the memory controller 123 is also referred to as a flash memory controller. In another embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 can receive a sequence of instructions from the memory controller 123 and access data stored in the memory cells according to the sequence of instructions.

[0027] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 for communication with the host system 11. The memory interface 22 is used to connect to the memory module 122 for communication with the memory module 122.

[0028] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. The memory control circuit 23 can also be considered the control core of the memory controller 123. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123. Furthermore, the memory control circuit 23 may include one or more buffer memories for temporarily storing data.

[0029] In one embodiment, the memory controller 123 further includes error checking and correction circuitry 24, buffer memory 25, and power management circuitry 26.

[0030] Error checking and correction circuit 24 is coupled to memory control circuit 23 and is used to perform error checking and correction procedures to ensure data integrity. Specifically, when memory control circuit 23 receives a write command from host system 11, error checking and correction circuit 24 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory control circuit 23 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into memory module 122. Subsequently, when memory control circuit 23 reads data from memory module 122, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 24 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0031] In one embodiment, the error checking and correction circuit 24 can perform single-frame encoding on data stored in the same entity unit, or multi-frame encoding on data stored in multiple entity units. Single-frame encoding and multi-frame encoding can respectively employ at least one of the following encoding algorithms: low-density parity code (LDPC), BCH code, convolutional code, or turbo code. Alternatively, in one embodiment, multi-frame encoding can also employ Reed-Solomon codes (RS codes) or XOR algorithms. Furthermore, in another embodiment, more encoding algorithms not listed above can be used, which will not be elaborated here. Depending on the encoding algorithm employed, the error checking and correction circuit 24 can encode the data to be protected to generate corresponding error correction codes and / or error checking codes.

[0032] Buffer memory 25 is coupled to memory control circuit 23 and is used to temporarily store data and instructions from host system 11 or data from memory module 122. Power management circuit 26 is coupled to memory control circuit 23 and is used to control the power supply of memory storage device 12.

[0033] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 3The memory module 122 includes multiple physical units 301(0) to 301(C). Each physical unit includes multiple memory cells for non-volatile data storage. Multiple physical units can form a physical block. Multiple physical units (or memory cells) in a physical block can be erased simultaneously. Furthermore, the memory control circuit 23 can configure multiple logic units 311(0) to 311(D) to map at least some of the physical units. For example, a logic unit can consist of one or more logic addresses. The mapping relationship between logic units and physical units can be recorded in a logic-to-physical mapping table.

[0034] In one embodiment, the memory module 122 is logically divided into a data area 310, an idle area 320, and a system area 330. Logically, physical units 301(1) to 301(A) belonging to the data area 310 store data (also called user data) from the host system 11. That is, when a write command and data to be written are received from the host system 11, the memory control circuit 23 extracts a physical block from the idle area 320 and writes (or programs) the data into the extracted physical block to replace the physical block in the data area 310. Physical units in the data area 310 are associated with the idle area 320 after being erased. In other words, physical units 301(A+1) to 301(B) in the idle area 320 have all been erased and do not store valid data. Multiple physical units in the idle area 320 can form an idle physical block.

[0035] Logically, physical units 301(B+1) to 301(C) belonging to the system area 330 are used to record system data. For example, system data includes information about the memory module's manufacturer and model, the number of physical blocks in the memory module, and the number of physical units in each physical block. In particular, the number of physical units in the data area 310, idle area 320, and system area 330 may vary depending on the memory specifications.

[0036] Generally, the memory control circuit 23 records the mapping relationship between logic units and physical units in a logic-to-physical mapping table. When the host system 11 wants to read data from or write data to the memory storage device 12, the memory control circuit 23 can access the memory module 122 according to the information in the logic-to-physical mapping table.

[0037] As described above, when executing a write instruction, regardless of which logical unit the data is to be written to, the memory control circuit 23 writes data in a sequential manner, one physical unit after another (also known as a random write mechanism). Specifically, the memory control circuit 23 extracts an empty idle physical block from the idle area 320 as the currently used or active physical block to write data. Furthermore, when this active physical block is full, the memory control circuit 23 extracts another empty idle physical block from the idle area 320 as the active physical block to continue writing data corresponding to the write instruction from the host system 11.

[0038] Figure 4 This is a schematic diagram of a group of entities according to an embodiment of the present invention. The memory module 122 includes multiple chip enablers (also referred to as chip enable groups). For ease of explanation, this embodiment assumes that the memory module 122 includes chip enablers CE(0), CE(1), CE(2), and CE(3). Each chip enabler CE(0), CE(1), CE(2), and CE(3) contains multiple physical nodes. The memory control circuit 23 can enable the chip enablers separately through chip enable pins. In addition, each chip enabler CE(0), CE(1), CE(2), and CE(3) can contain multiple planes (e.g., Figure 4 The planes PL(1) and PL(2), PL(3) and PL(4), PL(5) and PL(6), PL(7) and PL(8)). Those skilled in the art will clearly understand that the memory module 122 may have any other chip enable, which will not be elaborated here.

[0039] The memory control circuit 23 can group consecutive physical blocks belonging to different memory planes into a physical group for operations (e.g., data erasure and garbage collection). A physical group includes at least two usable physical blocks from all physical blocks. In this embodiment, the at least two usable physical blocks included in a physical group belong to different operating units (e.g., plane, interleave, or channel). Therefore, the physical blocks included in a physical group can be programmed simultaneously according to the same write instruction. In one embodiment, during a data erasure operation, data erasure is performed simultaneously on the physical blocks included in a physical group, on a physical group basis. During a garbage collection operation, data in the physical blocks included in a physical group is simultaneously copied to physical blocks in other physical groups, on a physical group basis.

[0040] In this embodiment, as Figure 4As shown, entity block Block 0 consists of entity pages 401(0)~401(3), entity block Block 1 consists of entity pages 402(0)~402(3), entity block Block 2 consists of entity pages 403(0)~403(3), entity block Block 3 consists of entity pages 404(0)~404(3), entity block Block 4 consists of entity pages 405(0)~405(3), entity block Block 5 consists of entity pages 406(0)~406(3), entity block Block 6 consists of entity pages 407(0)~407(3), and entity block Block... 7 consists of entity pages 408(0) to 408(3), and entity blocks Block0, Block1, Block2...Block7 belonging to different planes (PL(1), PL(2), PL(3), PL(4), PL(5), PL(6), PL(7), PL(8)) can be configured as entity group 410(0). Each entity block in entity group 410(0) comes from a different plane, and multi-plane operations can be performed in parallel for reading and writing. In another embodiment, entity blocks Block0, Block1, Block2...Block15 can be configured as entity group Unit 0. The present invention is not limited thereto.

[0041] Figure 5 This is a schematic diagram of a VC table according to an embodiment of the present invention. In this embodiment, the VC (validcount) table uses the VC field to record the total number of valid data in each entity group (e.g., Unit 0, Unit 1, Unit 2...Unit N) and the number of valid data in each entity block in the entity group (e.g., each entity group includes entity blocks Block 0, Block 1, Block 2...Block 15).

[0042] Please refer to Figure 5 Data in an entity page that has been filled with dots is considered valid data. Figure 5 The data stored in the white-illustrated entity pages is invalid data. Therefore, the total number of valid data for entity groups Unit0, Unit1, Unit2, Unit3, and Unit N are VC=22, VC=26, VC=27, VC=30, and VC=18, respectively. Among them, the VC values ​​(number of valid data) of entity blocks Block 0, Block 1, Block 2, and Block 15 in entity group Unit N are VC=4, VC=5, VC=3, and VC=6, respectively.

[0043] In one embodiment, when performing a waste collection operation, based on Figure 5 The VC field in the VC table shows the total number of valid data for each entity group. This is used to identify the entity group Unit N (the target entity group) with the smallest or smallest total number of valid data (VC = 18 is the smallest). Simultaneously, it determines whether the percentage of valid data in each entity block within entity group Unit N is greater than a threshold. In this embodiment, the user can set the threshold to 0.5 based on needs or experience. The VC value for entity block Block 0 is 4, and its percentage of valid data is calculated as 4 / 10 = 0.4. Similarly, the percentage of valid data for entity block Block 1 is calculated to be 0.5, for entity block Block 2 to be 0.3, and for entity block Block 15 to be 0.6. That is, only entity block Block 15 (the first entity block) has a percentage of valid data greater than the threshold, and the memory control circuit 23 determines that a replacement operation needs to be performed on entity block Block 15. When the percentage of valid data in an entity block is not greater than the threshold, the valid data in the entity blocks of entity group Unit N is moved to entity blocks in other entity groups.

[0044] In one embodiment, the memory control circuit 23 can select an empty physical block in another empty physical group to replace physical block Block 15 in physical group Unit N, and move valid data from other physical blocks in physical group Unit N (e.g., physical blocks Block 0, Block 1, Block 2) to physical blocks in other physical groups (e.g., physical group Unit 0, etc.). The selected empty physical block has a programmable / erase count close to or the same as that of physical block Block 15, and the empty physical block and physical block Block 15 belong to the same memory plane. This maintains that the physical blocks in physical group Unit N after the replacement of the physical block originate from different memory planes, as multi-plane parallel read / write operations are faster, thus improving the read / write efficiency of the rewritable non-volatile memory module.

[0045] In one embodiment, the validity of data can be determined based on the Physical Cell Address (PCA) recorded in the Page Table Entry (PTE). A PCA with a record indicates valid data, while an invalid PCA (0xFFFFFFFF) indicates invalid data. In other words, if a PTE entry contains a PCA with a record, then the data stored corresponding to that PCA is valid. Conversely, if the corresponding data is unavailable or has been erased, it is invalid.

[0046] In garbage collection, page-level and block-level markers are typically used to mark valid data. In one embodiment, each entity page has a valid bit to indicate whether the data within that entity page is valid. When data is written to an entity page, its valid bit is set to valid. When data is deleted or updated, the corresponding valid bit is set to invalid. During garbage collection, only entity pages with valid valid bits are retained; other invalid entity pages are erased. In another embodiment, each entity block has a block marker to indicate whether the data within the entire entity block is valid. When all entity pages in an entity block are marked as invalid, the block's block marker is set to invalid. During garbage collection, only entity blocks with valid block markers are retained; other invalid entity blocks are erased. The page-level and block-level marking methods described above can be used in combination to improve the efficiency and accuracy of garbage collection operations.

[0047] Furthermore, this application proposes a multi-level paging mechanism to establish the aforementioned PTE table. Specifically, multi-level paging is a page table structure that divides the virtual address space into multiple levels.

[0048] In multilevel paging, the virtual address space is divided into multiple levels, each with a corresponding page table. Each page table contains a set of Page Entries (PTEs), and each PTE entry corresponds to a physical address. By using multilevel paging, a large virtual address space can be divided into multiple smaller page tables, thereby reducing the size of the page tables.

[0049] In rewritable non-volatile memory modules, the PTE table is also built using a multi-level paging mechanism. First, the virtual address space of the entire rewritable non-volatile memory module is divided into multiple page tables, each corresponding to a logical address range. Then, the PTE entries in each page table record the physical addresses within the corresponding logical address range.

[0050] For example, suppose the virtual address space of a rewritable non-volatile memory module is divided into four page tables, each corresponding to a logical address range of 1GB. Then, the logical address range for the first page table is 0GB-1GB, the logical address range for the second page table is 1GB-2GB, and so on. The PTE entry in each page table records the physical address within the corresponding logical address range.

[0051] Through a multi-level paging mechanism, rewritable non-volatile memory modules can efficiently manage a large number of physical addresses and can be dynamically adjusted and expanded as needed.

[0052] The following combination Figure 6 This application illustrates a three-level page table paging mechanism that can quickly locate entity pages based on a three-level index and obtain information on whether the data stored on the corresponding entity page is valid or invalid.

[0053] Figure 6 This is a schematic diagram of a three-level page table paging system according to an embodiment of the present invention. Please refer to... Figure 6 The virtual address space of a rewritable non-volatile memory module can be divided into three page tables, and a three-level index can be used to quickly find physical pages.

[0054] Specifically, the three-level page table paging mechanism comprises three levels of indexes: the Page Global Directory index (PGD index), the Page Middle Directory index (PMDindex), and the Page Table Entry (PTE). Each index is an array, where each entry corresponds to a page. The virtual address is divided into three parts: the page directory index, the page middle directory index, and the page table.

[0055] When a physical page needs to be located, the process first retrieves the Page Intermediate Table (PMD) PCA (i.e., the physical address of the PMD) from the page directory index to find the corresponding PMD. Then, the Page Table (PTE) PCA (i.e., the physical address of the PTE) is retrieved based on the page intermediate index to find the corresponding page table. Finally, the corresponding physical page is found from the physical page number stored in the page table, thus obtaining information about whether the stored data is valid or invalid.

[0056] The three-level page table paging mechanism provided in this application only requires reading the necessary page table each time. It uses multi-level indexes to flexibly allocate and manage page tables, which can not only speed up the search for physical pages, but also reduce the time spent accessing memory.

[0057] This application further proposes to use a RUT (replace unit table) to record the management of target entity groups and entity blocks to be replaced.

[0058] Figure 7 This is a schematic diagram of a RUT table according to an embodiment of the present invention. Please refer to... Figure 7In this embodiment, in response to the fact that the proportion of valid data in the entity blocks is greater than the threshold, it is determined that the entity blocks (source blocks) S4, S5 and S3 in entity groups Unit4, Unit5 and Unit3 need to be replaced with the entity blocks (target blocks) T6, T0 and T1 in entity groups Unit6, Unit1 and Unit0.

[0059] When a replacement is needed, the memory planes to which the entity blocks S4, S5, and S3 belong, as well as the offsets of the memory planes in the second replacement group table (RUT L2), are first obtained based on the first replacement group table (RUT L1). Then, the up-down mapping relationship of the K-line recorded in RUT L2 is read based on the offsets. Based on the mapping relationship, the entity blocks S4, S5, and S3 are updated to be mapped to entity blocks T6, T0, and T1, so as to replace the entity blocks belonging to the same memory plane with the empty entity blocks.

[0060] In this embodiment, the memory plane to which the entity block S4 to be replaced belongs is PB0 and the offset is 0, obtained through RUT L1. Based on this offset, the mapping relationship (i.e., PB0, T6, S4) in RUT L2 is read. Based on this mapping relationship, the mapping to entity block S4 can be updated to the mapping to entity block T6, and entity block S4 and entity block T6 belong to the same memory plane PB0.

[0061] Similarly, the memory plane to which the entity block S5 to be replaced belongs, PB7, and the offset is 3, can be obtained through RUT L1. Based on this offset, the mapping relationship (i.e., PB7, T0, S5) in RUT L2 can be read. Based on this mapping relationship, the entity block S5 can be updated to the entity block T0, and the entity block S5 and the entity block T0 belong to the same memory plane PB7. The memory planes to which the entity block S3 to be replaced belongs, PB5 and PB2, and the offsets, 2 and 1, can be obtained through RUT L1. Based on these offsets, the mapping relationship in RUT L2 (i.e., PB5, T6, S3 and PB2, T1, S3) can be read. Based on this mapping relationship, the entity block S3 can be updated to be mapped to entity block T6, and entity block S3 and entity block T6 belong to the same memory plane PB5. The entity block S3 can be updated to be mapped to entity block T1, and entity block S3 and entity block T1 belong to the same memory plane PB2.

[0062] After replacing the source blocks S4, S5, and S3 in entity groups Unit4, Unit5, and Unit3 with the target blocks T6, T0, and T1 in entity groups Unit6, Unit1, and Unit0, please refer to... Figure 7 The diagram on the right shows that valid data in entity groups Unit2, Unit4, Unit5, and Unit3 has been moved or their entity blocks have been replaced with empty entity blocks.

[0063] In one embodiment, RUT L2 can record the upper and lower mapping relationships of the K-line according to the offset from small to large to facilitate searching. The maximum number of Units can be obtained by sorting by K-line representation.

[0064] Figure 8 This is a flowchart illustrating a block management method according to an embodiment of the present invention.

[0065] Please refer to Figure 8 The method of this embodiment is applicable to the memory storage device 12 in the above embodiments. The detailed steps of this embodiment will be described below with reference to the various components in the memory storage device 12. It is worth noting that... Figure 8 Each step can be implemented as multiple codes or circuits; this invention is not limited thereto. Furthermore, Figure 8 The method can be used in conjunction with the following example embodiments, or it can be used alone; the present invention does not limit it.

[0066] In step S801, the memory controller 123 obtains the number of valid data in each entity block in each entity group, and obtains the total number of valid data in each entity group based on the number of valid data in each entity block.

[0067] In step S802, during the garbage collection operation, the memory controller 123 selects the target entity group with the smaller total number of valid data from multiple entity groups.

[0068] In step S803, the memory controller 123 determines whether to perform a replacement operation on the first entity block based on whether the effective data ratio of the first entity block in the target entity group is greater than a threshold.

[0069] In step S804, in response to the fact that the proportion of valid data in the first entity block is greater than a threshold, the memory controller 123 replaces the first entity block with an empty entity block of another entity group, and moves the valid data of other entity blocks in the target entity group to entity blocks in other entity groups. In one embodiment, the first entity block and the empty entity block belong to the same memory plane, and the number of times the empty entity block is programmed / erased is close to the number of times the first entity block is programmed / erased.

[0070] In step S805, the memory controller 123 erases the target entity group.

[0071] In step S806, in response to the fact that the proportion of valid data in the first entity block is not greater than the threshold, the memory controller 123 moves the valid data in the entity block of the target entity group to the entity block of other entity groups, and jumps to step S805 to erase the target entity group.

[0072] Figure 9 This is a flowchart illustrating the use of a RUT table to perform a replacement operation on a first entity block according to an embodiment of the present invention.

[0073] Please refer to Figure 9 In step S8041, in response to the fact that the effective data ratio of the first entity block is greater than the threshold, the memory controller 123 determines that the first entity block needs to be replaced.

[0074] In step S8042, the memory controller 123 obtains the memory plane to which the first entity block belongs and the offset of the memory plane in the second replacement group table (RUT L2) based on the first replacement group table (RUT L1).

[0075] In step S8043, the memory controller 123 reads the mapping relationship in the second replacement group table according to the offset, and updates the mapping to the first entity block to the mapping to the empty entity block according to the mapping relationship, so as to replace the first entity block and the empty entity block belonging to the same memory plane.

[0076] Based on the above, the present invention provides a block management method, a memory storage device, and a memory controller. During the garbage collection process, a first entity block containing valid data in a target entity group is replaced with an empty entity block without valid data in another entity group. Valid data stored in other entity blocks in the target entity group is then moved to entity blocks in other entity groups, and the target entity group is erased. This reduces write amplification during the garbage collection process, thereby extending the lifespan of the memory storage device.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A block management method, characterized in that, For controlling a memory module, wherein the memory module includes multiple entity groups, each entity group includes multiple entity blocks belonging to different memory planes, each entity block includes multiple entity pages, and the block management method includes: Obtain the number of valid data items in each entity block within each entity group, and obtain the total number of valid data items in each entity group based on the number of valid data items in each entity block. When performing garbage collection operations, the target entity group is obtained based on the total number of valid data. Whether to perform a replacement operation on the first entity block is determined based on whether the proportion of valid data in the first entity block in the target entity group is greater than a threshold. In response to the first entity block having a valid data percentage greater than the threshold, the first entity block is replaced with an empty entity block from another entity group among the plurality of entity groups; including... The memory plane to which the first entity block belongs and the offset of the memory plane in the second replacement group table are obtained based on the first replacement group table. The mapping relationship in the second replacement group table is read according to the offset, and the mapping to the first entity block is updated to the mapping to the empty entity block according to the mapping relationship, so as to replace the first entity block and the empty entity block belonging to the same memory plane.

2. The block management method according to claim 1, characterized in that, The empty physical block and the first physical block belong to the same memory plane, and the number of times the empty physical block is programmed / erased is close to the number of times the first physical block is programmed / erased.

3. The block management method according to claim 1, characterized in that, The block management method also includes: The logical address space of the memory module is divided into multiple page tables corresponding to multiple logical address ranges, and each page table includes an entry for recording the entity address corresponding to each logical address range.

4. The block management method according to claim 3, characterized in that, The block management method also includes: The entity page corresponding to the entity address is read based on the entity address recorded in the table entry, and it is determined whether the data stored in the entity page is valid data.

5. The block management method according to claim 1, characterized in that, The mapping relationship of the second replacement group table record includes the memory plane, the empty entity block belonging to the same memory plane, and the first entity block.

6. A memory storage device, characterized in that, include: Connection interface, used to connect to the host system; A memory module includes multiple entity groups, each entity group including multiple entity blocks belonging to different memory planes, and each entity block including multiple entity pages; as well as The memory controller connects the connection interface to the memory module. The memory controller is used to obtain the number of valid data in each entity block in each entity group, and to obtain the total number of valid data in each entity group based on the number of valid data in each entity block. During garbage collection, the memory controller is used to obtain the target entity group based on the total number of valid data. The memory controller is used to determine whether to perform a replacement operation on the first entity block based on whether the effective data ratio of the first entity block in the target entity group is greater than a threshold. In response to the first entity block having a valid data percentage greater than the threshold, the memory controller replaces the first entity block with an empty entity block from another entity group among the plurality of entity groups; including... The memory controller is further configured to obtain the memory plane to which the first entity block belongs and the offset of the memory plane in the second replacement group table based on the first replacement group table; The memory controller is further configured to read the mapping relationship in the second replacement group table according to the offset, and update the mapping to the first entity block to the empty entity block according to the mapping relationship, so as to replace the first entity block and the empty entity block belonging to the same memory plane.

7. The memory storage device according to claim 6, characterized in that, The empty physical block and the first physical block belong to the same memory plane, and the number of times the empty physical block is programmed / erased is close to the number of times the first physical block is programmed / erased.

8. The memory storage device according to claim 6, characterized in that, The memory controller is further configured to divide the logical address space of the memory module into multiple page tables corresponding to multiple logical address ranges, each page table including an entry for recording the entity address corresponding to each logical address range.

9. The memory storage device according to claim 8, characterized in that, The memory controller is further configured to read the entity page corresponding to the entity address based on the entity address recorded in the table entry, and determine whether the data stored in the entity page is valid data.

10. The memory storage device according to claim 6, characterized in that, The mapping relationship of the second replacement group table record includes the memory plane, the empty entity block belonging to the same memory plane, and the first entity block.

11. A memory controller, characterized in that, include: Host interface, used to connect to the host system; A memory interface for connecting a memory module, wherein the memory module includes multiple entity groups, each entity group includes multiple entity blocks belonging to different memory planes, and each entity block includes multiple entity pages; Error checking and correction circuitry; as well as The memory control circuit is connected to the host interface, the memory interface, and the error checking and correction circuit. The memory control circuit is used to obtain the number of valid data in each entity block in each entity group, and to obtain the total number of valid data in each entity group based on the number of valid data in each entity block. During the garbage collection operation, the memory control circuit is used to obtain the target entity group based on the total number of valid data; The memory control circuit is used to determine whether to perform a replacement operation on the first entity block based on whether the effective data ratio of the first entity block in the target entity group is greater than a threshold. In response to the fact that the effective data ratio of the first entity block is greater than the threshold, the memory control circuit is used to replace the first entity block with an empty entity block of another entity group in the plurality of entity groups; This includes The memory control circuit is further configured to obtain the memory plane to which the first entity block belongs and the offset of the memory plane in the second replacement group table based on the first replacement group table; The memory control circuit is further configured to read the mapping relationship in the second replacement group table according to the offset, and update the mapping to the first entity block to the empty entity block according to the mapping relationship, so as to replace the first entity block and the empty entity block belonging to the same memory plane.

12. The memory controller according to claim 11, characterized in that, The empty physical block and the first physical block belong to the same memory plane, and the number of times the empty physical block is programmed / erased is close to the number of times the first physical block is programmed / erased.

13. The memory controller according to claim 11, characterized in that, The memory control circuit is further configured to divide the logical address space of the memory module into multiple page tables corresponding to multiple logical address ranges, each page table including an entry for recording the physical address corresponding to each logical address range.

14. The memory controller according to claim 13, characterized in that, The memory control circuit is further configured to read the entity page corresponding to the entity address based on the entity address recorded in the table entry, and to determine whether the data stored in the entity page is valid data.

15. The memory controller according to claim 11, characterized in that, The mapping relationship of the second replacement group table record includes the memory plane, the empty entity block belonging to the same memory plane, and the first entity block.

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