Methods, devices, electronic equipment, and storage media for locating motherboard memory faults

Abstract

This invention provides a method, apparatus, electronic device, and storage medium for locating motherboard memory faults. The method includes: in response to receiving a memory module test command input by a user, acquiring first pin voltage data of the memory module under test; performing array format numbering processing on the first pin voltage data according to the bidirectional binary synchronous serial bus information of the voltage acquisition module; in response to the completion of array format numbering processing, generating multiple first impedance comparison values ​​based on the first pin voltage data; determining whether a first target pin exists among multiple pairs of first test pins based on the multiple first impedance comparison values ​​and a difference threshold; if so, determining the first faulty pin based on the first reference impedance data, the first target impedance data, and the difference threshold; if not, in response to receiving a memory slot test command input by a user, performing a memory slot comparison test and a memory slot synchronization test according to the memory slot test command. The faulty pin is quickly located through the comparison test and the synchronization test.

Description

Technical Field

[0001] This invention relates to the field of memory testing technology, and in particular to a method, apparatus, electronic device, and storage medium for locating motherboard memory faults. Background Technology

[0002] DDR (Double Data Rate) memory, as a crucial component of computers (servers), is the cornerstone of big data, cloud computing, and cloud storage. Currently, DDR4 and DDR5 are commonly used in general-purpose servers and storage servers. During server development, issues frequently arise such as individual server motherboards failing to recognize or losing DDR memory; DDR memory being lost during power-on / power-off testing; servers failing to boot after inserting a particular memory module; and DDR speed failing to meet testing standards. The mainstream solution to these problems is currently to perform SI testing on the DDR memory. This involves professional SI engineers using an oscilloscope to perform SI tests on the DDR channel signals and observe the SI signal quality to determine the cause of the DDR failure. This method can accurately and effectively diagnose memory problems; however, a single server board has anywhere from 8 to 64 memory slots, and each memory slot has nearly 300 signal pins. Testing a single memory slot can take nearly 4 hours, resulting in a huge workload. Solution 2 involves using relevant testing fixtures and software provided by the processor vendor, such as Intel's XDP (Intel In-Target Probe–XDP3) fixture and CScripts software, to locate memory negotiation issues and collect memory error logs. However, this tool can only be used when the memory is identifiable but the connection fails. Furthermore, not all processor manufacturers provide memory debugging tools, such as Hygon, Zhaoxin, and Phytium. Summary of the Invention

[0003] Therefore, it is necessary to provide a method, device, electronic device, and storage medium for locating motherboard memory faults that can quickly pinpoint the fault location on the server motherboard, in response to the aforementioned technical problems.

[0004] In a first aspect, a method for locating motherboard memory faults is provided, characterized in that the method includes:

[0005] In response to receiving a memory module test command input by the user through the communication serial port, the voltage acquisition module is controlled to acquire the first pin voltage data of the memory module under test, wherein the memory module test command includes a difference threshold.

[0006] The voltage data of the first pin is numbered in array format according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module.

[0007] In response to the completion of array format numbering processing, multiple first impedance comparison values ​​for multiple pairs of first test pins are generated based on the first pin voltage data;

[0008] Based on the plurality of first impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of first target pins among the plurality of pairs of first test pins;

[0009] If so, the first faulty pin in the first target pin is determined based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold.

[0010] If not, in response to receiving the memory slot test command input by the user, the memory slot comparison test and memory slot synchronization test of the memory slot under test are performed according to the memory slot test command.

[0011] In one embodiment, generating multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data includes:

[0012] Based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module x The first test impedance R of each first test pin is calculated using the following formula. x ;

[0013] R x =(R1*R2*V x ) / (V*R2―V x *R2―R1*V x )

[0014] The multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number.

[0015] In one embodiment, determining the first faulty pin among the first target pins based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold includes:

[0016] Determine whether the first reference impedance data corresponding to the memory module under test exists in the electrically erasable programmable read-only memory;

[0017] If not, in response to receiving the first reference impedance data measurement instruction input by the user, the first reference impedance data is measured on memory modules of the same type and the first reference impedance data is generated;

[0018] If so, a first impedance synchronization value is generated based on the first reference impedance data and the first target impedance data, and the first faulty pin is determined based on the first impedance synchronization value and the difference threshold.

[0019] In one embodiment, the step of measuring the first reference impedance data on memory modules of the same type and generating the first reference impedance data includes:

[0020] In response to receiving the first sampling count corresponding to the first reference impedance data input by the user, the first reference voltage value corresponding to the memory module of the same type is obtained through the voltage acquisition module;

[0021] In response to the completion of acquiring the first reference voltage value, the first reference voltage value is acquired again according to the first acquisition count, and the first reference impedance data is generated according to the first reference voltage value corresponding to the first acquisition count.

[0022] In one embodiment, the step of performing memory slot comparison testing and memory slot synchronization testing on the memory slot under test according to the memory slot test instructions includes:

[0023] The voltage acquisition module is controlled to acquire the voltage data of the second pin corresponding to the memory slot under test.

[0024] The second pin voltage data is numbered in array format according to the bidirectional binary synchronous serial bus information.

[0025] In response to the completion of the array format numbering processing, multiple second impedance comparison values ​​for multiple pairs of second test pins are generated based on the second pin voltage data;

[0026] Based on the plurality of second impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of second target pins among the plurality of pairs of second test pins;

[0027] If so, the second faulty pin in the second target pin is determined based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

[0028] In one embodiment, generating multiple second impedance comparison values ​​for multiple pairs of second test pins based on the second pin voltage data includes:

[0029] Based on the first resistor R1, the second resistor R2, the total voltage V, and the second pin voltage data V in the voltage acquisition module y The second test impedance R for each second test pin is calculated using the following formula. y ;

[0030] R y =(R1*R2*V y ) / (V*R2―V y *R2―R1*V y )

[0031] The multiple second impedance comparison values ​​are calculated based on the second test impedance corresponding to the second test pin with the same number.

[0032] In one embodiment, determining the second faulty pin in the second target pin based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold includes:

[0033] Determine whether the second reference impedance data corresponding to the memory slot under test exists in the electrically erasable programmable read-only memory;

[0034] If not, in response to receiving the second sampling number corresponding to the second reference impedance data input by the user, the second reference voltage value corresponding to the memory slot of the same type is obtained through the voltage acquisition module;

[0035] In response to the completion of acquiring the reference voltage value, the second reference voltage value is acquired again according to the second acquisition number, and the second reference impedance data is generated according to the second reference voltage value corresponding to the second acquisition number.

[0036] If so, a second impedance synchronization value is generated based on the second reference impedance data and the second target impedance data, and the second faulty pin is determined based on the second impedance synchronization value and the difference threshold.

[0037] On the other hand, a device for locating motherboard memory faults is provided, characterized in that the device comprises:

[0038] The acquisition module is used to control the voltage acquisition module to acquire the first pin voltage data of the memory module under test in response to receiving a memory module test command input by the user through the communication serial port, wherein the memory module test command includes a difference threshold.

[0039] The processing module is used to perform array format numbering processing on the first pin voltage data according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module;

[0040] The generation module is used to generate multiple pairs of first impedance comparison values ​​for the first test pins based on the first pin voltage data in response to the completion of array format numbering processing.

[0041] The first determining module is used to determine whether there is one or more pairs of first target pins among the multiple pairs of first test pins based on the first impedance comparison value and the difference threshold.

[0042] If the second determining module is used, it is used to determine the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold.

[0043] The memory slot testing module, if not, is used to respond to the memory slot testing command input by the user and perform memory slot comparison test and memory slot synchronization test on the memory slot under test according to the memory slot testing command.

[0044] In one embodiment, the generation module generates multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data, including:

[0045] Based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module x The first test impedance R of each first test pin is calculated using the following formula. x ;

[0046] R x =(R1*R2*V x ) / (V*R2―V x *R2―R1*V x )

[0047] The multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number.

[0048] In one embodiment, the second determining module determines the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold, including:

[0049] Determine whether the first reference impedance data corresponding to the memory module under test exists in the electrically erasable programmable read-only memory;

[0050] If not, in response to receiving the first reference impedance data measurement instruction input by the user, the first reference impedance data is measured on memory modules of the same type and the first reference impedance data is generated;

[0051] If so, a first impedance synchronization value is generated based on the first reference impedance data and the first target impedance data, and the first faulty pin is determined based on the first impedance synchronization value and the difference threshold.

[0052] In one embodiment, the second determining module performs a first reference impedance data measurement on memory modules of the same type and generates the first reference impedance data by:

[0053] In response to receiving the first sampling count corresponding to the first reference impedance data input by the user, the first reference voltage value corresponding to the memory module of the same type is obtained through the voltage acquisition module;

[0054] In response to the completion of acquiring the first reference voltage value, the first reference voltage value is acquired again according to the first acquisition count, and the first reference impedance data is generated according to the first reference voltage value corresponding to the first acquisition count.

[0055] In one embodiment, the memory slot testing module performs memory slot comparison testing and memory slot synchronization testing on the memory slot under test according to the memory slot testing instructions, including:

[0056] The voltage acquisition module is controlled to acquire the voltage data of the second pin corresponding to the memory slot under test.

[0057] The second pin voltage data is numbered in array format according to the bidirectional binary synchronous serial bus information.

[0058] In response to the completion of the array format numbering processing, multiple second impedance comparison values ​​for multiple pairs of second test pins are generated based on the second pin voltage data;

[0059] Based on the plurality of second impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of second target pins among the plurality of pairs of second test pins;

[0060] If so, the second faulty pin in the second target pin is determined based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

[0061] In one embodiment, the memory slot testing module generates multiple second impedance comparison values ​​for multiple pairs of second test pins based on the second pin voltage data, including:

[0062] Based on the first resistor R1, the second resistor R2, the total voltage V, and the second pin voltage data V in the voltage acquisition module y The second test impedance R for each second test pin is calculated using the following formula. y ;

[0063] R y =(R1*R2*V y ) / (V*R2―V y *R2―R1*V y )

[0064] The multiple second impedance comparison values ​​are calculated based on the second test impedance corresponding to the second test pin with the same number.

[0065] In one embodiment, the memory slot testing module determines the second faulty pin in the second target pin based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold, including:

[0066] Determine whether the second reference impedance data corresponding to the memory slot under test exists in the electrically erasable programmable read-only memory;

[0067] If not, in response to receiving the second sampling number corresponding to the second reference impedance data input by the user, the second reference voltage value corresponding to the memory slot of the same type is obtained through the voltage acquisition module;

[0068] In response to the completion of acquiring the reference voltage value, the second reference voltage value is acquired again according to the second acquisition number, and the second reference impedance data is generated according to the second reference voltage value corresponding to the second acquisition number.

[0069] If so, a second impedance synchronization value is generated based on the second reference impedance data and the second target impedance data, and the second faulty pin is determined based on the second impedance synchronization value and the difference threshold.

[0070] In another aspect, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0071] In response to receiving a memory module test command input by the user through the communication serial port, the voltage acquisition module is controlled to acquire the first pin voltage data of the memory module under test, wherein the memory module test command includes a difference threshold.

[0072] The voltage data of the first pin is numbered in array format according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module.

[0073] In response to the completion of array format numbering processing, multiple first impedance comparison values ​​for multiple pairs of first test pins are generated based on the first pin voltage data;

[0074] Based on the plurality of first impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of first target pins among the plurality of pairs of first test pins;

[0075] If so, the first faulty pin in the first target pin is determined based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold.

[0076] If not, in response to receiving the memory slot test command input by the user, the memory slot comparison test and memory slot synchronization test of the memory slot under test are performed according to the memory slot test command.

[0077] In one embodiment, the processor performs the following steps when executing the computer program:

[0078] The process of generating multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data includes:

[0079] Based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module x The first test impedance R of each first test pin is calculated using the following formula. x ;

[0080] R x =(R1*R2*V x ) / (V*R2―V x *R2―R1*V x )

[0081] The multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number.

[0082] In one embodiment, the processor performs the following steps when executing the computer program:

[0083] The step of determining the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold includes:

[0084] Determine whether the first reference impedance data corresponding to the memory module under test exists in the electrically erasable programmable read-only memory;

[0085] If not, in response to receiving the first reference impedance data measurement instruction input by the user, the first reference impedance data is measured on memory modules of the same type and the first reference impedance data is generated;

[0086] If so, a first impedance synchronization value is generated based on the first reference impedance data and the first target impedance data, and the first faulty pin is determined based on the first impedance synchronization value and the difference threshold.

[0087] In one embodiment, the processor performs the following steps when executing the computer program:

[0088] The step of measuring the first reference impedance data of memory modules of the same type and generating the first reference impedance data includes:

[0089] In response to receiving the first sampling count corresponding to the first reference impedance data input by the user, the first reference voltage value corresponding to the memory module of the same type is obtained through the voltage acquisition module;

[0090] In response to the completion of acquiring the first reference voltage value, the first reference voltage value is acquired again according to the first acquisition count, and the first reference impedance data is generated according to the first reference voltage value corresponding to the first acquisition count.

[0091] In one embodiment, the processor performs the following steps when executing the computer program:

[0092] The process of performing memory slot comparison testing and memory slot synchronization testing according to the memory slot test instructions includes:

[0093] The voltage acquisition module is controlled to acquire the voltage data of the second pin corresponding to the memory slot under test.

[0094] The second pin voltage data is numbered in array format according to the bidirectional binary synchronous serial bus information.

[0095] In response to the completion of the array format numbering processing, multiple second impedance comparison values ​​for multiple pairs of second test pins are generated based on the second pin voltage data;

[0096] Based on the plurality of second impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of second target pins among the plurality of pairs of second test pins;

[0097] If so, the second faulty pin in the second target pin is determined based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

[0098] In one embodiment, the processor performs the following steps when executing the computer program:

[0099] The process of generating multiple second impedance comparison values ​​for multiple pairs of second test pins based on the second pin voltage data includes:

[0100] Based on the first resistor R1, the second resistor R2, the total voltage V, and the second pin voltage data V in the voltage acquisition module y The second test impedance R for each second test pin is calculated using the following formula. y ;

[0101] R y =(R1*R2*V y ) / (V*R2―V y *R2―R1*V y )

[0102] The multiple second impedance comparison values ​​are calculated based on the second test impedance corresponding to the second test pin with the same number.

[0103] In one embodiment, the processor performs the following steps when executing the computer program:

[0104] The step of determining the second faulty pin in the second target pin based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold includes:

[0105] Determine whether the second reference impedance data corresponding to the memory slot under test exists in the electrically erasable programmable read-only memory;

[0106] If not, in response to receiving the second sampling number corresponding to the second reference impedance data input by the user, the second reference voltage value corresponding to the memory slot of the same type is obtained through the voltage acquisition module;

[0107] In response to the completion of acquiring the reference voltage value, the second reference voltage value is acquired again according to the second acquisition number, and the second reference impedance data is generated according to the second reference voltage value corresponding to the second acquisition number.

[0108] If so, a second impedance synchronization value is generated based on the second reference impedance data and the second target impedance data, and the second faulty pin is determined based on the second impedance synchronization value and the difference threshold.

[0109] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0110] In response to receiving a memory module test command input by the user through the communication serial port, the voltage acquisition module is controlled to acquire the first pin voltage data of the memory module under test, wherein the memory module test command includes a difference threshold.

[0111] The voltage data of the first pin is numbered in array format according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module.

[0112] In response to the completion of array format numbering processing, multiple first impedance comparison values ​​for multiple pairs of first test pins are generated based on the first pin voltage data;

[0113] Based on the plurality of first impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of first target pins among the plurality of pairs of first test pins;

[0114] If so, the first faulty pin in the first target pin is determined based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold.

[0115] If not, in response to receiving the memory slot test command input by the user, the memory slot comparison test and memory slot synchronization test of the memory slot under test are performed according to the memory slot test command.

[0116] In one embodiment, the computer program performs the following steps when executed by a processor:

[0117] The process of generating multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data includes:

[0118] Based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module x The first test impedance R of each first test pin is calculated using the following formula. x ;

[0119] R x =(R1*R2*V x ) / (V*R2―V x *R2―R1*V x )

[0120] The multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number.

[0121] In one embodiment, the computer program performs the following steps when executed by a processor:

[0122] The step of determining the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold includes:

[0123] Determine whether the first reference impedance data corresponding to the memory module under test exists in the electrically erasable programmable read-only memory;

[0124] If not, in response to receiving the first reference impedance data measurement instruction input by the user, the first reference impedance data is measured on memory modules of the same type and the first reference impedance data is generated;

[0125] If so, a first impedance synchronization value is generated based on the first reference impedance data and the first target impedance data, and the first faulty pin is determined based on the first impedance synchronization value and the difference threshold.

[0126] In one embodiment, the computer program performs the following steps when executed by a processor:

[0127] The step of measuring the first reference impedance data of memory modules of the same type and generating the first reference impedance data includes:

[0128] In response to receiving the first sampling count corresponding to the first reference impedance data input by the user, the first reference voltage value corresponding to the memory module of the same type is obtained through the voltage acquisition module;

[0129] In response to the completion of acquiring the first reference voltage value, the first reference voltage value is acquired again according to the first acquisition count, and the first reference impedance data is generated according to the first reference voltage value corresponding to the first acquisition count.

[0130] In one embodiment, the computer program performs the following steps when executed by a processor:

[0131] The process of performing memory slot comparison testing and memory slot synchronization testing according to the memory slot test instructions includes:

[0132] The voltage acquisition module is controlled to acquire the voltage data of the second pin corresponding to the memory slot under test.

[0133] The second pin voltage data is numbered in array format according to the bidirectional binary synchronous serial bus information.

[0134] In response to the completion of the array format numbering processing, multiple second impedance comparison values ​​for multiple pairs of second test pins are generated based on the second pin voltage data;

[0135] Based on the plurality of second impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of second target pins among the plurality of pairs of second test pins;

[0136] If so, the second faulty pin in the second target pin is determined based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

[0137] In one embodiment, the computer program performs the following steps when executed by a processor:

[0138] The process of generating multiple second impedance comparison values ​​for multiple pairs of second test pins based on the second pin voltage data includes:

[0139] Based on the first resistor R1, the second resistor R2, the total voltage V, and the second pin voltage data V in the voltage acquisition module y The second test impedance R for each second test pin is calculated using the following formula. y ;

[0140] R y =(R1*R2*V y ) / (V*R2―V y *R2―R1*V y )

[0141] The multiple second impedance comparison values ​​are calculated based on the second test impedance corresponding to the second test pin with the same number.

[0142] In one embodiment, the computer program performs the following steps when executed by a processor:

[0143] The step of determining the second faulty pin in the second target pin based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold includes:

[0144] Determine whether the second reference impedance data corresponding to the memory slot under test exists in the electrically erasable programmable read-only memory;

[0145] If not, in response to receiving the second sampling number corresponding to the second reference impedance data input by the user, the second reference voltage value corresponding to the memory slot of the same type is obtained through the voltage acquisition module;

[0146] In response to the completion of acquiring the reference voltage value, the second reference voltage value is acquired again according to the second acquisition number, and the second reference impedance data is generated according to the second reference voltage value corresponding to the second acquisition number.

[0147] If so, a second impedance synchronization value is generated based on the second reference impedance data and the second target impedance data, and the second faulty pin is determined based on the second impedance synchronization value and the difference threshold.

[0148] The aforementioned method for locating motherboard memory faults involves, in response to receiving a memory module test command input by a user via a communication serial port, controlling a voltage acquisition module to acquire the first pin voltage data of the memory module under test, wherein the memory module test command includes a difference threshold; processing the first pin voltage data into an array format number based on the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module; in response to the completion of the array format numbering processing, generating multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data; determining whether there is one or more pairs of first target pins among the multiple pairs of first test pins based on the multiple first impedance comparison values ​​and the difference threshold; if so, determining the first faulty pin among the first target pins based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold; if not, in response to receiving a memory slot test command input by the user, performing a memory slot comparison test and a memory slot synchronization test on the memory slot under test according to the memory slot test command. First, a comparative test is performed on the memory module under test to determine if a target pin exists. If it exists, a synchronous test is then performed to identify the faulty pin from the target pin. If it does not exist, the memory module under test is encapsulated and a comparative test is performed on the memory slot (gold fingers) under test on the motherboard to determine the target pin in the memory slot. Then, a synchronous test is performed to identify the faulty pin from the target pin in the memory slot. Through this series of operations, the efficiency of locating faulty pins on the motherboard is improved. Attached Figure Description

[0149] Figure 1 A flowchart illustrating the method for locating motherboard memory faults;

[0150] Figure 2 A schematic diagram illustrating the steps involved in locating motherboard memory faults;

[0151] Figure 3 A structural example diagram of a voltage acquisition module for locating motherboard memory faults;

[0152] Figure 4 A schematic diagram of the system structure for applying a method to locate motherboard memory faults;

[0153] Figure 5 A schematic diagram of a device for locating motherboard memory faults;

[0154] Figure 6 This is an internal structural diagram of a computer device in an embodiment of the present invention. Detailed Implementation

[0155] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0156] This application provides, as follows: Figure 1 The flowchart illustrates the method for locating motherboard memory faults. When a user needs to locate a fault on a server motherboard, the memory module (the one under test in this case) is first removed from the motherboard. The memory module is then inserted into a voltage acquisition module containing an ADC (Analog-to-digital converter) chip. The voltage acquisition module can be controlled by an FPGA (Field Programmable Gate Array) module to acquire the pin voltage data of each memory module. Then, the impedance comparison value corresponding to each pair of test pins is calculated based on the pin voltage data. When there is an impedance comparison value greater than the difference threshold, the corresponding test pin is identified as the target pin. Then, synchronous testing is performed using reference impedance data to identify the faulty pin from the target pins. When there is no impedance comparison value greater than the difference threshold, it is determined that the memory module under test does not have a faulty pin. At this time, the user needs to reassemble the original memory module under test onto the server motherboard. Then, the same comparison and synchronous testing are performed on the memory slot (or gold fingers) on the motherboard with the memory module under test reassembled, thereby identifying the faulty pin of the memory slot (or gold fingers).

[0157] In one embodiment, such as Figure 2 As shown, the present invention provides a method for locating motherboard memory faults, characterized in that the method includes:

[0158] S201. In response to receiving a memory module test command input by the user through the communication serial port, the voltage acquisition module is controlled to acquire the first pin voltage data of the memory module under test, wherein the memory module test command includes a difference threshold.

[0159] S202. The voltage data of the first pin is numbered in array format according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module.

[0160] S203. In response to the completion of array format numbering processing, generate multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data;

[0161] S204. Determine whether there is one or more pairs of first target pins among the multiple pairs of first test pins based on the multiple first impedance comparison values ​​and the difference threshold;

[0162] S205. If so, then the first faulty pin in the first target pin is determined based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold.

[0163] S206. If not, then in response to receiving the memory slot test command input by the user, perform the memory slot comparison test and memory slot synchronization test of the memory slot under test according to the memory slot test command.

[0164] Specifically, when a user inputs a memory module test command via the communication serial port, a comparative test is first performed simultaneously on multiple memory modules of the same specification on the same motherboard. This is based on the I... 2 C (two-way synchronous serial bus) channel number and ADC chip I 2 The bidirectional two-wire synchronous serial bus information of address C is used to process the collected voltage information into an array format to ensure that the data numbering method of the corresponding pins of the two memory slots is consistent. Then, the impedance comparison value of the test pins with the same data number between multiple memory modules is calculated by comparison test. Then, the impedance comparison value and the difference threshold are determined. When the impedance comparison value is greater than the difference threshold, the test pin corresponding to the impedance comparison value is determined as the target pin. Then, the faulty pin is determined from the target pin after synchronous test using reference impedance data.

[0165] In one embodiment, generating multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data includes:

[0166] Based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module x The first test impedance R of each first test pin is calculated using the following formula. x ;

[0167] R x =(R1*R2*V x ) / (V*R2―V x *R2―R1*V x )

[0168] The multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number.

[0169] Specifically, this voltage acquisition module internally uses a resistor divider to sample the voltage of the corresponding pins, such as... Figure 3As shown, the voltage acquisition module applies a total voltage (external voltage) of V = 3.3V, and the highest voltage obtained through the voltage divider R1 and R2 will not exceed the highest voltage of the memory module pins, ensuring that the applied voltage will not damage the CPU or memory module chips. When the memory is inserted into the testing device, the pin voltage data V can be obtained from an ADC chip similar to the ADS7830. x By utilizing the series and parallel characteristics of resistors and Ohm's law, the first test impedance of each first test pin can be calculated. R2 is connected in parallel with the first test pin and in series with R1. The current is shunted after passing through R1, then conducts to ground through R2 and the first test pin, and finally conducts to ground. The derived formula is Rx = (R1*R2*Vx) / (V*R2―Vx*R2―R1*Vx). Figure 4 As shown, it can be based on I 2 The test impedance R is calculated from the test voltage measured by C0(1-4ADC). X1 And according to I 2 The test impedance R is calculated from the test voltage measured by C6(1-4ADC). X2 The corresponding impedance comparison values ​​are calculated. Furthermore, regardless of whether it's a comparative test or a synchronous test, to improve testing efficiency, based on the characteristics of the memory module, pins with the same power supply characteristics are treated as the same pin. For example, the 286 pins in a single DDR5 (Double Data Rate 5) memory module are simplified to 158 test pins. Using an 8-channel I2C interface ADS7830 to sample the pins under test, 20 ADC chips are needed. Every four ADS7830s are connected to the FPGA's I2C channel. The FPGA can then process the acquired data and store it in an external EEPROM, or print the acquisition results out via the UART (Universal Asynchronous Receiver / Transmitter) port. This means that power supply pins with the same characteristics in the memory module under test can be mapped to the same test pin, improving the efficiency of comparative and synchronous tests. Similarly, after calculating the impedance comparison values ​​for all pairs of test pins with the same number between the two memory modules, it is necessary to compare the impedance comparison values ​​with the difference threshold. For example, if one of the impedance comparison values ​​is greater than the difference threshold, it indicates that there is a significant difference between the pair of test pins corresponding to that impedance comparison value, thus quickly identifying this pair of test pins as target pins (suspected faulty pins). Next, it is necessary to determine whether one or both target pins in this pair are faulty.

[0170] In one embodiment, determining the first faulty pin among the first target pins based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold includes:

[0171] Determine whether the first reference impedance data corresponding to the memory module under test exists in the electrically erasable programmable read-only memory;

[0172] If not, in response to receiving the first reference impedance data measurement instruction input by the user, the first reference impedance data is measured on memory modules of the same type and the first reference impedance data is generated;

[0173] If so, a first impedance synchronization value is generated based on the first reference impedance data and the first target impedance data, and the first faulty pin is determined based on the first impedance synchronization value and the difference threshold.

[0174] Specifically, the system checks if the EEPROM (Erasable Programmable Read-Only Memory) contains reference impedance data corresponding to the memory module under test. If not, it first needs to measure the reference impedance data of a memory module of the same type as the memory module under test. In response to receiving the user's input of the first reference impedance data measurement command, it performs the first reference impedance data measurement on the memory module of the same type and generates the first reference impedance data. If yes, it generates an impedance synchronization value based on the reference impedance data and the target impedance data, and determines the faulty pin in the target pin based on the impedance synchronization value and the difference threshold. When the impedance synchronization values ​​corresponding to both target pins are higher than the difference threshold, it is determined that the target pins of both memory modules are faulty.

[0175] In one embodiment, the step of measuring the first reference impedance data on memory modules of the same type and generating the first reference impedance data includes:

[0176] In response to receiving the first sampling count corresponding to the first reference impedance data input by the user, the first reference voltage value corresponding to the memory module of the same type is obtained through the voltage acquisition module;

[0177] In response to the completion of acquiring the first reference voltage value, the first reference voltage value is acquired again according to the first acquisition count, and the first reference impedance data is generated according to the first reference voltage value corresponding to the first acquisition count.

[0178] Specifically, before the initial synchronous test, the EEPROM does not store the baseline data for the corresponding memory module. Furthermore, the pinouts of memory modules from different manufacturers and platforms vary significantly. Therefore, the baseline impedance data should be re-acquired for different types of memory modules. For example, if the user inputs ten acquisitions, the voltage acquisition module collects the pin voltages of all pins of the same type of memory module and calculates the pin impedance data for all pins. The average impedance is then calculated. The average impedance is calculated using the pin voltage data collected after ten acquisitions. After removing the maximum and minimum values, the average of the average impedances is taken as the baseline impedance data, thus improving the accuracy of the baseline impedance data.

[0179] In one embodiment, the step of performing memory slot comparison testing and memory slot synchronization testing on the memory slot under test according to the memory slot test instructions includes:

[0180] The voltage acquisition module is controlled to acquire the voltage data of the second pin corresponding to the memory slot under test.

[0181] The second pin voltage data is numbered in array format according to the bidirectional binary synchronous serial bus information.

[0182] In response to the completion of the array format numbering processing, multiple second impedance comparison values ​​for multiple pairs of second test pins are generated based on the second pin voltage data;

[0183] Based on the plurality of second impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of second target pins among the plurality of pairs of second test pins;

[0184] If so, the second faulty pin in the second target pin is determined based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

[0185] Specifically, when all impedance comparison values ​​in multiple memory modules are not greater than the difference threshold, it is determined that there are no faulty pins in the memory module under test. At this time, the user needs to encapsulate the original memory module under test onto the server motherboard. Then, in response to receiving the memory slot test command sent by the user, the comparison test and synchronous test are also performed on the memory slot (or gold finger) on the motherboard where the memory module under test is encapsulated, so as to determine the faulty pin of the memory slot (or gold finger).

[0186] In one embodiment, generating multiple second impedance comparison values ​​for multiple pairs of second test pins based on the second pin voltage data includes:

[0187] Based on the first resistor R1, the second resistor R2, the total voltage V, and the second pin voltage data V in the voltage acquisition module y The second test impedance R for each second test pin is calculated using the following formula. y ;

[0188] R y =(R1*R2*V y ) / (V*R2―V y *R2―R1*V y )

[0189] The multiple second impedance comparison values ​​are calculated based on the second test impedance corresponding to the second test pin with the same number.

[0190] Specifically, the voltage acquisition module applies a total voltage (external voltage) of V = 3.3V, and the highest voltage obtained through the voltage divider R1 and R2 will not exceed the highest voltage of the memory slot (or gold finger) pins, ensuring that the applied voltage will not damage the pins of the corresponding chip (such as CPU, memory chip, etc.) in the memory slot. Then, based on the pin voltage data V acquired by the ADS7830... y Using the series and parallel characteristics of resistors and Ohm's law, the second test impedance of each second test pin can be calculated. R2 is connected in parallel with the second test pin and in series with R1. The current is shunted after passing through R1, then grounded after passing through R2 and the second test pin, leading to the derived formula: Ry = (R1*R2*Vy) / (V*R2―Vy*R2―R1*Vy). When based on I... 2 The test impedance R is calculated from the test voltage measured by C5(15-20ADC). y1 And according to I 2 The test impedance R is calculated from the test voltage measured by C10(15-20ADC). y2 Calculate the corresponding impedance comparison value. Similarly, calculate the impedance comparison value for all two test pins with the same number between the two memory slots.

[0191] In one embodiment, determining the second faulty pin in the second target pin based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold includes:

[0192] Determine whether the second reference impedance data corresponding to the memory slot under test exists in the electrically erasable programmable read-only memory;

[0193] If not, in response to receiving the second sampling number corresponding to the second reference impedance data input by the user, the second reference voltage value corresponding to the memory slot of the same type is obtained through the voltage acquisition module;

[0194] In response to the completion of acquiring the reference voltage value, the second reference voltage value is acquired again according to the second acquisition number, and the second reference impedance data is generated according to the second reference voltage value corresponding to the second acquisition number.

[0195] If so, a second impedance synchronization value is generated based on the second reference impedance data and the second target impedance data, and the second faulty pin is determined based on the second impedance synchronization value and the difference threshold.

[0196] Specifically, when comparing the impedance comparison value and the difference threshold, for example, if one of the second impedance comparison values ​​is greater than the difference threshold, it indicates that there is a significant difference between the pair of test pins corresponding to that impedance comparison value, thus identifying this pair of test pins as target pins (suspected faulty pins). Next, it is necessary to determine whether one or both target pins in this pair are faulty. Before performing synchronous testing of the motherboard memory slots (or gold fingers), because the EEPROM does not store the baseline data of the memory slots of the same configuration server motherboard during the initial synchronous test, and the pin differences of memory slots from different manufacturers and platforms are significant, the baseline impedance data should be re-collected for different types of memory slots. For example, if the user inputs eight collection times, the voltage acquisition module collects the pin voltage of all pins in the same type of memory slot and calculates the pin impedance data of all pins, obtaining the average impedance. The average impedance is then calculated using the pin voltage data after eight collections. After removing the maximum and minimum values, the average of the average impedance values ​​is taken as the baseline impedance data. Generally, faulty pins can be located by performing comparative and synchronous tests on the memory module and the packaged memory slot (gold fingers). However, if both the first impedance comparison value corresponding to the memory module and the second impedance comparison value corresponding to the packaged memory slot (or gold fingers) are less than the difference threshold, it indicates that the pins of the memory module and memory slot in the server motherboard are not faulty. In this case, it is highly likely that the fault is in the corresponding pin of the CPU (Central Processing Unit) MIC (Memory Integrated Control, i.e., the memory module in the CPU). The specific method is as shown above. First, perform comparative tests on the pins in the MIC module to determine the target pin, and then perform synchronous tests to determine the faulty pin in the MIC module.

[0197] The proposed solution has the following beneficial effects:

[0198] 1) By conducting rapid impedance comparison tests on the corresponding pins of multiple memory modules, it can be determined whether there are suspected faulty pins in the memory modules. If so, the suspected faulty pins in multiple memory modules are then tested synchronously to identify the faulty pin, which improves the efficiency of locating faulty pins in memory modules.

[0199] 2) If no suspected faulty pins are found in the memory module, impedance comparison tests are then performed on the memory slots or gold fingers of the server motherboard that encapsulates the memory module to identify the suspected faulty pins in the memory slots or gold fingers. Then, synchronous tests are performed to identify the actual faulty pins from the suspected faulty pins, which improves the efficiency of locating faulty pins in the memory slots or gold fingers.

[0200] It should be understood that, although Figure 2The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0201] In one embodiment, such as Figure 5 As shown, a device for locating motherboard memory faults is also provided, characterized in that the device comprises:

[0202] The acquisition module 501 is used to control the voltage acquisition module to acquire the first pin voltage data of the memory module under test in response to receiving a memory module test command input by the user through the communication serial port, wherein the memory module test command includes a difference threshold.

[0203] Processing module 502 is used to perform array format numbering processing on the first pin voltage data according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module;

[0204] The generation module 503 is used to generate multiple pairs of first impedance comparison values ​​for the first test pins based on the first pin voltage data in response to the completion of array format numbering processing.

[0205] The first determining module 504 is used to determine whether there is one or more pairs of first target pins among the multiple pairs of first test pins based on the first impedance comparison value and the difference threshold.

[0206] If the second determining module 505 is such, it is used to determine the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold.

[0207] The memory slot test module 506, if not, is used to respond to the memory slot test command input by the user and perform memory slot comparison test and memory slot synchronization test on the memory slot under test according to the memory slot test command.

[0208] In one embodiment, the generation module generates multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data, including:

[0209] Based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module x The first test impedance R of each first test pin is calculated using the following formula. x ;

[0210] R x =(R1*R2*V x ) / (V*R2―V x *R2―R1*V x )

[0211] The multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number.

[0212] In one embodiment, the second determining module determines the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold, including:

[0213] Determine whether the first reference impedance data corresponding to the memory module under test exists in the electrically erasable programmable read-only memory;

[0214] If not, in response to receiving the first reference impedance data measurement instruction input by the user, the first reference impedance data is measured on memory modules of the same type and the first reference impedance data is generated;

[0215] If so, a first impedance synchronization value is generated based on the first reference impedance data and the first target impedance data, and the first faulty pin is determined based on the first impedance synchronization value and the difference threshold.

[0216] In one embodiment, the second determining module performs a first reference impedance data measurement on memory modules of the same type and generates the first reference impedance data by:

[0217] In response to receiving the first sampling count corresponding to the first reference impedance data input by the user, the first reference voltage value corresponding to the memory module of the same type is obtained through the voltage acquisition module;

[0218] In response to the completion of acquiring the first reference voltage value, the first reference voltage value is acquired again according to the first acquisition count, and the first reference impedance data is generated according to the first reference voltage value corresponding to the first acquisition count.

[0219] In one embodiment, the memory slot testing module performs memory slot comparison testing and memory slot synchronization testing on the memory slot under test according to the memory slot testing instructions, including:

[0220] The voltage acquisition module is controlled to acquire the voltage data of the second pin corresponding to the memory slot under test.

[0221] The second pin voltage data is numbered in array format according to the bidirectional binary synchronous serial bus information.

[0222] In response to the completion of the array format numbering processing, multiple second impedance comparison values ​​for multiple pairs of second test pins are generated based on the second pin voltage data;

[0223] Based on the plurality of second impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of second target pins among the plurality of pairs of second test pins;

[0224] If so, the second faulty pin in the second target pin is determined based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

[0225] In one embodiment, the memory slot testing module generates multiple second impedance comparison values ​​for multiple pairs of second test pins based on the second pin voltage data, including:

[0226] Based on the first resistor R1, the second resistor R2, the total voltage V, and the second pin voltage data V in the voltage acquisition module y The second test impedance R for each second test pin is calculated using the following formula. y ;

[0227] R y =(R1*R2*V y ) / (V*R2―V y *R2―R1*V y )

[0228] The multiple second impedance comparison values ​​are calculated based on the second test impedance corresponding to the second test pin with the same number.

[0229] In one embodiment, the memory slot testing module determines the second faulty pin in the second target pin based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold, including:

[0230] Determine whether the second reference impedance data corresponding to the memory slot under test exists in the electrically erasable programmable read-only memory;

[0231] If not, in response to receiving the second sampling number corresponding to the second reference impedance data input by the user, the second reference voltage value corresponding to the memory slot of the same type is obtained through the voltage acquisition module;

[0232] In response to the completion of acquiring the reference voltage value, the second reference voltage value is acquired again according to the second acquisition number, and the second reference impedance data is generated according to the second reference voltage value corresponding to the second acquisition number.

[0233] If so, a second impedance synchronization value is generated based on the second reference impedance data and the second target impedance data, and the second faulty pin is determined based on the second impedance synchronization value and the difference threshold.

[0234] Specific limitations regarding the fault location device for server motherboards can be found in the above description of the fault location method for server motherboards, and will not be repeated here. Each module in the aforementioned fault location device for server motherboards can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the corresponding operations of each module.

[0235] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements an alarm information processing method. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0236] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0237] In one embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0238] In response to receiving a memory module test command input by the user through the communication serial port, the voltage acquisition module is controlled to acquire the first pin voltage data of the memory module under test, wherein the memory module test command includes a difference threshold.

[0239] The voltage data of the first pin is numbered in array format according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module.

[0240] In response to the completion of array format numbering processing, multiple first impedance comparison values ​​for multiple pairs of first test pins are generated based on the first pin voltage data;

[0241] Based on the plurality of first impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of first target pins among the plurality of pairs of first test pins;

[0242] If so, the first faulty pin in the first target pin is determined based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold.

[0243] If not, in response to receiving the memory slot test command input by the user, the memory slot comparison test and memory slot synchronization test of the memory slot under test are performed according to the memory slot test command.

[0244] In one embodiment, the processor performs the following steps when executing the computer program:

[0245] The process of generating multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data includes:

[0246] Based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module x The first test impedance R of each first test pin is calculated using the following formula. x ;

[0247] R x =(R1*R2*V x ) / (V*R2―V x *R2―R1*V x )

[0248] The multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number.

[0249] In one embodiment, the processor performs the following steps when executing the computer program:

[0250] The step of determining the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold includes:

[0251] Determine whether the first reference impedance data corresponding to the memory module under test exists in the electrically erasable programmable read-only memory;

[0252] If not, in response to receiving the first reference impedance data measurement instruction input by the user, the first reference impedance data is measured on memory modules of the same type and the first reference impedance data is generated;

[0253] If so, a first impedance synchronization value is generated based on the first reference impedance data and the first target impedance data, and the first faulty pin is determined based on the first impedance synchronization value and the difference threshold.

[0254] In one embodiment, the processor performs the following steps when executing the computer program:

[0255] The step of measuring the first reference impedance data of memory modules of the same type and generating the first reference impedance data includes:

[0256] In response to receiving the first sampling count corresponding to the first reference impedance data input by the user, the first reference voltage value corresponding to the memory module of the same type is obtained through the voltage acquisition module;

[0257] In response to the completion of acquiring the first reference voltage value, the first reference voltage value is acquired again according to the first acquisition count, and the first reference impedance data is generated according to the first reference voltage value corresponding to the first acquisition count.

[0258] In one embodiment, the processor performs the following steps when executing the computer program:

[0259] The process of performing memory slot comparison testing and memory slot synchronization testing according to the memory slot test instructions includes:

[0260] The voltage acquisition module is controlled to acquire the voltage data of the second pin corresponding to the memory slot under test.

[0261] The second pin voltage data is numbered in array format according to the bidirectional binary synchronous serial bus information.

[0262] In response to the completion of the array format numbering processing, multiple second impedance comparison values ​​for multiple pairs of second test pins are generated based on the second pin voltage data;

[0263] Based on the plurality of second impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of second target pins among the plurality of pairs of second test pins;

[0264] If so, the second faulty pin in the second target pin is determined based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

[0265] In one embodiment, the processor performs the following steps when executing the computer program:

[0266] The process of generating multiple second impedance comparison values ​​for multiple pairs of second test pins based on the second pin voltage data includes:

[0267] Based on the first resistor R1, the second resistor R2, the total voltage V, and the second pin voltage data V in the voltage acquisition module y The second test impedance R for each second test pin is calculated using the following formula. y ;

[0268] R y =(R1*R2*V y ) / (V*R2―V y *R2―R1*V y )

[0269] The multiple second impedance comparison values ​​are calculated based on the second test impedance corresponding to the second test pin with the same number.

[0270] In one embodiment, the processor performs the following steps when executing the computer program:

[0271] The step of determining the second faulty pin in the second target pin based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold includes:

[0272] Determine whether the second reference impedance data corresponding to the memory slot under test exists in the electrically erasable programmable read-only memory;

[0273] If not, in response to receiving the second sampling number corresponding to the second reference impedance data input by the user, the second reference voltage value corresponding to the memory slot of the same type is obtained through the voltage acquisition module;

[0274] In response to the completion of acquiring the reference voltage value, the second reference voltage value is acquired again according to the second acquisition number, and the second reference impedance data is generated according to the second reference voltage value corresponding to the second acquisition number.

[0275] If so, a second impedance synchronization value is generated based on the second reference impedance data and the second target impedance data, and the second faulty pin is determined based on the second impedance synchronization value and the difference threshold.

[0276] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0277] In response to receiving a memory module test command input by the user through the communication serial port, the voltage acquisition module is controlled to acquire the first pin voltage data of the memory module under test, wherein the memory module test command includes a difference threshold.

[0278] The voltage data of the first pin is numbered in array format according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module.

[0279] In response to the completion of array format numbering processing, multiple first impedance comparison values ​​for multiple pairs of first test pins are generated based on the first pin voltage data;

[0280] Based on the plurality of first impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of first target pins among the plurality of pairs of first test pins;

[0281] If so, the first faulty pin in the first target pin is determined based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold.

[0282] If not, in response to receiving the memory slot test command input by the user, the memory slot comparison test and memory slot synchronization test of the memory slot under test are performed according to the memory slot test command.

[0283] In one embodiment, the computer program performs the following steps when executed by a processor:

[0284] The process of generating multiple first impedance comparison values ​​for multiple pairs of first test pins based on the first pin voltage data includes:

[0285] Based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module x The first test impedance R of each first test pin is calculated using the following formula. x ;

[0286] R x =(R1*R2*V x ) / (V*R2―V x *R2―R1*V x )

[0287] The multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number.

[0288] In one embodiment, the computer program performs the following steps when executed by a processor:

[0289] The step of determining the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold includes:

[0290] Determine whether the first reference impedance data corresponding to the memory module under test exists in the electrically erasable programmable read-only memory;

[0291] If not, in response to receiving the first reference impedance data measurement instruction input by the user, the first reference impedance data is measured on memory modules of the same type and the first reference impedance data is generated;

[0292] If so, a first impedance synchronization value is generated based on the first reference impedance data and the first target impedance data, and the first faulty pin is determined based on the first impedance synchronization value and the difference threshold.

[0293] In one embodiment, the computer program performs the following steps when executed by a processor:

[0294] The step of measuring the first reference impedance data of memory modules of the same type and generating the first reference impedance data includes:

[0295] In response to receiving the first sampling count corresponding to the first reference impedance data input by the user, the first reference voltage value corresponding to the memory module of the same type is obtained through the voltage acquisition module;

[0296] In response to the completion of acquiring the first reference voltage value, the first reference voltage value is acquired again according to the first acquisition count, and the first reference impedance data is generated according to the first reference voltage value corresponding to the first acquisition count.

[0297] In one embodiment, the computer program performs the following steps when executed by a processor:

[0298] The process of performing memory slot comparison testing and memory slot synchronization testing according to the memory slot test instructions includes:

[0299] The voltage acquisition module is controlled to acquire the voltage data of the second pin corresponding to the memory slot under test.

[0300] The second pin voltage data is numbered in array format according to the bidirectional binary synchronous serial bus information.

[0301] In response to the completion of the array format numbering processing, multiple second impedance comparison values ​​for multiple pairs of second test pins are generated based on the second pin voltage data;

[0302] Based on the plurality of second impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of second target pins among the plurality of pairs of second test pins;

[0303] If so, the second faulty pin in the second target pin is determined based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

[0304] In one embodiment, the computer program performs the following steps when executed by a processor:

[0305] The process of generating multiple second impedance comparison values ​​for multiple pairs of second test pins based on the second pin voltage data includes:

[0306] Based on the first resistor R1, the second resistor R2, the total voltage V, and the second pin voltage data V in the voltage acquisition module y The second test impedance R for each second test pin is calculated using the following formula. y ;

[0307] R y =(R1*R2*V y ) / (V*R2―V y *R2―R1*V y )

[0308] The multiple second impedance comparison values ​​are calculated based on the second test impedance corresponding to the second test pin with the same number.

[0309] In one embodiment, the computer program performs the following steps when executed by a processor:

[0310] The step of determining the second faulty pin in the second target pin based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold includes:

[0311] Determine whether the second reference impedance data corresponding to the memory slot under test exists in the electrically erasable programmable read-only memory;

[0312] If not, in response to receiving the second sampling number corresponding to the second reference impedance data input by the user, the second reference voltage value corresponding to the memory slot of the same type is obtained through the voltage acquisition module;

[0313] In response to the completion of acquiring the reference voltage value, the second reference voltage value is acquired again according to the second acquisition number, and the second reference impedance data is generated according to the second reference voltage value corresponding to the second acquisition number.

[0314] If so, a second impedance synchronization value is generated based on the second reference impedance data and the second target impedance data, and the second faulty pin is determined based on the second impedance synchronization value and the difference threshold.

[0315] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0316] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0317] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for locating motherboard memory faults, characterized in that, The method includes: In response to receiving a memory module test command input by the user through the communication serial port, the voltage acquisition module is controlled to acquire the first pin voltage data of the memory module under test, wherein the memory module test command includes a difference threshold. The voltage data of the first pin is numbered in array format according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module. In response to the completion of array format numbering processing, based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module. x The first test impedance R of each first test pin is calculated using the following formula. x ; R x = (R1*R2*V x ) / (V*R2-V x *R2-R1*V x ); Multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number. Based on the plurality of first impedance comparison values ​​and the difference threshold, determine whether there is one or more pairs of first target pins among the plurality of pairs of first test pins; If so, the first faulty pin in the first target pin is determined based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold. If not, in response to receiving the memory slot test command input by the user, perform memory slot comparison test and memory slot synchronization test of the memory slot under test according to the memory slot test command; The step of performing memory slot comparison testing and memory slot synchronization testing according to the memory slot test command includes: controlling the voltage acquisition module to acquire the second pin voltage data corresponding to the memory slot under test; performing array format numbering processing on the second pin voltage data according to the bidirectional binary synchronous serial bus information; in response to the completion of the array format numbering processing, generating multiple second impedance comparison values ​​for multiple pairs of second test pins according to the second pin voltage data; determining whether there is one or more pairs of second target pins among the multiple pairs of second test pins according to the multiple second impedance comparison values ​​and the difference threshold; if so, determining the second fault pin among the second target pins according to the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

2. The method according to claim 1, characterized in that, The step of determining the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold includes: Determine whether the first reference impedance data corresponding to the memory module under test exists in the electrically erasable programmable read-only memory; If not, in response to receiving the first reference impedance data measurement instruction input by the user, the first reference impedance data is measured on memory modules of the same type and the first reference impedance data is generated; If so, a first impedance synchronization value is generated based on the first reference impedance data and the first target impedance data, and the first faulty pin is determined based on the first impedance synchronization value and the difference threshold.

3. The method according to claim 2, characterized in that, The step of measuring the first reference impedance data of memory modules of the same type and generating the first reference impedance data includes: In response to receiving the first sampling count corresponding to the first reference impedance data input by the user, the first reference voltage value corresponding to the memory module of the same type is obtained through the voltage acquisition module; In response to the completion of acquiring the first reference voltage value, the first reference voltage value is acquired again according to the first acquisition count, and the first reference impedance data is generated according to the first reference voltage value corresponding to the first acquisition count.

4. The method according to claim 1, characterized in that, The process of generating multiple second impedance comparison values ​​for multiple pairs of second test pins based on the second pin voltage data includes: Based on the first resistor R1, the second resistor R2, the total voltage V, and the second pin voltage data V in the voltage acquisition module y The second test impedance R for each second test pin is calculated using the following formula. 𝑦 ; R y = (R1* R2*V y ) / (V*R2-V y *R2-R1*V y ) The multiple second impedance comparison values ​​are calculated based on the second test impedance corresponding to the second test pin with the same number.

5. The method according to claim 1, characterized in that, The step of determining the second faulty pin in the second target pin based on the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold includes: Determine whether the second reference impedance data corresponding to the memory slot under test exists in the electrically erasable programmable read-only memory; If not, in response to receiving the second sampling number corresponding to the second reference impedance data input by the user, the second reference voltage value corresponding to the memory slot of the same type is obtained through the voltage acquisition module; In response to the completion of acquiring the reference voltage value, the second reference voltage value is acquired again according to the second acquisition number, and the second reference impedance data is generated according to the second reference voltage value corresponding to the second acquisition number. If so, a second impedance synchronization value is generated based on the second reference impedance data and the second target impedance data, and the second faulty pin is determined based on the second impedance synchronization value and the difference threshold.

6. A device for locating motherboard memory faults, characterized in that, The device includes: The acquisition module is used to control the voltage acquisition module to acquire the first pin voltage data of the memory module under test in response to receiving a memory module test command input by the user through the communication serial port, wherein the memory module test command includes a difference threshold. The processing module is used to perform array format numbering processing on the first pin voltage data according to the bidirectional binary synchronous serial bus information corresponding to the voltage acquisition module; The generation module is used to, in response to the completion of array format numbering processing, generate data based on the first resistor R1, the second resistor R2, the total voltage V, and the first pin voltage data V in the voltage acquisition module. x The first test impedance R of each first test pin is calculated using the following formula. x ; R x = (R1*R2*V x ) / (V*R2-V x *R2-R1*V x ); Multiple first impedance comparison values ​​are calculated based on the first test impedance corresponding to the first test pin with the same number. The first determining module is used to determine whether there is one or more pairs of first target pins among multiple pairs of first test pins based on the first impedance comparison value and the difference threshold. If the second determining module is used, it is used to determine the first faulty pin in the first target pin based on the first reference impedance data, the first target impedance data corresponding to the first target pin, and the difference threshold. The memory slot testing module, if not, is used to respond to the memory slot testing command input by the user and perform memory slot comparison test and memory slot synchronization test on the memory slot under test according to the memory slot testing command; The step of performing memory slot comparison testing and memory slot synchronization testing according to the memory slot test command includes: controlling the voltage acquisition module to acquire the second pin voltage data corresponding to the memory slot under test; performing array format numbering processing on the second pin voltage data according to the bidirectional binary synchronous serial bus information; in response to the completion of the array format numbering processing, generating multiple second impedance comparison values ​​for multiple pairs of second test pins according to the second pin voltage data; determining whether there is one or more pairs of second target pins among the multiple pairs of second test pins according to the multiple second impedance comparison values ​​and the difference threshold; if so, determining the second fault pin among the second target pins according to the second reference impedance data, the second target impedance data corresponding to the second target pin, and the difference threshold.

7. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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