Memory subsystem addressing for data and additional data portions

Abstract

This document describes systems, apparatus, and methods related to addressing a memory subsystem for data and additional data portions. In an example method, addressing for data and additional data portions may include accessing data written to a memory device in response to receiving a first command configured according to a nondeterministic memory interface protocol. The first command may be a high-speed link CXL protocol compliance command. The example method may further include translating the address associated with the first command into a second command configured according to a standardized deterministic memory interface protocol. The second command may be a DRAM accessibility command. The example method may further include accessing a memory cell page of the memory device in which the data is written, and wherein the additional data portion associated with the data is written using the translated address associated with the first command.

Description

Technical Field

[0001] This disclosure generally relates to devices, systems, and methods for addressing data and additional data portions. Background Technology

[0002] Memory devices are typically provided as internal components of computers or other electronic systems, in semiconductors, or integrated circuits. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (such as host data, error data, etc.) and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Thyristor Random Access Memory (TRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, and resistive variable memory, such as Phase-Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Magnetoresistive Random Access Memory (MRAM), such as Spin Torque Transfer Random Access Memory (STT RAM), etc.

[0003] A memory device may be coupled to a host computer (e.g., a host computing device) to store data, commands, and / or instructions for use by the host computer or electronic system during operation. For example, data, commands, and / or instructions may be transferred between the host computer and the memory device during operation of the computing or other electronic system. Summary of the Invention

[0004] Embodiments of this disclosure provide a method for data addressing, comprising: accessing data written to a memory device in response to receiving a first command configured according to a nondeterministic memory interface protocol; translating an address associated with the first command to an address associated with a second command configured according to a standardized deterministic memory interface protocol; and accessing a memory cell page of the memory device in which the data is written, wherein additional data portions associated with the data are written using the second command including the translated address.

[0005] Another embodiment of this disclosure provides an apparatus for data addressing, comprising: a memory controller configured to receive commands associated with a plurality of memory cells in a memory device; and a processing means coupled to the plurality of memory cells, the processing means: receiving signaling instructing access to data in a memory cell page of the memory device according to a Computational High-Speed ​​Link (CXL) protocol; converting an address associated with the signaling to a DRAM-accessible address, wherein the conversion includes determining a sector in which the memory cell page is located; and accessing the page in the sector of the memory device associated with the data, wherein the data and associated Cyclic Redundancy Check (CRC) data are located in the page.

[0006] Another embodiment of this disclosure provides a system for data addressing, comprising: a host that sends commands configured according to a nondeterministic memory interface protocol; a memory device coupled to the host, the memory device including: a memory array including a plurality of memory cells; and a memory controller coupled to the memory array, the memory controller: receiving the commands, wherein the commands are associated with a 64-byte data portion; determining the location of the data portion within a memory page and within a sector in the memory array, wherein: the sector includes a plurality of data entries, wherein each of the plurality of entries includes data and corresponding CRC data; and the location within the memory page is based on a sector offset; and accessing the memory page associated with the data portion in the sector of the memory device. Attached Figure Description

[0007] Figure 1 An example computing system including a memory system is shown according to several embodiments of the present disclosure.

[0008] Figure 2 An example functional diagram showing a memory cell arranged in rows according to several embodiments of the present disclosure is illustrated.

[0009] Figure 3A This is an example functional diagram of a row of memory cells containing entries, according to several embodiments of the present disclosure.

[0010] Figure 3B This is an example functional diagram of a portion of CRC data associated with an entry, according to several embodiments of the present disclosure.

[0011] Figure 4A This is an example portion of a sector-associated memory array according to several embodiments of the present disclosure.

[0012] Figure 4B-C are each an instance location of a portion of data stored in a sector according to several embodiments of this disclosure.

[0013] Figure 5 The diagram illustrates an example method for addressing data and CRC data according to several embodiments of the present disclosure. Detailed Implementation

[0014] This document describes system apparatuses and methods related to addressing data and additional data portions (e.g., Cyclic Redundancy Check (CRC) data, Error Correction Code (ECC) data, etc.). Data stored within memory cells of a memory device can be located using addresses. The address of the data can be associated with a location within a group of memory cells, a page, a portion of a memory array, etc. In some instances, the data can be associated with commands configured according to a nondeterministic memory interface protocol, such as a computed high-speed link (CXL) command, and the command (e.g., a CXL command) can be associated with a specific size of the data (e.g., 64 bytes). When locating data in a memory device (e.g., a DRAM memory device, or a low-power DRAM memory device), cyclic redundancy check (CRC) data can be associated with the data to protect the integrity of the data. CRC data can add an offset to entries of the data (e.g., 64-byte entries, as associated with a CXL command), and thus make it difficult to maintain an address associated with an exponent or factor of two (2). Furthermore, ECC data can be used to correct the data.

[0015] For example, a data entry might contain 64 bytes of data (referred to as an "entry") and 4 bytes of CRC data associated with the data entry. In this example, a single entry might be associated with a size of 68 bytes (data plus CRC data), which would be more complex for address calculation because the 68 bytes are not evenly distributed across a data page (e.g., 2,048 bytes of data) or other data portions that are typically factors or exponents of two (2). Since a data page can be the amount of data accessed in a single access (e.g., a read or write operation), it is helpful to store entries within the page size to contain both data and CRC data.

[0016] Cyclic Redundancy Check (CRC) refers to an error detection code commonly used in digital networks and storage devices to detect unexpected alterations to the original data. A short check value is attached to a block of data entering these systems based on the remainder of a polynomial division of its contents. During retrieval, this can be repeated, and corrective action can be taken for data corruption if the check values ​​do not match. CRC can be used in error correction systems to detect errors. Furthermore, CRC is so named because the check (data verification) value is redundant (it extends the message without adding information) and can be based on a cyclic code. CRC can be used because it is simple to implement in binary hardware, easy to analyze, and particularly good at detecting common errors caused by noise in the transmission channel. Because the check value has a fixed length, the resulting function can be used as a hash function.

[0017] Additionally, sectors can be created in the memory array to accommodate channel throughput while still transmitting the same amount of data as when CRC data is not included in the total storage space. In some instances, and as will be further described below, a sector may contain 512 entries, with each page containing 30 entries (in addition to 2 bytes of CRC data and / or metadata). However, the 512 entries are not evenly distributed across the pages (because 512 is not divisible by 30), so these sectors will have an offset number and other determinations to locate a portion of the data. In some prior methods, additional address bits can be used to handle these offsets and uneven distributions due to inconsistencies between the CXL command and the corresponding data size and the DRAM (e.g., low-power DDR memory devices) and CRC data size (e.g., data pages). As will be described herein, a smaller number of address bits than those used in prior methods can be used to determine the location of data portions without incurring additional data overhead (e.g., storage and data transfer time).

[0018] As used herein, “memory cell set” or “set” refers to a physical arrangement of memory cells, such as a row of memory cells or a portion of a row of memory cells, and other possible configurations of memory cells. As used herein, “memory cell row” or “row” refers to an arrangement of memory cells that can be activated together (e.g., via an access line). Each row may contain several pages. As used herein, the terms “page” and “memory cell page” may be used interchangeably. As used herein, “page” refers to a unit that is programmed and / or sensed (e.g., several memory cells that are programmed and / or sensed together as a functional group). In some embodiments, each row (or a subset of rows) may include a memory cell page.

[0019] In some embodiments, the memory system may be a Compute Express Link (CXL) compliant memory system (e.g., the memory system may include a PCIe / CXL interface). CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to enhance the performance of next-generation data centers. CXL technology maintains memory coherence between the CPU memory space and the memory on the attached device, allowing resource sharing to achieve higher performance, reduced software stack complexity, and lower overall system cost.

[0020] With the increasing use of accelerators to supplement CPUs to support emerging applications such as artificial intelligence and machine learning, CXL is designed as an industry-open standard interface for high-speed communications. Built on the Peripheral Component Interconnect High Speed ​​(PCIe) infrastructure, CXL technology utilizes PCIe physical and electrical interfaces to provide advanced protocols in areas such as input / output (I / O) protocols, memory protocols (e.g., initially allowing the host to share memory with the accelerator), and coherence interfaces. In some embodiments, CXL technology may include multiple I / O channels configured to transmit multiple commands to or from circuitry outside the memory controller at a rate of approximately thirty-two (32) gigabits per second. In another embodiment, CXL technology may include a Peripheral Component Interconnect High Speed ​​(PCIe) 5.0 interface coupled to the multiple I / O channels, wherein the memory controller receives commands relating to at least one of a memory device, a second memory device, or any combination thereof via the PCIe 5.0 interface according to a compute high-speed link memory system.

[0021] In the following detailed description of this disclosure, reference is made to the accompanying drawings, which form a part of this disclosure, and the drawings illustrate by way of illustration one or more embodiments of this disclosure. These embodiments are described in sufficient detail to enable those skilled in the art to practice embodiments of this disclosure, and it should be understood that other embodiments may be utilized and process, electrical, and structural changes may be made without departing from the scope of this disclosure.

[0022] As used herein, designators such as “M” specifically relating to reference numerals in the drawings indicate that a number of specific features may be included. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may include both a single designation and multiple designations. Additionally, “several,” “at least one,” and “one or more” (e.g., several sound devices) may refer to one or more sound devices, while “multiple” is intended to mean more than one such thing. Furthermore, the words “may” and “may” are used throughout this application in a permissive sense (i.e., possible, able) rather than a mandatory sense (i.e., must). The term “comprising” and its derivatives mean “including but not limited to.” Depending on the context, the term “coupled / coupling” means a physical, direct or indirect connection or access to and movement (transmission) of commands and / or data.

[0023] The figures in this document follow a numbering rule, wherein the first one or more digits correspond to the figure number, and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. Generally, a single element symbol may be used herein to refer to a group or multiple elements or components. For example, multiple reference elements 203-0...203-M (e.g., 203-0 to 203-M) may generally be referred to as 203. As will be understood, elements shown in the various embodiments herein may be added, interchanged, and / or removed to provide multiple additional embodiments of this disclosure. In addition, the scale and / or relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of this disclosure and should not be considered as limiting.

[0024] Figure 1 Example computing system 100 including memory system 110 according to several embodiments of the present disclosure is illustrated. As used herein, "device" may refer to, but is not limited to, any of a variety of structures or combinations thereof, such as a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. In some embodiments, computing system 100 may include memory system 110, which includes memory controller 115 and memory devices 130, 140. Computing system 100 may be coupled to host system 120.

[0025] In some embodiments, memory controller 115 may be configured to manage DRAM memory devices. Memory devices 130, 140 may provide main memory for computing system 100 or may be used as additional memory or storage devices throughout computing system 100. In some embodiments, memory devices 130, 140 may be ferroelectric field-effect transistor (FeFET) memory devices. In another embodiment, memory devices 130, 140 may be dynamic random access memory (DRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (ReRAM) devices, or any combination thereof. Memory devices 130, 140 may include one or more arrays of memory cells, such as volatile and / or non-volatile memory cells. In various embodiments, memory devices 130, 140 may include at least one array of volatile memory cells. Embodiments are not limited to a particular type of memory device. For example, memory devices may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, etc. Although shown as two memory devices 130, 140, it should be understood that the scope of this disclosure covers a single memory device or three or more memory devices.

[0026] The memory system 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory systems 110. In some embodiments, the host system 120 is coupled to memory systems 110 of different types. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect communication connection (e.g., with an intermediate component) or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0029] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., a dynamic memory controller), and a memory protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory system 110 to execute commands. As used herein, the term "command" refers to instructions from a memory system for performing a task or function. For example, memory controller 115 of memory system 110 may cause processing device 117 to perform a task based on a given command. In some embodiments, a command may include a memory request. That is, a command may be a request to read data from and / or write data to a memory device (e.g., a second memory device 130 and / or a first memory device 140). Host system 120 may, for example, write data to and read data from memory system 110 based on a command (e.g., a memory request).

[0030] Host system 120 can be coupled to memory system 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Compute High Speed ​​Link (CXL) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory system 110. When memory system 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize interface access components (e.g., memory devices 130, 140). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory system 110 and host system 120. Generally, host system 120 can access multiple memory systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] In various embodiments, memory controller 115 may generate status information, which may be transmitted to or from host system 120, for example, via sideband channel 157. Sideband channel 157 may be independent of (e.g., separate from) a dual data rate (DDR) memory interface and / or non-volatile memory high-speed (NVMe) interface used to transmit (e.g., transfer) DDR commands and / or NVM commands between host system 120 and memory device 110. That is, in some embodiments, sideband channel 157 may be used to transmit commands causing bit vector operations from host system 120 to memory device 110, while a control bus (not shown) is used to transmit DRAM commands and / or NVM commands from host system 120 to memory device 110. Memory devices 130, 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Examples of volatile memory devices may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Examples of non-volatile memory devices may include, but are not limited to, read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0033] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 and 140 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 and 140 may be grouped into pages, and a page may refer to a logical cell of the memory device used to store data. In some embodiments, a memory cell page may include one or more rows of memory cells. Alternatively, a row of memory cells may include one or more sets of memory cells.

[0034] Memory controller 115 (or simply controller 115) can communicate with memory devices 130, 140 to perform operations such as reading data, writing data, erasing data, and other such operations at memory devices 130, 140. Memory controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. Memory controller 115 may be a microcontroller, dedicated logic circuitry (e.g., field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] Although the instance storage system 110 has Figure 1 The memory system 110 is shown to include a memory controller 115, but in another embodiment of this disclosure, the memory system 110 does not include a memory controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory system).

[0036] Generally, the memory controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between host addresses (e.g., host physical address (HPA)) and device addresses (e.g., device physical address (DPA)) associated with memory devices 130 and 140. The memory controller 115 may further include a host interface circuitry that communicates with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the second memory device 130 and / or the first memory device 140, and translate responses associated with the second memory device 130 and / or the first memory device 140 into information for the host system 120.

[0037] The memory system 110 may also include additional circuitry or components not shown. In some embodiments, the memory system 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory controller 115 and decode the addresses to access the second memory device 130 and / or the first memory device 140.

[0038] The memory subsystem 110 includes an address component 113, which can be configured to schedule and / or perform operations to perform addressing operations and can be implemented using various components, data paths, and / or interfaces of the memory subsystem 110. The address component 113 may include various circuitry to facilitate determining the location of portions of memory to be read and / or written using address data associated with memory cells of the memory devices 130, 140. For example, the address component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry or software and / or firmware, which allows the address component 113 to schedule and / or perform data storage operations associated with accessing data and CRC data in memory cells to protect data integrity and transfer data to various components, data paths, and / or interfaces of the memory subsystem 110.

[0039] Address component 113 may be communicatively coupled to memory devices 130 and 140 and may access the internal data paths of memory devices 130 and 140, memory subsystem 110 and / or the interface of memory subsystem 110 to perform the operations described herein and / or transfer stored data to additional elements of memory subsystem 110.

[0040] In some embodiments, the memory subsystem controller 115 includes at least a portion of the address component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the address component 113 is part of a host system 110 (not shown), an application program, or an operating system.

[0041] As discussed herein, memory system 110 may receive a command from host 120 to access a portion of data. In some instances, the command may be a CXL command and may be associated with 64 bytes of data. Due to the size of this data portion, the addressing of the data and / or its storage may be associated with this data size in memory system 110 (e.g., memory devices 130, 140). For example, each data entry may be 64 bytes, and a specific number of entries may be stored per page. For instance, 30 entries consisting of 64 bytes may be stored in a page (totaling 1,920 bytes), and 128 bytes of CRC data and / or metadata may be stored in said page and associated with the other 30 entries of said data page (totaling 2,048 bytes or 2kB together with the data and CRC data in said page).

[0042] Furthermore, for example, in some embodiments, the memory controller 115 may receive a first command (e.g., a CXL command or CXL compliance command) associated with a set of memory cells in a memory device (e.g., a second memory device 130 and / or a first memory device 140) that corresponds to a data unit size (e.g., 64 bytes) for a CXL command, the memory device comprising a plurality of memory cell sets corresponding to a respective portion of a memory cell array of memory. The command may be associated with a request to read data from the memory system 110 (e.g., a read request) or a request to write data to the memory system 110 (e.g., a write request). The memory controller 115 may activate the memory cell set in response to the command to perform memory access to the memory. For example, the memory controller 115 may cause the memory cell set to be activated to write data to the memory device. Similarly, the memory controller 115 may cause the memory cell set to be activated to read data stored on the memory device. As used herein, the term “activation” refers to the action of opening a row, set, and / or page to allow data reading and / or writing to said row, set, and / or page after opening. For example, one or more row access commands can be asserted on rows, sets, and / or pages of a memory cell to cause data (e.g., charge) stored in the memory cell to be read by the circuitry associated with the memory device.

[0043] Figure 2 Example functional diagram 221 is shown, illustrating a memory cell arranged in rows according to several embodiments of the present disclosure. Functional diagram 221 can be used with a computer system (e.g., Figure 1 The computer system 100) is used in conjunction with it. Functional diagram 221 can be used in several memory devices (e.g., for example, Figure 1 The memory devices 130, 140 are located within the memory. The functional diagram may include an array 209 of memory cells 203-0 to 203-M, a row decoder 223, a row buffer 225, multiple sense amplifiers 206-1 to 206-U, and a multiplexer 227.

[0044] Array 209 comprises memory cells (generally referred to as memory cells 203, and more specifically as 203-0 to 203-J) coupled to rows of access lines 204-0, 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, ..., 204-R (generally referred to as access lines 204) and columns of sensing lines 205-0, 205-1, 205-2, 205-3, 205-4, 205-5, 205-6, 205-7, ..., 205-S (generally referred to as sensing lines 205). Furthermore, the array 209 of memory cells is not limited to a specific number of access lines and / or sensing lines, and the use of the terms "row" and "column" does not refer to a specific physical structure and / or orientation of the access lines and / or sensing lines. Although not depicted, each column of memory cells may be associated with a corresponding pair of complementary sensing lines.

[0045] Each column of the memory cell can be coupled to a plurality of corresponding sense amplifiers 206-0, 206-1, 206-2, 206-3, 206-4, 206-5, 206-6, 206-7, ..., 206-U, which are coupled to corresponding sense lines 205-0, 205-1, 205-2, 205-3, 205-4, 205-5, 205-6, 205-7, ..., 205-S. Each of the corresponding sense amplifiers 206 is coupled to a row buffer 225 for storing data accessed from the memory cell 203. For example, the memory cell 203 can be selectively activated via a decoding line to transfer data sensed by the corresponding sense amplifiers 206-0 to 206-U to the row buffer 225.

[0046] In some embodiments, the memory controller (e.g. Figure 1 The memory controller 115 can receive a first command and initiate a first activation of a first row of cells coupled to access line 204-0. Activation of the first row of cells can initiate memory access to one or more memory devices. As used herein, row activation can include activation of all rows or activation of a subset of rows. For example, row activation can include activating all transistors in each cell 203-0, 203-1, 203-2, 203-3, 203-4, ..., 203-M in the row, or it can include activating some but not all transistors on the row (a subset of cells 203-0 to 203-M). Row activation (or similarly, activation of a subset of rows) can permit information to be stored on or accessed from the row.

[0047] In some embodiments, such as Figure 2As shown, multiplexer 227 can be used to select specific data in row buffer 225 corresponding to a cell column. For example, a row address can be input to row decoder 223 to indicate which row to access, and a column address can be input to multiplexer 227 to indicate which data associated with a column in row buffer 225 to select, so that specific data from a specific cell can be selected. The selected data can then be transmitted out of multiplexer 227.

[0048] Figure 3A This is an example functional diagram 312 of a memory cell row 335 including entry 337, according to several embodiments of the present disclosure. In this example, the memory cell row 335 may store thirty (30) data entries, for example, data entry 0 (“0”) 337-0 to data entry 29 (“29”) 337-29, and CRC data portion 313. Although shown as not including some entries, it should be understood that entries 7 337-7 to 25 337-25 are consecutive (indicated by dotted lines). Figure 3A For the purpose of this explanation, column address row 331 contains several column addresses 333, ranging from column address 0 (“0”) 333-0 to column address 63 (“63”) 333-63. Each column address can represent 32 bytes of information, thus two column addresses are used for a single entry. For example, column address 0 333-0 and column address 1 333-1 are used for data entry 0 337-0.

[0049] like Figure 3A As explained, there are 30 data entries 337 and two cyclic redundancy check (CRC) data entries 339-1 and 339-2, each of which is 64 bytes in size. Therefore, the total length of line 335 is 2,048 bytes (or 2kB). Similarly, since there are 64 column addresses 333, each 32 bytes, the total number of column address spaces is also 2,048 bytes (or 2kB).

[0050] Figure 3B This is an example functional diagram of several embodiments of the present disclosure, including a CRC data portion 313 associated with an entry. Figure 3B The CRC data portion 313 in the middle can be related to Figure 3A The CRC data portion 312. The first line of the CRC data 333-60 contains portions 0 (341-0) to 7 (341-7) of the CRC data, and corresponds to the data stored in... Figure 3A The CRC data at column addresses 333-60. Furthermore, the second row of the CRC data, 333-61, contains parts 8 (341-8) to 15 (341-15) of the CRC data, and corresponds to the data stored in... Figure 3AThe CRC data at column address 333-61. The third row of the CRC data, 333-62, contains the 16th part (341-16) to the 23rd part (341-23) of the CRC data, and corresponds to the data stored in... Figure 3A The CRC data at column address 333-62. The fourth row of the CRC data, 333-63, contains the 24th part (341-24) to the 31st part (341-31) of the CRC data, and corresponds to the data stored in... Figure 3A The CRC data at column addresses 333-63.

[0051] A line of byte position 345 indicates the byte position used for CRC data within each CRC portion 341. For example, portion 0 of the CRC data 341-0 is stored across byte position 0 to byte position 2 347-2, indicating that the length of CRC data portion 341-0 is 3 bytes. Furthermore, this portion 0 of the CRC data 341-0 is associated with metadata 343-0, which is one byte in length. Although shown as 3 bytes in length, the CRC data can range from 24 bits (3 bytes) to 28 bits. Similarly, although shown as one byte in size, the metadata can range from 4 bits to 8 bits (corresponding to whether the CRC data size is less or more bits / byte). In this way, the CRC data and metadata are stored at the end of the data page, and each portion of the CRC data corresponds to a data entry (and protects its integrity). And, as... Figure 3B As explained, the last two parts of the CRC data, 343-30 and 343-31, are not concatenated to the data because... Figure 3A There are only 30 entries, and they can be reserved for other purposes.

[0052] Figure 4A This is an example portion 414 of a sector-associated memory array according to several embodiments of the present disclosure. Portion 414 of the memory array may include a plurality of memory cell rows 453-0 to 453-7 (hereinafter collectively referred to as memory cell rows 453). Each of the memory cell rows 453 may include a channel for transferring data to a location, such as channel 0 451-0 to channel 14 451-14. Data pages may be stored in each of the memory cell rows 453 corresponding to a particular channel. For example, a first data page may be stored in row 453-0 at channel 451-0, a second data page may be stored in row 453-0 at channel 451-1, and so on. In this way, there are 15 data pages stored across the first row 453-0.

[0053] Although shown as containing 15 channels (e.g., channels 0 451-0 to 14 451-14), instances may not be limited to this. For example, channel 16 (which in the illustration extends exactly through channel 14 451-14) could be used to store the corresponding parity data. While in the configuration of logical data, channel 15 could be stored adjacent to and parity data could be stored adjacent to channel 14 451-14, the physical storage of the parity data could differ. Each of the channels has a channel offset of 455, which increases in increments of 30 from channel 0 451-0 to channel 14 451-14. For example, channel 0 451-0 has an offset of "0", channel 1 451-1 has an offset of "30", and so on, indicating the number of entries preceding the channel, such that there are 30 entries before channel 451-1, 60 entries before channel 451-2, and so on.

[0054] For example, since some parity values ​​are accessed multiple times and in a repetitive manner, the channels where they are physically stored can be scrambled to achieve more even utilization. This can be achieved by using a bitwise XOR operation on the logical channel bits for the data row address bits (e.g., DDR row address bits). Thus, the parity data corresponding to the first row 453-0 can be physically stored in this 15th channel (and logically in the 15th channel), and the parity data corresponding to the second row 453-1 can be physically stored in the 14th channel (and logically still in the 15th channel). Furthermore, the parity data corresponding to the third row 453-2 can be physically stored in the 13th channel (and logically still in the 15th channel), and so on, until each of the rows 453 is passed.

[0055] One of the channels described above is used for the parity bit (and in Figure 4A In this 16-channel architecture (shown and further described below, with 15 channels for data entries and CRC data), a RAID stripe architecture can be used. A RAID stripe can contain 15 data entries and a parity entry. Data and parity entries can have 64 bytes of data, CRC bits, and metadata bits. The metadata bits can include: 2 bits for Meta0, 1 ​​bit for host poison, and 1 bit for device poison. The 16 entries of a RAID stripe can be distributed across 16 channels, thus allowing the use of 16 different memory devices. The entries of a given RAID stripe can be addressed using the same chip select, group address, row address, and column address.

[0056] Referring to the poison bit, data received from the host (e.g., to a memory system) may be incorrect or corrupted. Such incorrect or corrupted data may be referred to as "poisoned data." A poisoned data unit (e.g., a bit) can be used to indicate whether received data is poisoned. A poisoned data unit may be received, for example, as part of a write command. For example, a poison bit value "1" may indicate that received data corresponding to a write command is poisoned data, and a poison bit value "0" may indicate that received data corresponding to a write command is not poisoned data. Embodiments are not limited to this. For example, a poison bit value "1" may be used to indicate poisoned data, and a bit value "0" may be used to indicate that data is not poisoned data. A host poison bit may indicate that data from the host is corrupted, and / or a device poison bit may indicate that data stored in the device is corrupted, and so on.

[0057] Because the difference between the 64-byte fragment used for CXL commands and the storage of data and CRC data is greater than that of a 68-byte fragment (e.g., a 64-byte fragment with 64 bytes of data and 4 bytes of CRC data and metadata), a conversion from CXL commands to their actual location within the memory device can be performed. This conversion may involve division by multiples of 30, since 30 entries are used per page to accommodate the additional CRC data and metadata, as described above. However, to reduce the amount of divisor bits used, some address bits can be directly mapped to memory device address bits by calculating column addresses, channel selectors, and row bits (e.g., R[15:13]) through division. To perform this conversion, the CXL address space can be divided into 7 sectors, identified by sector values ​​(e.g., “sectorID”).

[0058] Furthermore, address bit assignments are indicated by Table 1 shown below, and may correspond to which number / type of bits will be used for which address-related physical capacity type. As illustrated in Table 1, the three most significant address bits can be assigned to the SectorID. The following address bits can be assigned to the lower significant row address bits: R[12:0]x16 mode or R[13:0]x8 mode. Subsequently, the rank and row group address bits indicate the corresponding rank and row group positions in the memory device. The CXL command request has a size of 64 bytes, therefore the bits for the device physical address (e.g., DPA), such as DPA[5:0], are zero.

[0059]

[0060]

[0061] Table 1

[0062] In instances of x16 buses (e.g., low-power DRAM memory device buses), either the lower 32 bytes or the upper 32 bytes can be selected. For example, in x16 mode, 2 bytes are delivered per clock cycle. Entry 337-0 is 64 bytes in size and consists of 32 bytes at column address 333-0 and 32 bytes at column address 333-1. Column address 333-0 contains C[0] = 0 and column address 333-1 contains C[0] = 1, where C[0] = DPA[5]. The remaining nine DPA bits are assigned to the SectorEntry value. The SectorID value and the SectorEntry value determine the most significant row address bits (e.g., R[15:13] for x16 mode), the logical channel selector (e.g., Figure 4A The 15 channels will be selected from the [3:0] bits, and the column address bits (e.g., C[5:1]). Considering RAID and CRC overhead, the data placement efficiency is 87.5%, which means the device capacity is 7 / 8 of the DRAM address space. For example, 7 / 8 of the DRAM address space is used to contain 64 bytes of DPA data. For any given DPA[n-3:15] bits, the SectorEntry value selects one of 512 entries for the sector. These 512 entries are sequentially distributed along 15 logical channels (e.g., channels 451-0 to 451-14), while the last logical channel (not shown) is reserved for parity data. Although the example described herein involves a specific bus width, any bus width can be used with appropriate corresponding address bit assignments.

[0063] like Figure 4A As described, each row across each of channels 451 contains a total of 450 entries (indicated by offset 455 numbered from "0" to "440"). These 450 entries consist of 30 entries per channel and a total of 15 channels 451 (15 x 30 = 450), resulting in 450 entries for a given row, row group, and rank. A portion 414 of the memory array is divided into sectors, each containing 512 entries. Sector 0 spans from the beginning of row 453-0 at channel 451-0 to offset 457-1, which is 62 entries from the beginning of row 453-1 (the “2” to the left of offset 457-1 indicates the presence of two 64-byte data portions from the second channel 451-2 in the first row 453-1 of sector 0, and the “28” indicates the presence of twenty-eight 64-byte data portions from the second channel 451-2 in the first row 453-1, which marks the beginning of sector 1). For ease of reference, Table 2 indicates the initial entry value (e.g., the “EntryInit” value), which indicates the initial entry value used in row 453 of the sector.

[0064] SectorID EntryInit 0 0 1 62 2 124 3 186 4 248 5 310 6 372 7 434

[0065] Table 2

[0066] Sector 1 spans from offset 457-1 to offset 457-2, again spanning 512 entries. Sector 2 spans from offset 457-2 to offset 457-3. Sector 3 spans from offset 457-3 to offset 457-4. Sector 4 spans from offset 457-4 to offset 5, sector 5 spans from offset 457-5 to offset 457-6, and sector 6 spans from offset 457-6 to offset 457-7. The "16" bytes to the right of offset 457-7 are extra bytes reserved for other purposes.

[0067] To determine the location of an entry, a formula can be used to eliminate the need for additional address bits. First, the index determination can be performed using the following:

[0068] SectorID = DPA[36:34]

[0069] EntryID = DPA[14:6]

[0070] Index = FirstEntry + EntryID

[0071] If Index > 449 then

[0072] Index = Index - 449

[0073] R[15:13] = Sector ID + 1

[0074] else

[0075] R[15:13] = Sector ID

[0076] end if

[0077] CID = Index / 30

[0078] C[5:1]=Index-ChOffset=Index=30*ChID

[0079] Figure 4B-4C This is an instance determined by using a specific value for the position of each entry in section 414 of the array.

[0080] Figure 4B -C are each an instance location of a portion of data stored in a sector according to several embodiments of this disclosure. Figure 4BThe first instance shown contains a SectorID value of 2 (e.g., SectorID = DPA[36:34] = 2). The EntryID of this first instance is 150 (e.g., EntryID = DPA[14:6] = 150), indicated by arrow 463. Therefore, Figure 4B The index 461 is 274 (e.g., FirstEntry (sector 2) + EntryID = 124 + 150 = 274). Since index 461 is less than "449", the row position value is used (e.g., R[15:13]) (and no increment of 1 is performed), and since R[15:13] indicates row 2 (sector 2), row 2 453-2 is used. The channel ID (ChID) is 9 (Index / 30 = 274 / 30 = 9). The column address used within the channel (e.g., ChID = 9) is 4 (e.g., C[5:1] = Index - ChOffset = Index - 30 * ChID = 274 - 270 = 4). Therefore, the entry is located in row 2 453-2 (sector 2) and channel 9 451-9, and is 4 entries from the beginning of the channel data.

[0081] The following describes the determination in formula format:

[0082] SectorID = DPA[36:34] = 2

[0083] EntryID = DPA[14:6] = 150

[0084] Index=FirstEntry+EntryID=124+150=274

[0085] If Index > 449 then

[0086] Index = Index - 449

[0087] R[15:13] = Sector ID + 1

[0088] else

[0089] R[15:13] = Sector ID = 2

[0090] end if

[0091] CID = Index / 30 = 274 / 30 = 9

[0092] C[5:1]=Index-ChOffset=Index=30*ChID=274-270=4

[0093] Figure 4CThe second instance shown contains a SectorID value of 2 (e.g., SectorID = DPA[36:34] = 2). The EntryID of this second instance is 365 (e.g., EntryID = DPA[14:6] = 365), indicated by arrow 467. Therefore, Figure 4C The index 469 is 40 (e.g., the initial index is = FirstEntry(sector 2) + EntryID = 124 + 365 = 489). Since index 469 is greater than "449", index 469 is "489 - 449 = 40" and the row is incremented by 1 (e.g., row 2 453-2 becomes row 3 453-3 because it is incremented by 1). The channel ID (ChID) is 1 (Index / 30 = 40 / 30 = 1). The column address used within the channel (e.g., ChID = 1) is 10 (e.g., C[5:1] = Index - ChOffset = Index - 30 * ChID = 40 - 30 = 10). Therefore, the entry is located in row 3 453-3 (sector 2) and channel 1 451-1, and is 10 entries from the beginning of the channel data.

[0094] The following describes the determination in formula format:

[0095] SectorID = DPA[36:34] = 2

[0096] EntryID = DPA[14:6] = 365

[0097] Index=FirstEntry+EntryID=124+365=489

[0098] If Index > 449 then

[0099] Index=Index-449=489-449=40

[0100] R[15:13]=Sector ID+1=2+1=3

[0101] else

[0102] R[15:13] = Sector ID

[0103] end if

[0104] CID = Index / 30 = 40 / 30 = 1

[0105] C[5:1]=Index-ChOffset=Index=30*ChID=40-30=10

[0106] Figure 5 The diagram illustrates an example method 571 for addressing data and additional data portions (e.g., cyclic redundancy check (CRC) data, error correction code (ECC) data, etc.) according to several embodiments of the present disclosure. In some embodiments, a computer system (e.g., computer system 100) may include a memory controller (e.g., Figure 1 The memory controller 115) and the processing device (e.g., Figure 1 (Processing device 117). The memory controller can cause the processing device to determine the address for an entry within the memory array. In some instances, the host can send commands compliant with CXL to the memory device for access.

[0107] In method 571, as described in 572, a memory controller can access data written to a memory device in response to receiving a first command configured according to a nondeterministic memory interface protocol, such as a Compute High-Speed ​​Link (CXL) protocol compliance command. The memory device comprises a plurality of sets of memory cells corresponding to corresponding portions of a memory cell array of the memory device. The sets of memory cells may correspond to rows of memory cells or pages of memory cells in a memory system. The memory controller can receive commands to execute read requests and / or write requests for the sets of memory cells. The memory controller can activate a row of memory cells to access one or more memory devices. For example, the memory controller can apply a sensed voltage to a row of memory cells to activate it. In some instances, method 571 may include translating the address associated with the first command by determining a sector in the memory device that includes a page containing the data.

[0108] In some instances, the memory device may be a Computational High-Speed ​​Link (CXL) compliant memory device. In some instances, method 571 may include accessing 64 bytes of data and corresponding additional data portions (e.g., CRC data, ECC data, etc.). In some instances, the CRC data associated with the data is 24 bits (3 bytes). In some instances, the metadata associated with the CRC data is in the range of 4 to 8 bits. In some instances, the metadata includes a host poison bit and a memory device poison bit.

[0109] In 574, method 571 describes a memory controller that can translate an address associated with a first command into a second command configured according to a standardized deterministic memory interface protocol. For example, the second command could be a dynamic random access memory (DRAM) access command.

[0110] In 576, method 571 describes a memory controller that can access a memory cell page of a memory device in which data is written, wherein additional data portions associated with said data (e.g., cyclic redundancy check (CRC) data, ECC data, etc.) are written using translated addresses associated with CXL protocol compliance commands. In some instances, the page comprises multiple data portions, each of which is 64 bytes in size. In some instances, the multiple data portions are stored contiguously in the page, and multiple additional data portions (e.g., multiple CRC data portions, multiple ECC data portions, etc.) associated with each of said multiple data portions are also stored contiguously in the page.

[0111] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments. This disclosure is intended to cover modifications or variations of one or more embodiments of this disclosure. It should be understood that the above description has been carried out illustratively and not restrictively. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of one or more embodiments of this disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of this disclosure should be determined with reference to the appended claims together with the full scope of the equivalents given by such claims.

[0112] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than expressly stated in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is, in itself, a separate embodiment.

Claims

1. A method comprising: In response to receiving a first command configured according to a nondeterministic memory interface protocol, data written to a memory device is accessed, the first command being a calculation high-speed link (CXL) protocol compliance command; Translating the address associated with the first command to a second command configured according to a standardized deterministic memory interface protocol, wherein the second command is a DRAM-accessible command and wherein translating the address associated with the first command includes: Determine sectors in the memory device, the sectors comprising memory cell pages containing the data; Assign the most significant address bit from a plurality of address bits to a sector value, wherein the sector value identifies the sector; and The remaining address bits from the plurality of address bits are allocated to at least one of the row address bits, rank bits, group address bits, channel selection bits, and column address bits, wherein the allocation method of the plurality of address bits corresponds to the physical capacity of the memory device; and Access the memory cell page of the memory device in which the data is written, wherein an additional data portion associated with the data is written using a second command that includes a translated address associated with the first command.

2. The method according to claim 1, wherein: The data being accessed is 64 bytes in size; and The additional data portion is either the Cyclic Redundancy Check (CRC) data portion or the Error Correction Code (ECC) portion.

3. The method according to claim 2, wherein: The additional data portion associated with the data is the CRC data portion and is in the range of 24 to 28 bits in size; and The metadata associated with the CRC data portion is in the range of 4 to 8 bits.

4. The method of claim 3, wherein the metadata includes host poison bits and memory device poison bits.

5. The method according to claim 1, wherein: The page comprises multiple data sections, each of which is 64 bytes in size.

6. The method according to claim 5, wherein: The plurality of data portions are stored contiguously in the page, and a plurality of additional data portions associated with each of the plurality of data portions are stored contiguously in the page.

7. An apparatus comprising: A memory controller configured to receive commands associated with a plurality of memory cells in a memory device; as well as Processing device, coupled to the plurality of memory cells, the processing device: Receive signaling instructing access to data in a memory cell page of the memory device according to the Computational High-Speed ​​Link (CXL) protocol; The address associated with the signaling is translated into a DRAM-accessible address, wherein the translation includes determining the sector where the memory cell page is located, and the translation of the address associated with the signaling includes the processing means: Determine a sector in the memory device, the sector comprising the page containing the data; Assign the most significant address bit from a plurality of address bits to a sector value, wherein the sector value identifies the sector; and The remaining address bits from the plurality of address bits are allocated to at least one of the row address bits, rank bits, group address bits, channel selection bits, and column address bits, wherein the allocation method of the plurality of address bits corresponds to the physical capacity of the memory device; and Access the page in the sector of the memory device associated with the data, wherein the data and the cyclic redundancy check (CRC) data associated with the data are in the page.

8. The device of claim 7, wherein the data portion is 64 bytes in size.

9. The device of claim 7, wherein the page associated with the data portion is 2048 bytes in size.

10. The device according to claim 7, wherein: The sector in the memory device comprises 512 entries, and each entry is 64 bytes of data.

11. The device of claim 10, wherein each of the 512 entries comprises at least 3 bytes of CRC data.

12. The device of claim 7, wherein the memory device is a computation high-speed link (CXL) compliant memory device.

13. The device of claim 7, further comprising a ferroelectric field-effect transistor (FeFET) memory device, a dynamic random access memory (DRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (ReRAM) device, or any combination thereof.

14. A system comprising: The host sends commands configured according to a nondeterministic memory interface protocol, wherein the commands are calculation high-speed link (CXL) protocol compliance commands; A memory device coupled to the host, the memory device comprising: A memory array comprising multiple memory cells; and A memory controller, coupled to the memory array, wherein the memory controller: Receive the command, wherein the command is associated with a 64-byte data portion; Determine the location of the data portion within a memory page and within a sector of the memory array, wherein: A sector comprises multiple data entries, each of which includes data and corresponding cyclic redundancy check (CRC) data; The most significant address bit among a plurality of address bits is assigned to a sector value, wherein the sector value identifies the sector; and The remaining address bits among the plurality of address bits are allocated to at least one of row address bits, rank bits, group address bits, channel selection bits, and column address bits, wherein the allocation method of the plurality of address bits corresponds to the physical capacity of the memory device; and The location within the memory page is based on sector offset; and Access the memory page associated with the data portion in the sector of the memory device.

15. The system according to claim 14, wherein: The sector spans at least two rows of memory cells within the memory array.

16. The system of claim 15, wherein the additional sector begins at an offset from the beginning of the memory cell row to which the sector terminates.

17. The system of claim 14, wherein the memory controller receives address bits associated with the data portion, wherein the most significant address bit of the address bits is allocated to the sector value, and at least a portion of the remaining address bits indicates at least one of a specific channel and a specific offset associated with the location of the data portion.

18. The system of claim 14, wherein the memory controller determines which of a plurality of channels will locate the data portion, wherein the memory device comprises fifteen (15) channels and each page of the memory in the memory array spans one of the fifteen (15) channels.

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