A single-bit all-digital in-memory computing circuit based on approximate 4-2 compressor

Abstract

The application is a single-bit all-digital in-memory computing unit based on an approximate 4-2 compressor. The structure supports the multiplication and accumulation of binary input stimuli and weights in a neural network. In the binary network, there are two values: "+1" and "-1". In the circuit, voltage VDD represents "+1", and voltage VSS represents "-1". VDD is the power supply voltage, and VSS is the zero voltage of the ground. For the final multiplication and accumulation result, the number of "+1" can be added, that is, the high and low levels of the digital circuit are added to obtain the multiplication and accumulation result. Four SRAM units in each column share an approximate 4-2 compressor as a unit to obtain the final 2-bit approximate multiplication and accumulation result.

Description

Technical Field

[0001] This invention belongs to the technical field, specifically relating to a single-bit all-digital in-memory computing circuit based on an approximate 4-2 compressor. Background Technology

[0002] In today's era of rapid development in artificial intelligence, the traditional von Neumann architecture suffers from the "memory wall" and "power wall" problems for data-intensive neural networks. In-memory computing architecture, by combining storage units and computing circuits, fundamentally solves the von Neumann bottleneck.

[0003] However, mainstream analog dense circuits have relatively weak anti-interference capabilities, while digital all-digital in-memory computing architectures demonstrate superior robustness. However, the addition of extra multiplication and addition tree circuits in digital in-memory computing structures leads to increased power consumption and area loss, making them difficult to apply. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a single-bit all-digital in-memory computing circuit based on an approximate 4-2 compressor, which has higher stability and accuracy and is less susceptible to external interference.

[0005] To achieve the above objectives, the present invention is implemented using the following technical solution: In a first aspect, the present invention provides a single-bit all-digital in-memory computing circuit based on an approximate 4-2 compressor, comprising at least one approximate 4-2 compressor and a set of memory cells connected to the approximate 4-2 compressor; A set of storage units consists of four storage cells; Each of the aforementioned storage cells stores 1 bit of weight information and is connected to the approximate 4-2 compressor via an XNOR gate; The approximate 4-2 compressor includes a first-stage circuit and a second-stage circuit; The first stage circuit includes two inverters and one NAND gate, and the second stage circuit includes two NAND gates; the two inverters and one NAND gate of the first stage circuit are respectively connected to the two NAND gates of the second stage circuit. Of the four memory cells, two memory cells are connected to the two inverters of the first-stage circuit through an XOR gate, and two memory cells are connected to the same NAND gate of the first-stage circuit through an XOR gate. The two inverters in the first stage circuit are used to invert the multiplication and accumulation result of the two memory cells and output it to the NAND gate in the second stage circuit; The NAND gate of the first-stage circuit is used to output the bitwise multiplication result of the other two memory cells to the NAND gate of the second-stage circuit; The NAND gate in the second-stage circuit is used to output an approximate result.

[0006] Furthermore, the storage unit includes a data latch structure and two conducting N-transistors; Furthermore, the data latch structure includes two inverters connected end-to-end; Furthermore, the gates of the two N-transistors in the memory cell are controlled by the same word line WL, and the source and drain of the two N-transistors are connected to bit lines BL, BLB and an inverter; Furthermore, storage cells in the same column are connected using the same bit line.

[0007] Furthermore, the Q terminal of each storage cell is connected to the input terminal of the XOR gate in its bitwise multiplication structure. The other end of the XOR gate input is connected to the input excitation IN, and the output is entered into the approximate 4-2 compressor as the bitwise multiplication result.

[0008] Furthermore, there are multiple approximate 4-2 compressors, each of which is connected to a set of storage units.

[0009] Secondly, the present invention provides a single-bit all-digital in-memory computation method based on an approximate 4-2 compressor, which, based on the single-bit all-digital in-memory computation circuit described in the first aspect, includes: The bitwise multiplication result of the four storage units in a group is input into an approximate 4-2 compressor for multiplication and accumulation. The multiplication and accumulation result of the single bit is multiplied and accumulated, and the four 1-bit data are multiplied and accumulated to obtain the multiplication and accumulation result.

[0010] Furthermore, the storage unit includes a data latch structure and two conducting N-transistors; The method further includes: In storage mode, the in-memory computing circuit performs normal SRAM write operations. When the word line signal is high, two N-type transistors are turned on to write the preloaded weight data on the bit line into the storage cell. The written weight data is stored in SRAM in 1-bit form.

[0011] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: 1. Compared with analog intensive in-memory computing circuits that complete multiplication and accumulation by charging and discharging, the digital domain gate circuits of this application have higher stability and accuracy and are less susceptible to external interference; 2. Compared to the high power consumption of adder arrays in traditional digital in-memory computing structures, this structure introduces a novel approximate 4-2 compressor. The traditional approach uses full adders and half adders for addition, which results in significant power waste. Here, an approximate 4-2 compressor is used for addition, reducing power consumption while maintaining acceptable error. This reduces the power consumption of the adder array section, thereby reducing the overall power waste of the digital in-memory computing structure. 3. This structure supports the multiplication and accumulation of binary input excitations and weights in neural networks. The binary network contains two values, "+1" and "-1". In the circuit, voltage VDD represents "+1" and voltage VSS represents "-1", where VDD is the power supply voltage and VSS is the zero voltage (ground). The final multiplication and accumulation result can be seen as adding the number of "+1" values, i.e., adding them according to the high and low levels of the digital circuit. The four SRAM cells in each column share an approximate 4-2 compressor, resulting in a final 2-bit approximate multiplication and accumulation result. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the overall structure of the in-memory computing circuit of the present invention; Figure 2 This is a schematic diagram of the storage cell structure of the present invention; Figure 3 This is a schematic diagram of the approximate 4-2 compressor structure of the present invention; In the diagram: 1. Inverter; 2. N-transistor; 3. XOR gate; 4. NAND gate; 10. Storage unit; 20. Compressor. Detailed Implementation

[0013] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0014] In the description of this embodiment, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this embodiment and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this embodiment. Example

[0015] This embodiment provides a single-bit all-digital in-memory computing circuit based on an approximate 4-2 compressor, including a compressor and at least one set of memory cells. Figure 1This refers to the overall structure of the in-memory computing circuit.

[0016] Components: Each memory cell 10 consists of two cross-coupled inverters 1 and two conducting N-type transistors 2, totaling 6 transistors. Each memory cell 10 stores 1 bit of weight information and uses an XNOR gate 3 to perform bitwise multiplication. The storage cell 10 in this application is a 6-transistor SRAM cell with an additional XNOR gate 3; An approximate 4-2 compressor 20 (including the five logic gates on the far right, i.e. the right side of the BLB) is composed of three NAND gates 4 and two inverters 1. The compressor 20 has two stages of circuitry, with the first stage consisting of two inverters and one NAND gate 4, and the second stage consisting of two NAND gates 4. WL<3:0> is the word line signal, BL and BLB are the bit line signals, Q<3:0> and QB<3:0> are the internal storage nodes of SRAM storage cell 10, IN<3:0> is the input stimulus, and OUT<1:0> is the 2-bit multiply-accumulate output result, which is an approximate result; Figure 1 The circuit diagram for the built-in computing circuit is shown, where the left side ( Figure 2 This is the overall in-memory computing circuit structure diagram, on the right ( Figure 3 ( ) is the gate-level circuit diagram of an approximate 4-2 compressor 20.

[0017] Connection relationships: Two inverters 1 are connected end to end to form a data latch structure. The gates of the two N transistors 2 in each SRAM 6T structure (the memory cell 10 structure in this application is an improvement on the conventional SRAM 6T structure, including 4 SRAM cells) are controlled by the same word line WL. The source and drain are connected to the bit lines BL, BLB and inverter 1. The memory cells 10 in the same column are connected using the same bit line. The Q terminal of each storage cell 10 is connected to the input terminal of the XNOR gate 3 in its bitwise multiplication structure (the bitwise multiplication structure is the XNOR gate 3, which is used in this application to implement single-bit bitwise multiplication). The other end of the XNOR gate 3 input is connected to the input excitation IN, and the output is entered into the approximate 4-2 compressor 20 as the bitwise multiplication result. The two inverters 1 in the approximate 4-2 compressor 20 invert the multiplication and accumulation result of the two inputs and output it to the second-stage NAND gate 4 (there are two NAND gates 4 in the second stage on the right side of BLB). The other two bit-by-bit multiplication results are connected to the two inputs of a NAND gate 4 and output to the next stage NAND gate 4. Finally, the output of the second-stage NAND gate 4 is used as the multiplication and accumulation result. Operation process: The circuit has two operating modes: storage mode and computation mode. In storage mode, the in-memory computation circuit performs normal SRAM write operations. When the word line signal is high, two N-type transistors are turned on, and the preloaded weight data on the bit line is written into storage cell 10. The written weight data is stored in SRAM in 1-bit form.

[0018] Once the storage mode is complete, the computation mode begins. In computation mode, the multiply-accumulate result of a single bit is multiplied and accumulated; here, four 1-bit data points are multiplied and accumulated. The traditional approach is to use full adders and half adders, but this results in significant power consumption waste. Here, an approximate 4-2 compressor is used for addition, reducing power consumption while maintaining acceptable error.

[0019] The truth table for the approximate 4-2 compressor 20 is shown below:

[0020] The Boolean logic for the approximate 4-2 compressor 20 is as follows: As can be seen from the truth table, the approximate 4-2 compressor 20 has a relatively accurate result when there are many "1"s in the input. Therefore, the in-memory calculation circuit will have high accuracy in neural networks with a high density of "1"s.

[0021] Compared to existing in-memory computing circuits, this structure has two advantages: The first advantage is that, compared with analog intensive in-memory computing circuits that complete multiplication and accumulation by charging and discharging, digital domain gate circuits have higher stability and accuracy and are less susceptible to external interference. The second advantage is that, compared to the high power consumption of adder arrays in traditional digital in-memory computing structures, the approximate computing structure in this design can significantly reduce the power consumption and area of ​​the adder array, making it highly valuable. This structure reduces the power consumption of the adder array section by introducing a novel approximate 4-2 compressor, thereby reducing the overall power waste in the digital in-memory computing structure.

[0022] The ABCD characters here correspond to the output of an XOR gate for four memory locations in a group. The horizontal line above the character represents "NOT", and "OUT" is the output. <0> OUT represents the lower bit of the approximate output result. <1> This represents the higher digit of the approximate output result.

[0023] This structure supports the multiplication and accumulation of binary input excitations and weights in neural networks. The binary network contains two values, "+1" and "-1". In the circuit, voltage VDD represents "+1" and voltage VSS represents "-1", where VDD is the power supply voltage and VSS is the zero voltage (ground). The final multiplication and accumulation result can be seen as adding the number of "+1" values, i.e., adding them according to the high and low levels of the digital circuit. The four SRAM cells in each column share an approximate 4-2 compressor 20, resulting in a final 2-bit approximate multiplication and accumulation result.

[0024] Example 2: This embodiment provides a single-bit all-digital in-memory computation method based on an approximate 4-2 compressor, based on the computation circuit described in Embodiment 1, including: The circuit has two operating modes: storage mode and computation mode. In storage mode, the in-memory computation circuit performs normal SRAM write operations. When the word line signal is high, two N-type transistors 2 are turned on, and the preloaded weight data on the bit line is written into the storage cell 10. The written weight data is stored in the SRAM in the form of 1 bit.

[0025] Once the storage mode is complete, the computation mode begins. In computation mode, the multiply-accumulate result of a single bit is multiplied and accumulated; here, four 1-bit data points are multiplied and accumulated. The traditional approach is to use full adders and half adders, but this results in significant power consumption waste. Here, an approximate 4-2 compressor is used for addition, reducing power consumption while maintaining acceptable error.

[0026] The binarized network contains two values, "+1" and "-1". In the circuit, voltage VDD represents "+1" and voltage VSS represents "-1", where VDD is the power supply voltage and VSS is the zero voltage grounded. The final multiply-accumulate result can be seen as adding the number of "+1" values, i.e., adding them according to the high and low levels of the digital circuit. The four SRAM storage cells 10 in each column share an approximate 4-2 compressor 20 as a unit, resulting in a final 2-bit approximate multiply-accumulate result.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0028] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0029] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0030] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0031] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A single-bit all-digital in-memory computing circuit based on an approximate 4-2 compressor, characterized in that, It includes at least one approximate 4-2 compressor and a set of storage units connected to the approximate 4-2 compressor; A set of storage units consists of four storage cells, and a set of storage units shares an approximate 4-2 compressor; Each of the aforementioned storage cells stores 1 bit of weight information and is connected to the approximate 4-2 compressor via an XNOR gate; The approximate 4-2 compressor includes a first-stage circuit and a second-stage circuit; The first stage circuit includes two inverters and one NAND gate, and the second stage circuit includes two NAND gates; the two inverters and one NAND gate of the first stage circuit are respectively connected to the two NAND gates of the second stage circuit. Of the four memory cells, two memory cells are connected to the two inverters of the first-stage circuit through an XOR gate, and two memory cells are connected to the same NAND gate of the first-stage circuit through an XOR gate. The two inverters in the first stage circuit are used to invert the bitwise multiplication result of the two memory cells and output it to the NAND gate in the second stage circuit; The NAND gate of the first-stage circuit is used to output the bitwise multiplication result of the other two memory cells to the NAND gate of the second-stage circuit; The NAND gate in the second-stage circuit is used to output an approximate result.

2. The single-bit all-digital in-memory computing circuit according to claim 1, characterized in that, The storage unit includes a data latch structure and two conducting N-transistors.

3. The single-bit all-digital in-memory computing circuit according to claim 2, characterized in that, The data latch structure includes two inverters connected end-to-end.

4. The single-bit all-digital in-memory computing circuit according to claim 3, characterized in that, The gates of the two N-transistors in the memory cell are controlled by the same word line WL, and the source and drain of the two N-transistors are connected to bit lines BL, BLB and an inverter.

5. The single-bit all-digital in-memory computing circuit according to claim 4, characterized in that, Storage cells in the same column are connected using the same bit line.

6. The single-bit all-digital in-memory computing circuit according to claim 1, characterized in that, The Q terminal of each memory cell is connected to the input of its XNOR gate. The other end of the XNOR gate's input is connected to the input excitation IN. The output of the XNOR gate is fed into the approximate 4-2 compressor as the result of bitwise multiplication.

7. The single-bit all-digital in-memory computing circuit according to claim 1, characterized in that, There are multiple approximate 4-2 compressors, and each approximate 4-2 compressor is connected to a set of storage units.

8. A single-bit all-digital memory computation method based on an approximate 4-2 compressor, characterized in that, The single-bit all-digital in-memory computing circuit according to any one of claims 1-7 includes: The bitwise multiplication results of the four storage units in a set are input into an approximate 4-2 compressor for multiplication and accumulation to obtain the multiply-accumulated result.

9. The single-bit all-digital memory computation method based on an approximate 4-2 compressor according to claim 8, characterized in that, The storage unit includes a data latch structure and two conducting N-transistors; The method further includes: In storage mode, the in-memory computing circuit performs normal SRAM write operations. When the word line signal is high, two N-type transistors are turned on to write the preloaded weight data on the bit line into the storage cell. The written weight data is stored in SRAM in 1-bit form.

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