Octagonal double-ring high-throughput TRNG circuit based on FPGA and working method thereof

Abstract

The application discloses an octagonal double-ring high-throughput TRNG circuit based on FPGAs and a working method thereof, and the circuit comprises an entropy source circuit, a sampling circuit and a post-processing circuit; wherein the entropy source circuit is composed of four substructures, and any i-th substructure comprises an outer ring and an inner ring; the sampling circuit is composed of four D flip-flops; and the post-processing circuit is composed of three XOR gates and is divided into two stages.The application can greatly reduce hardware resource consumption, realize high throughput, guarantee the robustness of the structure, and thus can be applied to authentication protocols and key generation and other application fields.

Description

Technical Field

[0001] This invention belongs to the field of hardware security, specifically an octagonal dual-ring high-throughput TRNG circuit based on FPGAs and its operation mode. Background Technology

[0002] With the rise of technologies such as cloud computing and the Internet of Things, information security has become an increasingly important issue. Most everyday services, such as data storage and banking management, rely on authentication protocols, key and token generation. However, in today's rapidly evolving technological landscape, traditional key generation techniques are proving inadequate. To effectively address this problem and provide reliable keys for the hardware security field, TRNGs have emerged. TRNGs are an emerging hardware security primitive and an important component of the security field. They are used in many key generation mechanisms, authentication protocols, cryptographic algorithms, simulation software problems (such as Monte Carlo simulations), and random masking in side-channel attack defense systems. TRNGs generate uncertain, non-periodic, and non-repeating sequences by extracting noise from natural physical phenomena. Common entropy sources used to generate random numbers include thermal noise sources, radioactive decay, metastability, and jitter.

[0003] Various TRNG circuits based on thermal noise require significant power to amplify the noise. Metastable TRNGs utilize the metastability of latch circuits to generate random numbers, but they also consume very large areas and power. Jitter, a common entropy source in TRNGs, is primarily extracted from ring oscillator chains using XOR gates. These oscillator-based TRNG circuits are relatively easy to design, but the quality of the random numbers generated by them needs improvement. Furthermore, the power consumption of the circuits is high when using a large number of oscillator chains to generate random numbers in parallel.

[0004] Most existing TRNG circuit designs are based on only one entropy source, either trading high throughput for higher resource consumption or lower resource consumption for lower throughput. They cannot simultaneously meet the requirements of low resource consumption and high throughput. However, in the era of "Internet Plus," as more applications migrate to resource-constrained IoT environments, the demand for lighter, faster, and lower-power TRNGs is also increasing. In practical production applications, TRNG research is pursuing lower resource consumption, higher throughput, and better stability. Summary of the Invention

[0005] The present invention addresses the shortcomings of the prior art by proposing an octagonal double-ring high-throughput TRNG circuit and its operating method based on FPGAs. This aims to significantly reduce hardware resource overhead while achieving high throughput and ensuring structural robustness, thus enabling its application in fields such as authentication protocols and key generation.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0007] The present invention provides an octagonal dual-ring high-throughput TRNG circuit based on FPGAs, characterized in that it includes: an entropy source circuit, a sampling circuit, and a post-processing circuit.

[0008] The entropy source circuit consists of four identical substructures;

[0009] Any i-th substructure consists of an inner ring and an outer ring. The inner ring of any i-th substructure consists of three single-input inverters and one two-input XOR gate. The outer ring of any i-th substructure consists of two single-input inverters and one two-input NAND gate, i∈[1,4].

[0010] In the outer ring of the i-th substructure, the output terminal rout1_i of the first single-input inverter is connected to the input terminal rout2_i of the second single-input inverter;

[0011] The output terminal rout2_i of the second single-input inverter is connected to the data input terminal NAND of the dual-input NAND gate;

[0012] The output terminal NOUT of the dual-input NAND gate is used as the input terminal of the first single-input inverter, and the enable input terminal EN of the dual-input NAND gate is connected to the external enable signal EN.

[0013] The output terminal rout2_i of the second single-input inverter is used as the output terminal of the outer loop of the i-th substructure and connected to the inner loop of the i-th substructure;

[0014] In the inner ring of the i-th substructure, the output terminal ROUT1_i of the first single-input inverter is connected to the input terminal ROIN2_i of the second single-input inverter;

[0015] The output terminal ROUT2_i of the second single-input inverter is connected to the input terminal ROIN3_i of the third single-input inverter;

[0016] The output terminal ROUT3_i of the third single-input inverter is connected to the inner loop input terminal XOR_1_i of the dual-input XOR gate; the outer loop input terminal XOR_2_i of the dual-input XOR gate is connected to the output terminal rout2_i of the second single-input inverter in the outer loop.

[0017] The output of the dual-input XOR gate is connected to the input ROIN1_i of the first single-input inverter;

[0018] The output terminal ROUT2_i of the second single-input inverter in the inner loop of the i-th substructure is taken as the entropy source output terminal OUT_i of the i-th substructure;

[0019] Each substructure is connected by a single-input single-output buffer. Each single-input buffer contains an input terminal BIN and an output terminal BOUT. The input terminal BIN is connected to the output terminal ROUT1_i of the first single-input inverter in the inner loop of the i-th substructure, and the output terminal BOUT is connected to the inner loop input terminal XOR_1_i+1 of the dual-input XOR gate in the (i+1)-th substructure, to form an octagonal ring.

[0020] The sampling circuit consists of four D flip-flops. Any i-th D flip-flop includes: a data input terminal D_i, a clock input terminal CLK_i, and a data output terminal Q_i.

[0021] Among them, the data input terminal D_i of the i-th D flip-flop is connected to the entropy source output terminal OUT_i of the i-th substructure; the clock input terminal CLK_i of the i-th D flip-flop receives the output signal of the external IP core; the data output terminal Q_i of the i-th D flip-flop is connected to the input terminal of the first-stage XOR gate in the post-processing circuit.

[0022] The post-processing circuit consists of three two-input XOR gates and is divided into two stages. The first stage consists of two two-input XOR gates, and the second stage consists of one two-input XOR gate.

[0023] The input terminals of the first two-input XOR gate in the first stage are connected to the data output terminals Q_1 and Q_2 of the first D flip-flop in the sampling circuit, respectively; the input terminals of the second two-input XOR gate in the first stage are connected to the data output terminals Q_3 and Q_4 of the third D flip-flop in the sampling circuit, respectively.

[0024] The input terminals of the two-input XOR gates in the second stage are respectively connected to the output terminals XOR_OUT_1 and XOR_OUT_2 of the first two-input XOR gates in the first stage. The output terminal of the two-input XOR gates in the second stage serves as the output terminal TRNG_OUT of the TRNG circuit.

[0025] The operating method of the octagonal dual-ring high-throughput TRNG circuit based on FPGAs described in this invention is characterized by the following steps:

[0026] Step 1: Initialize all enable terminals EN in the entropy source circuit to 0, and set the clock input CLK_i of the i-th D flip-flop in the sampling circuit to f;

[0027] Step 2: Set all enable terminals EN=1 in the entropy source circuit to make the entropy source circuit start oscillating;

[0028] Step 3: Use a sampling circuit to collect the output sequence {OUT_i, i = 1, 2, 3, 4} of the four substructures in the entropy source circuit;

[0029] Step 4: Input {OUT_i, i = 1, 2, 3, 4} into the post-processing circuit, and let it go through two stages of post-processing to output the random sequence TRNG_OUT of the TRNG circuit.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0031] 1. This invention proposes an octagonal double-ring high-throughput TRNG circuit and its operating method based on FPGAs through hardware-level design of the TRNG circuit structure, overcoming the problem that existing TRNG circuits cannot simultaneously meet the requirements of high throughput and low resource consumption. It employs a hybrid entropy source method, utilizing both jitter and metastability as the source of randomness through circuit structure design. This hybrid entropy source significantly reduces hardware resource overhead, achieving a high throughput of 320 Mbps on Artix-7 and 300 Mbps on Kintex-7, while ensuring structural robustness. It can be used in demanding information security fields such as encryption and decryption. Experimental results show that this invention outperforms most existing TRNGs in terms of the ratio of throughput to FPGA resource utilization, and the generated random sequences passed NISTSP 800-22 and NIST SP 800-90B tests.

[0032] 2. The activation of this invention is controlled by the enable terminal EN of the outer loop dual-input NAND gate. When EN = 0, the dual-input NAND gate acts as a buffer, and the entropy source circuit does not oscillate. When EN = 1, the dual-input NAND gate acts as an inverter, and the entropy source circuit begins to oscillate, generating a random output sequence. This overcomes the problem that some existing TRNG circuits are always in an oscillating state once powered on and cannot be manually controlled. By controlling whether the circuit is activated by the enable terminal EN of the outer loop dual-input NAND gate, power consumption can be greatly reduced, making this invention suitable for portable devices with standby time requirements.

[0033] 3. In this invention, the i-th substructure of the entropy source circuit adopts a double-ring structure with an outer ring and an inner ring. The jitter accumulated in the outer ring is extracted by the two-input XOR gate of the inner ring. The extracted jitter is transmitted to the inner ring through the two-input XOR gate of the inner ring, becoming the original jitter of the inner ring. Based on this original jitter, the inner ring accumulates jitter again through its own three single-input inverters, and finally outputs OUT_i. Experimental results show that, with the same number of inverters, the jitter obtained by adopting the above double-ring structure is better than that of the traditional single-ring structure. Therefore, the double-ring structure can reduce resource consumption.

[0034] 4. The TRNG structure proposed in this invention uses common structures already available in various FPGAs, such as one-input one-output LUT_1 and two-input one-output LUT_2, which has strong portability and can be implemented on most FPGAs. Attached Figure Description

[0035] Figure 1 This is a structural diagram of the octagonal double-ring high-throughput TRNG of the present invention;

[0036] Figure 2 This is a circuit diagram of the i-th substructure of the entropy source in this invention;

[0037] Figure 3 This is a schematic diagram of the entropy source circuit structure of the octagonal double-ring high-throughput TRNG of the present invention;

[0038] Figure 4 This is a structural diagram of the sampling circuit of the present invention;

[0039] Figure 5 This is a structural diagram of the post-processing circuit of the present invention. Detailed Implementation

[0040] In this embodiment, an octagonal dual-ring high-throughput TRNG circuit based on Field Programmable Gate Arrays (FPGAs) is described, such as... Figure 1 As shown, it consists of an entropy source circuit, a sampling circuit, and a post-processing circuit;

[0041] The entropy source circuit consists of four identical substructures;

[0042] like Figure 2 As shown, any i-th substructure consists of an inner loop and an outer loop. The inner loop of any i-th substructure consists of three single-input inverters and one two-input XOR gate, and the outer loop of any i-th substructure consists of two single-input inverters and one two-input NAND gate, i∈[1,4].

[0043] In the outer ring of the i-th substructure, the output terminal rout1_i of the first single-input inverter is connected to the input terminal rout2_i of the second single-input inverter;

[0044] The output terminal rout2_i of the second single-input inverter is connected to the data input terminal NAND of the dual-input NAND gate;

[0045] The output terminal NOUT of the dual-input NAND gate is used as the input terminal of the first single-input inverter, and the enable input terminal EN of the dual-input NAND gate is connected to the external enable signal EN.

[0046] The output terminal rout2_i of the second single-input inverter is used as the output terminal of the outer loop of the i-th substructure and connected to the inner loop of the i-th substructure;

[0047] In the inner ring of the i-th substructure, the output terminal ROUT1_i of the first single-input inverter is connected to the input terminal ROIN2_i of the second single-input inverter;

[0048] The output terminal ROUT2_i of the second single-input inverter is connected to the input terminal ROIN3_i of the third single-input inverter;

[0049] The output terminal ROUT3_i of the third single-input inverter is connected to the inner loop input terminal XOR_1_i of the dual-input XOR gate; the outer loop input terminal XOR_2_i of the dual-input XOR gate is connected to the output terminal rout2_i of the second single-input inverter in the outer loop.

[0050] The output of the dual-input XOR gate is connected to the input ROIN1_i of the first single-input inverter;

[0051] The output terminal ROUT2_i of the second single-input inverter in the inner loop of the i-th substructure is taken as the entropy source output terminal OUT_i of the i-th substructure.

[0052] like Figure 3 As shown, each substructure is connected by a single-input single-output buffer. Each single-input buffer contains an input terminal BIN and an output terminal BOUT. The input terminal BIN is connected to the output terminal ROUT1_i of the first single-input inverter in the inner loop of the i-th substructure, and the output terminal BOUT is connected to the inner loop input terminal XOR_1_i+1 of the two-input XOR gate in the (i+1)-th substructure, thus forming an octagonal ring.

[0053] like Figure 4 As shown, the sampling circuit consists of four D flip-flops. Any i-th D flip-flop includes: a data input terminal D_i, a clock input terminal CLK_i, and a data output terminal Q_i.

[0054] Among them, the data input terminal D_i of the i-th D flip-flop is connected to the entropy source output terminal OUT_i of the i-th substructure; the clock input terminal CLK_i of the i-th D flip-flop receives the output signal of the external IP core; the data output terminal Q_i of the i-th D flip-flop is connected to the input terminal of the first-stage XOR gate in the post-processing circuit.

[0055] like Figure 5 As shown, the post-processing circuit consists of three two-input XOR gates and is divided into two stages. The first stage consists of two two-input XOR gates, and the second stage consists of one two-input XOR gate.

[0056] The inputs of the first two-input XOR gate in the first stage are connected to the data outputs Q_1 of the first D flip-flop and Q_2 of the second D flip-flop in the sampling circuit, respectively; the inputs of the second two-input XOR gate in the first stage are connected to the data outputs Q_3 of the third D flip-flop and Q_4 of the fourth D flip-flop in the sampling circuit, respectively.

[0057] The inputs of the two-input XOR gates in the second stage are connected to the outputs of the first two-input XOR gate (XOR_OUT_1) and the second two-input XOR gate (XOR_OUT_2) in the first stage, respectively. The output of the two-input XOR gates in the second stage serves as the output of the TRNG circuit (TRNG_OUT).

[0058] In this embodiment, the NAND gate is configured using the following steps:

[0059] Step 1: Set the initial value of the two-input, one-output LUT_2 to 4'b0111;

[0060] Step 2: Set the input terminal I0 of the two-input, one-output LUT_2 as the enable terminal EN;

[0061] Step 3: Connect the input terminal I1 of the two-input, one-output LUT_2 to the output terminal rout2_i of the second inverter in the outer loop;

[0062] Step 4: Connect the output terminal O of the two-input one-output lookup table LUT_2 to the input terminal roin1_i of the first inverter in the outer loop;

[0063] The XOR gate is configured using the following steps:

[0064] Step 1: Set the initial value of the two-input, one-output LUT_2 to 4'b0110;

[0065] Step 2: Connect the input terminal I0 of the two-input, one-output LUT_2 to the output terminal rout2_i of the second inverter in the outer loop;

[0066] Step 3: Connect the input terminal I1 of the two-input one-output LUT_2 to the output terminal ROUT3_i of the third inverter in the inner loop;

[0067] Step 4: Connect the output terminal O of the two-input, one-output LUT_2 to the input terminal ROIN1_i of the first inverter in the inner loop.

[0068] The inverter is configured using the following steps:

[0069] Step 1: Set the initial value of the input-output LUT_1 to 2'b01;

[0070] Step 2: Connect the input terminal I of the one-input-one-output LUT_1 to the corresponding input;

[0071] Step 3: Connect the output terminal O of the input-output LUT_1 to the corresponding output;

[0072] In this embodiment, the operation method of an octagonal dual-ring high-throughput TRNG circuit based on FPGAs is carried out according to the following steps:

[0073] Step 1: Based on the overall schematic diagram of the octagonal double-loop high-throughput TRNG circuit, write the octagonal double-loop high-throughput TRNG circuit using Verilog HDL. Set the frequency of the clock input terminal CLK_i of the four D flip-flops in the sampling circuit to f. This clock signal is generated by setting the IP core.

[0074] Step 2: Create a new .ucf file and perform pin constraints on the clock signal required to implement the octagonal double-loop high-throughput TRNG circuit and the UART signal required to transmit data to the host computer.

[0075] Step 3: After synthesis and implementation using ISE 14.7, download the program;

[0076] Step 4: Using the MicroBlaze soft-core processor and SDK software debugging package, initialize all enable terminals EN in the entropy source circuit to 0;

[0077] Step 5, 100ms later, using the MicroBlaze soft core processor and SDK software debugging package, all enable terminals EN=1 in the entropy source circuit are set to oscillate.

[0078] Step 6: Use the sampling circuit to collect the output sequence {OUT_i, i = 1, 2, 3, 4} of the four substructures in the entropy source circuit;

[0079] Step 7: Input {OUT_i, i = 1, 2, 3, 4} into the post-processing circuit, and let it go through two stages of post-processing to output the random sequence TRNG_OUT of the TRNG circuit.

[0080] Step 8: Upload the random sequence output TRNG_OUT of the obtained octagonal double-ring high-throughput TRNG circuit to the host computer via UART serial port, and then perform randomness testing.

[0081] Randomness testing steps:

[0082] The randomness of the generated random bit data was tested using the NIST test suite. NIST tests are standards published by the National Institute of Standards and Technology (NIST) for testing the randomness of binary sequences, with NIST SP800 being a series of information security guidelines. NIST SP800-22, specifically released by NIST for evaluating the randomness of arbitrary random number sequences, is one of the most widely used test suites. NIST SP800-22 contains 15 test items, and each test item reports its minimum p-value and pass rate. A test item is considered passed when its p-value is greater than 0.01. In this invention, all test items have p-values ​​significantly greater than 0.01, and the test results all pass the NIST test, demonstrating true randomness.

[0083] NIST SP800-90B is another crucial test suite for evaluating the quality of true random numbers. Unlike NIST SP800-22, NIST SP800-90B focuses on the null hypothesis of the test number sequence and uses different methods to estimate the statistical distribution and minimum entropy of the sequence. The randomness test of NIST SP800-90B consists of two test channels: the so-called independent and identically distributed (IID) test and the non-IID test. The IID test verifies whether each element in the random number sequence has the same probability distribution and whether all possible values ​​are independent of each other. The random sequences generated in this invention all passed the SP800-90 B test.

[0084] To further illustrate the positive effects of this invention, the proposed octagonal dual-loop high-throughput TRNG circuit was designed and implemented using Xilinx Kintex-7 and Xilinx Artix-7 FPGA platforms. The designed TRNG achieved throughputs of 300 Mbps and 320 bps, respectively, with resource consumption of 35 LUTs and 4 D flip-flops, simultaneously meeting the requirements of low resource consumption and high throughput. To more intuitively demonstrate the superiority of this invention in terms of resource consumption and throughput, the data from this invention were compared with several existing high-quality TRNG circuit structures that use jitter or metastability as entropy sources, as shown in Table 1.

[0085] Table 1. Comparison of experimental data from this invention with other high-quality TRNG experimental data.

[0086] Document 1 Shaking 528 177 6Mbps Spartan-3A Document 2 Shaking 10 5 1.15Mbps Spartan-6 Document 3 Metastable state 36 0 12.5Mbps Spartan-6 This invention jitter + metastability 35 4 320Mbps Artix-7 This invention jitter + metastability 35 4 300Mbps Kintex-7

[0087] Reference 1 is NN Anandakumar, SK Sanadhya, and M.S. Hashmi, “FPGA-based true random number generation using programmable delays in oscillator-rings,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 3, pp. 570-574, Mar. 2020.

[0088] The second document is B.Yang, N.Mentens, M.Grujic, N.Mentens, and I.Verbauwhede, "ES-TRNG: A high-throughput, low-area true random number generator based on edgesampling," IACR Trans.Cryptograph.Hardw.Embedded Syst., vol.2018, no.3, pp.267-292, 2018.

[0089] The third document is RDSala, D.Bellizia and G.Scotti, "High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, doi:10.1109 / TCSI.2022.3199218.

[0090] Table 1 further illustrates the hybrid entropy source method employed in this invention. Through circuit structure design, both jitter and metastability entropy sources are utilized as the source of randomness, significantly reducing hardware resource overhead. Simultaneously, a high throughput of 320 Mbps is achieved on Artix-7 and 300 Mbps on Kintex-7, while ensuring structural robustness. This makes it suitable for demanding information security applications such as encryption and decryption. Table 1 demonstrates that, in terms of the ratio of throughput to FPGA resource utilization, this invention outperforms most existing TRNGs.

Claims

1. An octagonal dual-ring high-throughput TRNG circuit based on FPGAs, characterized in that, include: Entropy source circuit, sampling circuit, post-processing circuit; The entropy source circuit consists of four identical substructures; Any i-th substructure consists of an inner ring and an outer ring. The inner ring of any i-th substructure consists of three single-input inverters and one two-input XOR gate. The outer ring of any i-th substructure consists of two single-input inverters and one two-input NAND gate, i∈[1,4]. In the outer ring of the i-th substructure, the output terminal rout1_i of the first single-input inverter is connected to the input terminal rout2_i of the second single-input inverter; The output terminal rout2_i of the second single-input inverter is connected to the data input terminal NAND of the dual-input NAND gate; The output terminal NOUT of the dual-input NAND gate is used as the input terminal of the first single-input inverter, and the enable input terminal EN of the dual-input NAND gate is connected to the external enable signal EN. The output terminal rout2_i of the second single-input inverter is used as the output terminal of the outer loop of the i-th substructure and connected to the inner loop of the i-th substructure; In the inner ring of the i-th substructure, the output terminal ROUT1_i of the first single-input inverter is connected to the input terminal ROIN2_i of the second single-input inverter; The output terminal ROUT2_i of the second single-input inverter is connected to the input terminal ROIN3_i of the third single-input inverter; The output terminal ROUT3_i of the third single-input inverter is connected to the inner loop input terminal XOR_1_i of the dual-input XOR gate; the outer loop input terminal XOR_2_i of the dual-input XOR gate is connected to the output terminal rout2_i of the second single-input inverter in the outer loop. The output of the dual-input XOR gate is connected to the input ROIN1_i of the first single-input inverter; The output terminal ROUT2_i of the second single-input inverter in the inner loop of the i-th substructure is taken as the entropy source output terminal OUT_i of the i-th substructure; Each substructure is connected by a single-input single-output buffer. Each single-input buffer contains an input terminal BIN and an output terminal BOUT. The input terminal BIN is connected to the output terminal ROUT1_i of the first single-input inverter in the inner loop of the i-th substructure, and the output terminal BOUT is connected to the inner loop input terminal XOR_1_i+1 of the dual-input XOR gate in the (i+1)-th substructure, to form an octagonal ring. The sampling circuit consists of four D flip-flops. Any i-th D flip-flop includes: a data input terminal D_i, a clock input terminal CLK_i, and a data output terminal Q_i. Among them, the data input terminal D_i of the i-th D flip-flop is connected to the entropy source output terminal OUT_i of the i-th substructure; the clock input terminal CLK_i of the i-th D flip-flop receives the output signal of the external IP core; the data output terminal Q_i of the i-th D flip-flop is connected to the input terminal of the first-stage XOR gate in the post-processing circuit. The post-processing circuit consists of three two-input XOR gates and is divided into two stages. The first stage consists of two two-input XOR gates, and the second stage consists of one two-input XOR gate. The input terminals of the first two-input XOR gate in the first stage are connected to the data output terminals Q_1 and Q_2 of the first D flip-flop in the sampling circuit, respectively; the input terminals of the second two-input XOR gate in the first stage are connected to the data output terminals Q_3 and Q_4 of the third D flip-flop in the sampling circuit, respectively. The input terminals of the two-input XOR gates in the second stage are respectively connected to the output terminals XOR_OUT_1 and XOR_OUT_2 of the first two-input XOR gates in the first stage. The output terminal of the two-input XOR gates in the second stage serves as the output terminal TRNG_OUT of the TRNG circuit.

2. The operating method of the octagonal dual-ring high-throughput TRNG circuit based on FPGAs according to claim 1, characterized in that: Follow these steps: Step 1: Initialize all enable terminals EN in the entropy source circuit to 0, and set the clock input CLK_i of the i-th D flip-flop in the sampling circuit to f; Step 2: Set all enable terminals EN=1 in the entropy source circuit to make the entropy source circuit start oscillating; Step 3: Use the sampling circuit to collect the output sequence {OUT_i, i = 1, 2, 3, 4} of the four substructures in the entropy source circuit; Step 4: Input {OUT_i, i = 1, 2, 3, 4} into the post-processing circuit, and let it go through two stages of post-processing to output the random sequence TRNG_OUT of the TRNG circuit.

Images