A refresh control circuit, memory and refresh control method

Abstract

This disclosure provides a refresh control circuit, a memory, and a refresh control method. The refresh control circuit includes: a processing module configured to receive a refresh command signal, perform pulse merging processing on the refresh command signal to obtain a refresh merged signal; the refresh command signal has multiple pulses in a first time period, and the refresh command signal maintains a constant level state in a second time period, with the first and second time periods alternating; a logic module configured to receive the refresh command signal and the refresh merged signal, perform logical operations on the refresh command signal and the refresh merged signal to obtain a target control signal; and a power supply module configured to receive the target control signal and determine whether to perform a power supply operation based on the level state of the target control signal. Thus, for multiple refresh operations, the power supply module only needs to supply power concentratedly in the first time period, which can reduce the number of switching operations of the power supply module and save current consumption.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and in particular to a refresh control circuit, a memory, and a refresh control method. Background Technology

[0002] In the self-refresh mode of Dynamic Random Access Memory (DRAM), the memory needs to be in a refresh state during a refresh operation and return to an idle state after the refresh operation is completed. However, the repeated switching between the refresh and idle states results in current consumption, which negatively impacts memory performance. Summary of the Invention

[0003] This disclosure provides a refresh control circuit, a memory, and a refresh control method that centrally power multiple refresh operations to reduce current loss.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a refresh control circuit applied to a memory, the refresh control circuit comprising:

[0006] The processing module is configured to receive a refresh command signal, perform pulse merging processing on the refresh command signal, and obtain a refresh merged signal; wherein, the refresh command signal has multiple pulses in a first time period, the refresh command signal maintains a constant level in a second time period, and the first time period and the second time period alternate;

[0007] The logic module is configured to receive the refresh command signal and the refresh merge signal, perform logical operations on the refresh command signal and the refresh merge signal to obtain a target control signal; wherein the target control signal has different level states in the first time period and the second time period.

[0008] The power supply module is configured to receive the target control signal, determine whether to perform a power supply operation based on the level state of the target control signal, and the power supply operation is used to support the execution of the refresh operation.

[0009] In some embodiments, the processing module is specifically configured to control the refresh merging signal to change from a first state to a second state according to the first signal edge of the refresh command signal in the first time period; and to control the refresh merging signal to change from a second state to a first state according to the last signal edge of the refresh command signal in the first time period.

[0010] In some embodiments, the processing module includes a frequency divider and a first inverter; wherein,

[0011] The frequency divider is configured to receive the refresh command signal, perform frequency division processing on the refresh command signal, and obtain the frequency-divided signal.

[0012] The first inverter is configured to receive the frequency-divided signal, invert the frequency-divided signal, and obtain the refreshed and merged signal.

[0013] The number of pulses of the refresh command signal within the first time period is a fixed value.

[0014] In some embodiments, the processing module is further configured to perform a reset process on the frequency divider during the second time period.

[0015] In some embodiments, the frequency divider includes A flip-flops and A second inverters; wherein,

[0016] The input terminal of the i-th flip-flop is connected to the output terminal of the i-th second inverter, and the output terminal of the i-th flip-flop is connected to the input terminal of the i-th second inverter.

[0017] The clock terminal of the first flip-flop is used to receive the refresh command signal. When i is greater than or equal to 2, the clock terminal of the i-th flip-flop is connected to the output terminal of the (i-1)-th flip-flop. The output terminal of the A-th flip-flop is used to output the frequency-divided signal.

[0018] Where A is a positive integer greater than 1, and i is a positive integer less than or equal to A.

[0019] In some embodiments, the target control signal is in a third state during the first time period, and the target control signal is in a fourth state, either entirely or partially, during the second time period;

[0020] The power supply module is specifically configured to, when the target control signal is in the third state, be turned on to perform a power supply operation; or, when the target control signal is in the fourth state, be turned off to not perform a power supply operation.

[0021] In some embodiments, the first state and the third state are both high-level states, and the second state and the fourth state are both low-level states.

[0022] In some embodiments, the logic module includes a first NOR gate, a second NOR gate, and a third inverter; wherein,

[0023] The first input terminal of the first NOR gate is connected to the refresh command signal, and the first input terminal of the second NOR gate is connected to the refresh merge signal;

[0024] The second input terminal of the first NOR gate is connected to the output terminal of the second NOR gate, and the second input terminal of the second NOR gate and the input terminal of the third inverter are both connected to the output terminal of the first NOR gate.

[0025] The output of the third inverter is used to output the target control signal.

[0026] Secondly, embodiments of this disclosure provide a memory, the memory including a refresh controller and a refresh control circuit; wherein,

[0027] The refresh controller is configured to generate a refresh command signal, wherein the refresh command signal has multiple pulses in a first time period, and the refresh command signal maintains a constant level in a second time period, and the first time period and the second time period alternate.

[0028] The refresh control circuit is configured to receive the refresh command signal, perform pulse merging and logical operation processing on the refresh command signal to obtain a target control signal, wherein the level state of the target control signal is different in the first time period and the second time period; and determine whether to perform a power supply operation based on the level state of the target control signal, wherein the power supply operation is used to support the execution of the refresh operation.

[0029] In some embodiments, the target control signal is in a third state during the first time period, and the target control signal is in a fourth state, either entirely or partially, during the second time period;

[0030] The refresh control circuit includes a power supply module and is further configured to, when the target control signal is in a third state, adjust the power supply module to an on state to perform a power supply operation; or, when the target control signal is in a fourth state, adjust the power supply module to a off state to not perform a power supply operation.

[0031] In some embodiments, the memory further includes:

[0032] The storage array, connected to the refresh controller and the refresh control circuit, is configured to receive the refresh command signal; and, when the refresh control circuit performs a power supply operation, to perform a refresh operation based on a pulse in the refresh command signal.

[0033] Thirdly, embodiments of this disclosure provide a refresh control method applied to a memory including a refresh control circuit, the method comprising:

[0034] A refresh command signal is determined, and the refresh command signal has multiple pulses in a first time period, and the refresh command signal maintains a constant level in a second time period, with the first time period and the second time period alternating;

[0035] The refresh command signal is processed by pulse merging and logical operation to obtain the target control signal, and the target control signal has different level states in the first time period and the second time period.

[0036] Based on the level of the target control signal, it is determined whether the refresh control circuit performs a power supply operation, and the power supply operation is used to support the execution of the refresh operation.

[0037] In some embodiments, the target control signal is in a third state during the first time period, and the target control signal is in a fourth state, either entirely or partially, during the second time period;

[0038] The step of determining whether the refresh control circuit in the memory should perform a power supply operation based on the level state of the target control signal includes:

[0039] When the target control signal is in the third state, the power supply module in the refresh control circuit is switched to the on state to perform a power supply operation; or,

[0040] When the target control signal is in the fourth state, the power supply module in the refresh control circuit is adjusted to the off state so that no power supply operation is performed.

[0041] In some embodiments, the method further includes:

[0042] When the refresh control circuit performs a power supply operation, it controls the memory to perform a refresh operation based on a pulse in the refresh command signal.

[0043] In some embodiments, the step of performing pulse merging and logical operation processing on the refresh command signal to obtain the target control signal includes:

[0044] The refresh command signal is subjected to pulse merging processing to obtain a refresh merged signal;

[0045] The refresh command signal and the refresh merge signal are subjected to logical operations to obtain the target control signal.

[0046] This disclosure provides a refresh control circuit, a memory, and a refresh control method. Multiple refresh operations are generated in a first time period so that power supply operations are performed centrally in the first time period. As a result, the power supply module only needs to be switched on and off once for multiple refresh operations, reducing the number of times the power supply module is switched on and off, saving current loss, and improving the performance of the memory. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of a partial structure of a memory.

[0048] Figure 2 This is a schematic diagram of a signal timing.

[0049] Figure 3 This is a schematic diagram of a refresh control circuit provided in an embodiment of the present disclosure;

[0050] Figure 4 A signal timing diagram provided in an embodiment of this disclosure;

[0051] Figure 5 This is another signal timing diagram provided in an embodiment of the present disclosure;

[0052] Figure 6 This is a schematic diagram of another refresh control circuit provided in an embodiment of the present disclosure;

[0053] Figure 7 This is a schematic diagram of the structure of a frequency divider provided in an embodiment of the present disclosure;

[0054] Figure 8 A schematic diagram of the structure of a memory provided in an embodiment of this disclosure;

[0055] Figure 9 A schematic diagram of another memory structure provided in an embodiment of this disclosure;

[0056] Figure 10 This is a flowchart illustrating a refresh control method provided in an embodiment of the present disclosure. Detailed Implementation

[0057] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0059] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0060] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0061] Memory (such as DRAM) needs to be refreshed to maintain data validity. In self-refresh mode, there are two main sources of current loss: the refresh current generated in the memory array, and the control current of the peripheral circuitry.

[0062] Specifically, in self-refresh mode, the memory exists in a refresh state and an idle state. During a refresh operation, the memory needs to switch from the idle state to the refresh state, turning on the power amplifier (PowerAmplifier) ​​and the local power domain for the row signals. The power amplifier provides control current to the peripheral circuitry, while the local power domain provides refresh current generated within the memory array; both the power amplifier and the local power domain power the refresh operation. After the refresh operation is complete, the memory needs to switch from the refresh state to the idle state, turning off the power amplifier and the local power domain.

[0063] See Figure 1 This shows a schematic diagram of a partial structure of a memory. See also... Figure 2 It illustrates a signal timing diagram. For example... Figure 1 and Figure 2As shown, the refresh controller generates a refresh command signal, where each pulse indicates a refresh operation. The refresh command signal is processed into a refresh control signal, with a one-to-one correspondence between the pulses in the refresh command and refresh control signals, and the pulse width in the refresh control signal being slightly wider than that in the refresh command signal. The refresh control signal is input to the Power Amplifier and Local Power Domain. The rising edge of the refresh control signal turns on the Power Amplifier and Local Power Domain, switching the memory to refresh mode, thus executing refresh operation 0 or refresh operation 1. The falling edge of the refresh control signal turns off the Power Amplifier and Local Power Domain, switching the memory to standby mode. In other words, each refresh operation causes the Power Amplifier and Local Power Domain to switch on and off.

[0064] However, each time the Power Amplifier and Local Power Domain are turned on or off, they consume current, which negatively impacts memory performance.

[0065] Based on this, this disclosure provides a refresh control circuit, including: a processing module configured to receive a refresh command signal and perform pulse merging processing on the refresh command signal to obtain a refresh merged signal; wherein the refresh command signal has multiple pulses in a first time period, and the refresh command signal maintains a constant level state in a second time period, with the first and second time periods alternating; a logic module configured to receive the refresh command signal and the refresh merged signal, and perform logical operations on the refresh command signal and the refresh merged signal to obtain a target control signal; wherein the target control signal has different level states in the first and second time periods; and a power supply module configured to receive the target control signal and determine whether to perform a power supply operation based on the level state of the target control signal, wherein the power supply operation is used to support the execution of refresh operations. In this way, multiple refresh operations are generated in the first time period, and the power supply operation is executed centrally in the first time period, so that the power supply module only needs to switch on and off once for multiple refresh operations, reducing the number of switching operations of the power supply module, saving current consumption, and improving memory performance.

[0066] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0067] In one embodiment of this disclosure, see Figure 3This illustrates a schematic diagram of a refresh control circuit 10 provided in an embodiment of the present disclosure. Figure 3 As shown, the refresh control circuit 10 may include:

[0068] Processing module 11 is configured to receive refresh command signal, perform pulse merging processing on refresh command signal to obtain refresh merge signal; wherein, refresh command signal has multiple pulses in the first time period, refresh command signal maintains a constant level in the second time period, and the first time period and the second time period alternate.

[0069] Logic module 12 is configured to receive refresh command signal and refresh merge signal, perform logical operations on refresh command signal and refresh merge signal to obtain target control signal; wherein the target control signal has different level states in the first time period and the second time period.

[0070] The power supply module 13 is configured to receive the target control signal, determine whether to perform a power supply operation based on the level of the target control signal, and the power supply operation is used to support the execution of the refresh operation.

[0071] It should be noted that the refresh control circuit 10 of this embodiment can be applied to memory, such as DRAM or Synchronous Dynamic Random Access Memory (SDRAM), and can reduce current consumption during the refresh process.

[0072] Here, the power supply module 13 may include the aforementioned Power Amplifier and Local Power Domain. When the power supply module 13 performs a power supply operation, the memory is in a refresh state, allowing the refresh operation to be performed; when the power supply module 13 does not perform a power supply operation, the memory is in an idle state, and the refresh operation cannot be performed.

[0073] It should be noted that one pulse in the refresh command signal indicates one refresh operation. The refresh control circuit 10 can concentrate the refresh operations within a first time period, thereby reducing the number of times the power supply module switches on and off. For example, see... Figure 4 This illustrates a signal timing diagram provided in an embodiment of the present disclosure. Figure 4 As shown, the refresh command signal has multiple pulses in the first time period, and the target control signal will remain unchanged in the first time period until it is adjusted to another level in the second time period. Thus, the power supply module 13 always performs power supply operation in the first time period and does not perform power supply operation in the second time period.

[0074] In this way, since multiple refresh operations are concentrated in the first time period, the power supply operation only needs to be performed in the first time period. The power supply module only needs to be switched on and off once for multiple refresh operations, which reduces the number of times the power supply module is switched on and off, saves current consumption, and improves the performance of the memory.

[0075] In some embodiments, the processing module 11 is specifically configured to control the refresh merging signal to change from a first state to a second state according to the first signal edge of the refresh command signal in the first time period; and to control the refresh merging signal to change from a second state to a first state according to the last signal edge of the refresh command signal in the first time period.

[0076] It should be noted that the first state and the second state are different. For example, the first state may refer to a high-level state, and the second state to a low-level state; or the first state may refer to a low-level state, and the second state to a high-level state, depending on the specific application scenario. Here, the high-level state allows the N-type MOSFET to conduct, and the low-level state allows the P-type MOSFET to conduct.

[0077] Here, a signal edge refers to either a rising edge or a falling edge. A rising edge occurs when a signal transitions from a low level to a high level, while a falling edge occurs when a signal transitions from a high level to a low level. In the foregoing description, the first signal edge can be a rising edge, in which case the last signal edge is a falling edge. Alternatively, the first signal edge can be a falling edge, in which case the last signal edge is a rising edge.

[0078] In one specific embodiment, see Figure 5 This illustrates another signal timing diagram provided by an embodiment of the present disclosure. Figure 5 As shown, assuming the refresh command signal has N pulses in the first time period, after the first rising edge, the refresh merging signal changes from high to low; after the Nth falling edge, the refresh merging signal changes from low to high. N is a positive integer. Furthermore, since the refresh merging signal is generated by the refresh command signal, there is a certain delay between the two.

[0079] In this way, the time period during which the refresh command signal has multiple pulses corresponds to the time period during which the refresh merging signal is in the second state, thus realizing pulse merging processing.

[0080] In some embodiments, such as Figure 6 As shown, the processing module 11 may include a frequency divider 111 and a first inverter 112; wherein,

[0081] Frequency divider 111 is configured to receive refresh command signal, perform frequency division processing on refresh command signal, and obtain frequency-divided signal;

[0082] The first inverter 112 is configured to receive the frequency-divided signal, invert the frequency-divided signal, and obtain a refresh merged signal; wherein the number of pulses of the refresh command signal in the first time period is a fixed value.

[0083] It should be noted that the pulse width of the frequency-divided signal is the duration of multiple pulses of the refresh command signal within the first time period.

[0084] In addition, processing module 11 is also configured to reset the frequency divider during the second time period. Thus, as... Figure 5 As shown, after the first rising edge of the refresh command signal within the first time period, the refresh merging signal changes from a high level to a low level; after the Nth falling edge of the refresh command signal within the first time period, the refresh merging signal changes from a low level to a high level. Then, during the second time period, because the frequency divider 111 is reset, the level of the refresh merging signal will remain unchanged until a new pulse is generated by the refresh command signal.

[0085] It should also be noted that the first inverter 112 can also be placed before the frequency divider 111. That is, the refresh command signal is first input to the input terminal of the first inverter 112, and then the output terminal of the first inverter 112 is connected to the input terminal of the frequency divider 111. The frequency divider 111 is used to output the refresh merging signal.

[0086] In some embodiments, such as Figure 7 As shown, the frequency divider 111 includes A flip-flops and A second inverters; wherein, the input of the i-th flip-flop is connected to the output of the i-th second inverter, and the output of the i-th flip-flop is connected to the input of the i-th second inverter; the clock terminal of the 1st flip-flop is used to receive the refresh command signal, and when i is greater than or equal to 2, the clock terminal of the i-th flip-flop is connected to the output of the (i-1)-th flip-flop; the output of the A-th flip-flop is used to output the frequency-divided signal; wherein, A is a positive integer greater than 1, and i is a positive integer less than or equal to A.

[0087] It should be noted that the number of flip-flops in the frequency divider 111 can be determined based on the actual application scenario. For example... Figure 7 As shown, each flip-flop also has a reset terminal for receiving a reset signal rst and performing a reset process based on the reset signal rst.

[0088] In some embodiments, the target control signal is in the third state during a first time period, and the target control signal is in the fourth state in all or part of the second time period.

[0089] The power supply module 13 is specifically configured to be turned on to perform power supply operation when the target control signal is in the third state; or to be turned off to not perform power supply operation when the target control signal is in the fourth state.

[0090] It should be noted that the third state and the fourth state are different. The third state is a high level state and the fourth state is a low level state; or the third state is a low level state and the fourth state is a high level state, depending on the actual application scenario.

[0091] Here, the target control signal must be in the third state for the entire first time period, so that the power supply module 13 is always on during the first time period, ensuring that N refresh operations can be executed smoothly; conversely, the target control signal can be partially in the fourth state during the second time period, that is, the time when the target control signal is in the third state can be longer than the first time period, while covering the first time period, providing some redundant on time.

[0092] In this way, the power supply module 13 only needs to switch states according to the target control signal, and does not need to switch on and off repeatedly during the execution of N refresh operations, thus reducing power consumption.

[0093] In one specific embodiment, such as Figure 5 As shown, the first and third states are both high-level states, while the second and fourth states are both low-level states. For ease of explanation, the signal edge generated when the refresh merging signal changes from the first state to the second state is called the first signal edge, and the signal edge generated when the refresh merging signal changes from the second state to the first state is called the second signal edge. Similarly, the signal edge generated when the target control signal changes from the fourth state to the third state is called the third signal edge, and the signal edge generated when the target control signal changes from the third state to the fourth state is called the fourth signal edge.

[0094] like Figure 5 It is known that the first signal edge is delayed by the first signal edge of the refresh command signal in the corresponding first time period, and the second signal edge is delayed by the last signal edge of the refresh command signal in the corresponding first time period. Therefore, logic module 12 is needed to perform further calculations on the refresh merging signal and the refresh command signal to ensure that the third state of the target control signal can completely cover the first time period.

[0095] In some embodiments, such as Figure 6As shown, the logic module 12 may include a first NOR gate 121, a second NOR gate 122, and a third inverter 123; wherein, the first input terminal of the first NOR gate 121 is connected to the refresh command signal, and the first input terminal of the second NOR gate 122 is connected to the refresh merging signal; the second input terminal of the first NOR gate 121 is connected to the output terminal of the second NOR gate 122, and the second input terminal of the second NOR gate 122 and the input terminal of the third inverter 123 are both connected to the output terminal of the first NOR gate 121; the output terminal of the third inverter 123 is used to output the target control signal.

[0096] Therefore, please refer to Figure 5 The third signal edge of the target control signal is aligned with the first signal edge of the refresh command signal in the corresponding first time period, and the fourth signal edge of the target control signal is aligned with the corresponding second signal edge. That is, the power supply module 13 always performs power supply operation in the first time period to support the execution of multiple refresh operations.

[0097] This disclosure provides a refresh control circuit. By optimizing the refresh control, multiple refresh operations can be completed in one go, which can greatly reduce the number of times the power supply module is switched on and off, thereby reducing current consumption.

[0098] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 8 This illustrates a schematic diagram of the composition structure of a memory 20 provided in an embodiment of this disclosure. For example... Figure 8 As shown, the memory 20 may include a refresh controller 201 and a refresh control circuit 10; wherein,

[0099] The refresh controller 201 is configured to generate a refresh command signal, and the refresh command signal has multiple pulses in the first time period, and the refresh command signal maintains a constant level in the second time period, with the first time period and the second time period alternating.

[0100] The refresh control circuit 10 is configured to receive a refresh command signal, perform pulse merging and logical operation processing on the refresh command signal to obtain a target control signal, wherein the level state of the target control signal is different in the first time period and the second time period; and, based on the level state of the target control signal, determine whether to perform a power supply operation, wherein the power supply operation is used to support the execution of the refresh operation.

[0101] It should be noted that one pulse in the refresh command signal indicates one refresh operation. In other words, the memory 20 can perform multiple refresh operations in a single time period, reducing the number of power supply switching operations and saving current consumption.

[0102] Here, as Figure 9As shown, the refresh control circuit 10 may include a processing module 11, a logic module 12, and a power supply module 13, and its specific structure can be referred to the foregoing content.

[0103] exist Figure 9 Based on this, in some implementations, the target control signal is in the third state in the first time period, and the target control signal is in the fourth state in all or part of the second time period.

[0104] The refresh control circuit 10 is also configured to adjust the power supply module 13 to the on state to perform power supply operation when the target control signal is in the third state; or, when the target control signal is in the fourth state, adjust the power supply module 13 to the off state to not perform power supply operation.

[0105] It should be noted that the third state of the target control signal covers at least the first time period, so that the refresh control circuit 10 is always powered during the first time period to support the execution of multiple refresh operations.

[0106] In some embodiments, the memory 20 may further include:

[0107] The storage array, connected to the refresh controller 201 and the refresh control circuit 10, is configured to receive refresh command signals; when the refresh control circuit 10 performs a power supply operation, it performs a refresh operation based on a pulse in the refresh command signal.

[0108] This disclosure provides a memory that, by optimizing refresh control, can perform multiple refresh operations in a concentrated manner. This greatly reduces the number of power supply switching operations, thereby reducing current consumption.

[0109] In some embodiments of this disclosure, see Figure 10 This illustrates a flowchart of a refresh control method provided in an embodiment of this disclosure. Figure 10 As shown, the method may include:

[0110] S301: Determine the refresh command signal, and the refresh command signal has multiple pulses in the first time period. The refresh command signal maintains a constant level in the second time period. The first time period and the second time period alternate.

[0111] It should be noted that the refresh control method provided in this embodiment is applied to a memory 20 that includes a refresh control circuit 10, and the specific structure of the refresh control circuit 10 is described above.

[0112] S302: Perform pulse merging and logical operation processing on the refresh command signal to obtain the target control signal, and the target control signal has different level states in the first time period and the second time period.

[0113] S303: Based on the level of the target control signal, determine whether the refresh control circuit should perform a power supply operation, and the power supply operation is used to support the execution of the refresh operation.

[0114] In some embodiments, when the refresh control circuit performs a power supply operation, the memory is controlled to perform a refresh operation based on a pulse in the refresh command signal.

[0115] In this way, multiple refresh operations are performed in the first time period, so power is only needed in the first time period, which reduces the number of power supply switching operations, reduces circuit consumption, and improves memory performance.

[0116] In some embodiments, the target control signal is in a third state during a first time period, and all or part of the target control signal is in a fourth state during a second time period. Determining whether the refresh control circuit in the memory performs a power supply operation based on the level state of the target control signal may include:

[0117] When the target control signal is in the third state, the refresh control circuit is switched to the on state to perform the power supply operation; or, when the target control signal is in the fourth state, the refresh control circuit is switched to the off state to not perform the power supply operation.

[0118] In some embodiments, the pulse merging and logical operation processing of the refresh command signal to obtain the target control signal may include:

[0119] The refresh command signal is pulse-merged to obtain the refresh merged signal; logical operations are performed on the refresh command signal and the refresh merged signal to obtain the target control signal.

[0120] In one specific embodiment, the pulse merging processing of the refresh command signal to obtain a refresh merged signal may include:

[0121] During the first time period, the refresh command signal is frequency divided to obtain the frequency-divided signal; the frequency-divided signal is then inverted to obtain the refresh merged signal; the number of pulses of the refresh command signal during the first time period is a fixed value; during the second time period, signal reset processing is performed to keep the level of the refresh merged signal unchanged.

[0122] It should be noted that frequency division can be accomplished using multiple flip-flops and multiple inverters; see details below. Figure 7 Assuming the first state refers to a high-level state and the second state refers to a low-level state, such as... Figure 5As shown, after the first rising edge of the refresh command signal within the first time period, the refresh merging signal changes from a high level to a low level; after the Nth falling edge of the refresh command signal within the first time period, the refresh merging signal changes from a low level to a high level. Then, during the second time period, due to the signal reset process, the level of the refresh merging signal will remain unchanged until a new pulse is generated by the refresh command signal.

[0123] Thus, after the first signal edge of the refresh command signal in the first time period, the refresh merging signal is adjusted from the first state to the second state; after the last signal edge of the refresh command signal in the first time period, the refresh merging signal is adjusted from the second state to the first state, until the arrival of the next first time period. In a specific embodiment, the level changes of the refresh command signal and the refresh merging signal are as follows: Figure 5 As shown. Accordingly, the step of performing logical operations on the refresh command signal and the refresh merging signal to obtain the target control signal may include:

[0124] The refresh command signal and the first intermediate processing signal are ORed together to obtain the second intermediate processing signal; wherein, the first intermediate processing signal is obtained by ORing the refresh merge signal and the second intermediate processing signal; the second intermediate processing signal is NOTed to obtain the target control signal.

[0125] In this way, the rising edge of the target control signal is aligned with the first signal edge of the refresh command signal in the first time period, and the falling edge of the target control signal is aligned with the rising edge of the refresh merging signal. As a result, the third state of the target control signal can completely cover the first time period, ensuring that multiple refresh operations can be executed normally.

[0126] This disclosure provides a refresh control method. By optimizing the refresh control, multiple refresh operations can be completed in one go, which can greatly reduce the number of power supply switching operations, thereby reducing current consumption.

[0127] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A refresh control circuit, characterized by comprising: The refresh control circuit, applied to a memory, includes: The processing module is configured to receive a refresh command signal, perform pulse merging processing on the refresh command signal, and obtain a refresh merged signal; wherein, the refresh command signal has multiple pulses in a first time period, the refresh command signal maintains a constant level in a second time period, and the first time period and the second time period alternate; The logic module is configured to receive the refresh command signal and the refresh merge signal, perform logical operations on the refresh command signal and the refresh merge signal to obtain a target control signal; wherein the target control signal has different level states in the first time period and the second time period. The power supply module is configured to receive the target control signal, determine whether to perform a power supply operation based on the level state of the target control signal, and the power supply operation is used to support the execution of the refresh operation; The processing module is specifically configured to control the refresh merging signal to change from a first state to a second state based on the first signal edge of the refresh command signal in the first time period; and to control the refresh merging signal to change from a second state to a first state based on the last signal edge of the refresh command signal in the first time period.

2. The refresh control circuit of claim 1, wherein, The processing module includes a frequency divider and a first inverter; wherein... The frequency divider is configured to receive the refresh command signal, perform frequency division processing on the refresh command signal, and obtain the frequency-divided signal. The first inverter is configured to receive the frequency-divided signal, invert the frequency-divided signal, and obtain the refreshed and merged signal. The number of pulses of the refresh command signal within the first time period is a fixed value.

3. The refresh control circuit according to claim 2, characterized in that, The processing module is further configured to perform a reset process on the frequency divider during the second time period.

4. The refresh control circuit of claim 2, wherein, The frequency divider includes A flip-flops and A second inverters; wherein... The input terminal of the i-th flip-flop is connected to the output terminal of the i-th second inverter, and the output terminal of the i-th flip-flop is connected to the input terminal of the i-th second inverter. The clock terminal of the first flip-flop is used to receive the refresh command signal. When i is greater than or equal to 2, the clock terminal of the i-th flip-flop is connected to the output terminal of the (i-1)-th flip-flop. The output terminal of the A-th flip-flop is used to output the frequency-divided signal. Where A is a positive integer greater than 1, and i is a positive integer less than or equal to A.

5. The refresh control circuit of claim 1, wherein, The target control signal is in a third state during the first time period, and the target control signal is in a fourth state, either entirely or partially, during the second time period. The power supply module is specifically configured to, when the target control signal is in the third state, be turned on to perform a power supply operation; or, when the target control signal is in the fourth state, be turned off to not perform a power supply operation.

6. The refresh control circuit of claim 5, wherein, Both the first state and the third state are high-level states, while both the second state and the fourth state are low-level states.

7. The refresh control circuit of claim 6, wherein, The logic module includes a first NOR gate, a second NOR gate, and a third inverter; wherein... The first input terminal of the first NOR gate is connected to the refresh command signal, and the first input terminal of the second NOR gate is connected to the refresh merge signal; The second input terminal of the first NOR gate is connected to the output terminal of the second NOR gate, and the second input terminal of the second NOR gate and the input terminal of the third inverter are both connected to the output terminal of the first NOR gate. The output of the third inverter is used to output the target control signal.

8. A memory, comprising: The memory includes a refresh controller and a refresh control circuit; wherein... The refresh controller is configured to generate a refresh command signal, wherein the refresh command signal has multiple pulses in a first time period, and the refresh command signal maintains a constant level in a second time period, and the first time period and the second time period alternate. The refresh control circuit is configured to receive the refresh command signal, perform pulse merging and logical operation processing on the refresh command signal to obtain a target control signal, wherein the target control signal has different level states in the first time period and the second time period; and determine whether to perform a power supply operation based on the level state of the target control signal, wherein the power supply operation is used to support the execution of the refresh operation. The refresh control circuit includes: The processing module is configured to receive the refresh command signal, perform pulse merging processing on the refresh command signal, and obtain a refresh merged signal; wherein, the refresh command signal has multiple pulses in a first time period, the refresh command signal maintains a constant level in a second time period, and the first time period and the second time period alternate; The logic module is configured to receive the refresh command signal and the refresh merge signal, perform logical operations on the refresh command signal and the refresh merge signal to obtain the target control signal; The processing module is specifically configured to control the refresh merging signal to change from a first state to a second state based on the first signal edge of the refresh command signal in the first time period; and to control the refresh merging signal to change from a second state to a first state based on the last signal edge of the refresh command signal in the first time period.

9. The memory of claim 8, wherein, The target control signal is in a third state during the first time period, and the target control signal is in a fourth state, either entirely or partially, during the second time period. The refresh control circuit includes a power supply module and is further configured to, when the target control signal is in a third state, adjust the power supply module to an on state to perform a power supply operation; or, when the target control signal is in a fourth state, adjust the power supply module to a off state to not perform a power supply operation.

10. The memory of claim 8, wherein, The memory also includes: The storage array, connected to the refresh controller and the refresh control circuit, is configured to receive the refresh command signal; and, when the refresh control circuit performs a power supply operation, to perform a refresh operation based on a pulse in the refresh command signal.

11. A refresh control method, characterized by, Applied to a memory containing refresh control circuitry, the method includes: A refresh command signal is determined, and the refresh command signal has multiple pulses in a first time period, and the refresh command signal maintains a constant level in a second time period, with the first time period and the second time period alternating; The refresh command signal is processed by pulse merging and logical operation to obtain the target control signal, and the target control signal has different level states in the first time period and the second time period. Based on the level state of the target control signal, it is determined whether the refresh control circuit performs a power supply operation, and the power supply operation is used to support the execution of the refresh operation; The step of performing pulse merging and logical operation processing on the refresh command signal to obtain the target control signal includes: The refresh command signal is subjected to pulse merging processing to obtain a refresh merged signal. Specifically, this includes controlling the refresh merged signal to change from a first state to a second state based on the first signal edge of the refresh command signal in the first time period; and controlling the refresh merged signal to change from a second state to a first state based on the last signal edge of the refresh command signal in the first time period. The refresh command signal and the refresh merge signal are subjected to logical operations to obtain the target control signal.

12. The refresh control method of claim 11, wherein, The target control signal is in a third state during the first time period, and the target control signal is in a fourth state, either entirely or partially, during the second time period. The step of determining whether the refresh control circuit in the memory should perform a power supply operation based on the level state of the target control signal includes: When the target control signal is in the third state, the power supply module in the refresh control circuit is turned on to perform a power supply operation; or, When the target control signal is in the fourth state, the power supply module in the refresh control circuit is adjusted to the off state so that no power supply operation is performed.

13. The refresh control method of claim 11, wherein, The method further includes: When the refresh control circuit performs a power supply operation, it controls the memory to perform a refresh operation based on a pulse in the refresh command signal.

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