Apparatus, method, and memory controller for row hammer mitigation using tiered detector

Abstract

This application relates to row hammer mitigation using tiered detectors. An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can include row hammer detection circuitry configured to receive signaling indicative of a row activate command having a row address, increment a row counter corresponding to the row address stored in a data structure in a register or storage device, determine whether the incremented row counter is greater than a row hammer threshold, and issue a row hammer mitigation command to mitigate a row hammer.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically to row hammer mitigation using a hierarchical detector. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this application provides an apparatus for row hammer mitigation using a layered detector, the apparatus comprising: a plurality of memory devices; and one or more memory controllers coupled to the plurality of memory devices, the memory controller including a row hammer detection circuitry configured to: receive signaling indicating a row activation command and a row address; increment a row counter corresponding to the row address in a data structure stored in a register or memory device coupled to the controller; determine that the incremented row counter is greater than a row hammer threshold (RHT); and, in response to determining that the incremented row counter is greater than the RHT, issue a row hammer mitigation command to mitigate the row hammer.

[0004] In another aspect, this application provides a method for row hammer mitigation using a hierarchical detector, the method comprising: receiving at a memory controller of a memory subsystem a signaling indicating a row activation command having a row address; incrementing a row counter corresponding to the row address, the row address being stored in a data structure of a first row hammer detector among a plurality of row hammer detectors included in the memory controller; determining at the memory controller whether the incremented row counter is greater than a row hammer threshold (RHT); and in response to determining that the incremented row counter is greater than the RHT, issuing a row hammer mitigation command to mitigate the row hammer.

[0005] In another aspect, this application provides a memory controller for row hammer mitigation using a hierarchical detector, the memory controller comprising: an interface management circuitry configured for a nondeterministic memory protocol; a first row hammer detector included in the row hammer detection circuitry; and a second row hammer detector included in the row hammer detection circuitry; wherein the memory controller is configured to: receive, via the interface management circuitry, a signaling instruction indicating a row activation command having a row address in a memory device; increment a row counter corresponding to the row address stored in a first data structure of the first row hammer detector; determine when the incremented row counter is greater than a first row hammer threshold of the first row hammer detector; and, in response to determining that the incremented row counter is greater than the first row hammer threshold, issue a row hammer mitigation command to perform row hammer detection using the second row hammer detector. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This is a functional block diagram of a computing system including a memory controller according to several embodiments of the present disclosure.

[0008] Figure 2 This is a functional block diagram of a memory controller having a first configuration according to several embodiments of the present disclosure.

[0009] Figure 3 This is a functional block diagram of a memory controller with a second configuration according to several embodiments of the present disclosure.

[0010] Figure 4 This is a functional flowchart of several embodiments of the present disclosure.

[0011] Figure 5 This is a flowchart of a method for row hammer mitigation using a layered detector, according to several embodiments of the present disclosure. Detailed Implementation

[0012] This describes a memory controller used for row hammer mitigation with a tiered detector. The memory controller may be contained within a device, such as a memory system. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system such as a solid-state drive (SSD).

[0013] In some embodiments, the memory system may be a nondeterministic memory protocol compatible memory system, such as a Compute High-Speed ​​Link (CXL) compatible memory system. For example, the host interface can be managed using the CXL protocol and coupled to the host via an interface configured for the Peripheral Component Interconnect High-Speed ​​(PCIe) protocol. CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to enhance the performance of next-generation data centers. CXL technology maintains memory coherence between the CPU memory space and the memory on the attached device, allowing resource sharing to achieve higher performance, reduced software stack complexity, and lower overall memory system cost. With the increasing use of accelerators to supplement CPUs to support emerging applications such as artificial intelligence and machine learning, CXL is designed as an industry-open standard interface for high-speed communication. CXL technology is built on the PCIe infrastructure, utilizing PCIe physical and electrical interfaces to provide advanced regional protocols such as input / output (I / O) protocols, memory protocols (e.g., initially allowing the host to share memory with the accelerator), and coherence interfaces.

[0014] Row hammering refers to the unintended change in capacitor voltage of a memory cell row due to frequent access to adjacent rows. Row hammering attacks can be used to intentionally alter, access, and / or corrupt data stored in memory by rapidly and repeatedly accessing specific rows. For example, a first row adjacent to a second row can be repeatedly accessed within a relatively short period of time. Repeated access to the first row can leak voltage from memory cells coupled to the second row to memory cells coupled to the first row. Voltage leakage can lead to data corruption in memory cells coupled to the second row. The first and second rows may not be directly adjacent, but may be within several rows of each other. As used herein, memory cells and / or rows may be adjacent to each other if they are physically close to each other in the memory array or physically close enough to allow charge to leak from memory cells coupled to a row to different memory cells coupled to different rows. Memory cell rows may be adjacent to different memory cell rows if the row addresses are contiguous and / or if there are no other rows between adjacent rows. Memory cells may be adjacent to each other if they are coupled to rows that are adjacent to each other.

[0015] Furthermore, due to various physical effects of geometric shrinkage during manufacturing, the row hammer threshold of a memory subsystem has been reduced to a level where applications running on the host computer system may unintentionally corrupt their own data or the data of different applications sharing the same memory. As used herein, the row hammer threshold is the threshold number of accesses to a row of memory cells after which the memory cells in that row leak charge.

[0016] Some hammer detector algorithms are probabilistic and therefore cannot guarantee perfect (e.g., complete, accurate, and / or precise) prevention of data corruption. For example, if an attacker knows enough details about these existing hammer detection methods and their implementation mechanisms, the attacker can exploit their weaknesses to bypass or disrupt the detector and corrupt the data.

[0017] Some implementations of hammer detector algorithms require excessive amounts of memory and / or operating power that are practically unusable. For example, methods attempting to eliminate any false alarms may utilize large amounts of memory and / or operating power to achieve this goal, and thus may be practically useless. Some methods can be implemented using large content-addressable memory (CAM). The CAM compares input search data with a table of stored data and returns the address of the matching data. However, a large CAM size (e.g., greater than 2.5 megabytes) makes such methods consume large amounts of memory and / or operating power.

[0018] This disclosure addresses the above and other drawbacks by implementing row hammer mitigation using hierarchical detectors. As used herein, a hierarchical detector generally refers to a row hammer detection circuitry system contained in an individual memory controller and configured to perform various aspects related to row hammer mitigation. For example, a row hammer detection circuitry system may refer to multiple row hammer detectors in an individual memory controller. The row hammer detection circuitry system may be contained in the same or different physical parts of the memory controller (e.g., a central part, a back-end part, etc.). For example, a first row hammer detector may be contained in the central part (e.g., in a central controller) and a second row hammer detector may be contained in a different part, such as a back-end part (e.g., in a channel controller / memory controller). However, in some embodiments, the row hammer detection circuitry system (e.g., a row hammer detector) may be contained in the same part of the memory controller (e.g., in a central controller).

[0019] In any case, hierarchical detectors allow for enhanced row hammer detection compared to other methods that rely on individual row hammer detectors, such as those on the memory device. That is, the embodiments described herein employ a memory device without row hammer detectors, unlike other methods. The hierarchical detectors described herein may reside on and execute entirely on one or more parts of the memory controller, while other methods rely on row hammer detectors on the memory device and are therefore constrained by the computational power and / or size of the memory device. For example, other methods may be constrained by the size of buffers and / or DIMMs in DRAM or other types of memory devices. Therefore, such methods may be limited to individual row hammer detectors on the memory device. Conversely, the methods described herein allow for the use of multiple row hammer detectors, different types of row hammer detectors, different row hammer mitigation commands, and / or enhanced / complex row hammer detectors (e.g., those capable of handling higher rates of events), which utilize greater power and / or can handle higher rates of data.

[0020] This disclosure also allows for smaller memory (e.g., SRAM) sizes and / or enables smaller maximum false alarm rates (in the absence of any false alarms), eliminating the risk of "denial of service" compared to previous methods. For example, the hierarchical detector can be customized to detect different types of row hammer events (e.g., one-sided row hammer attacks, two-sided row hammer attacks, etc.) and / or incorporate different types of row hammer detectors (e.g., a high-speed first row hammer detector for filtering events and a second, high-granularity row hammer detector for confirming the presence of a row hammer, etc.). Therefore, the accuracy, speed, and / or reduction of any number of false alarms / false alarms can be enhanced compared to individual, generic row hammer detectors designed to detect various / all types of row hammers and / or detectors limited by the amount of space / computing power available at the memory device.

[0021] Although the examples presented in this article are in the context of line hammer attacks, they can also be applied to data loss caused by memory cell leaks due to accessing memory cells or adjacent memory cells at rates greater than RHT.

[0022] Interfaces such as Peripheral Component Interconnect High Speed ​​(PCIe), Compute High Speed ​​Link (CXL), and Cache Coherent Interconnect for Accelerators (CCIX) allow various memory devices to be connected to a host system. The combination of interface and memory technology improvements can allow the deployment of “remote memory,” which may consist of system memory (e.g., memory devices) implemented behind a memory subsystem such as PCIe, CXL, CCIX, or GenZ. As used herein, the front end of a memory subsystem may also be referred to as the interface of the memory subsystem or the front end of the controller of the memory subsystem. As used herein, the front end of a memory subsystem may include hardware and / or firmware configured to receive data (e.g., requests and / or data) and provide data to the back end of the memory subsystem. The back end of the memory subsystem may include hardware and / or firmware to receive data (e.g., requests and / or data) from the front end of the memory subsystem and may include executing requests provided from the host on the memory devices of the memory subsystem.

[0023] As used herein, unless expressly indicated otherwise, the singular forms “a / an” and “the” include both singular and plural references. Furthermore, the word “may” is used throughout this application in a permissive sense (i.e., possible, able) rather than in a mandatory sense (i.e., must). The term “comprising” and its derivatives mean “including but not limited to”. The term “coupled” means a direct or indirect connection. It should be understood that data can be transmitted, received, or exchanged via electronic signals (e.g., current, voltage, etc.), and the phrase “signal indicating [data]” refers to the data itself being transmitted, received, or exchanged in a physical medium. A signal may correspond to a command (e.g., a read command, a write command, etc.).

[0024] The figures in this document follow a numbering rule, where the first one or more digits correspond to the figure number, and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. For example, 110 could represent... Figure 1 Component "10" in the text, and similar components can be found in the text. Figure 2 The symbol is represented as 210. Hyphens and additional numbers or letters can be used to represent similar elements within the symbol. See, for example... Figure 1Elements 102-1, 102-2, and 102-M are used in the drawings. Such similar elements can generally be represented without hyphens and additional numbers or letters. For example, elements 102-1, 102-2, and 102-M can be collectively referred to as 102. As used herein, the designations “N” and “M”, especially with respect to the reference numerals in the figures, indicate that several such specific features may be included. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or removed to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the invention and should not be construed as limiting.

[0025] Figure 1 This is a functional block diagram of a computing system 101 including a memory controller 100 according to several embodiments of the present disclosure. The memory controller 100 may include a front-end portion 104, a central controller portion 110, and a back-end portion 119. The computing system 101 may include a host 103 coupled to the memory controller 100 and memory devices 126-1, ..., 126-N. The memory controller 100 coupled to the host 103 may be discretely coupled to one or more of the memory devices 126-1, ..., 126-N.

[0026] The front-end portion 104 includes interfaces and interface management circuitry for coupling the memory controller 100 to the host 103 via input / output (I / O) channels 102-1, 102-2, ..., 102-M, and circuitry for managing the I / O channels 102. Any number of I / O channels 102 may be present, such as eight, sixteen, or another number. In some embodiments, the I / O channels 102 may be configured as a single port. In at least one embodiment, the interface between the memory controller 100 and the host 103 may be a PCIe physical and electrical interface operating according to the CXL protocol.

[0027] The central controller section 110 may include and / or be referred to as a data management circuitry. The central controller section 110 may control the execution of memory operations in response to a request received from the host 103. Examples of memory operations include memory access requests, such as a read operation to read data from the memory device 126 or a write operation to write data to the memory device 126.

[0028] The central controller portion 110 may include a hammer detection circuitry system 115. For example, in some embodiments, the central controller portion 110 may include a hammer detection circuitry system 115 that includes a first hammer detector and a second hammer detector. However, as detailed herein, in some embodiments, at least a portion of the hammer detection circuitry system 115 may be located elsewhere within the memory controller 100, for example, having at least a portion of the hammer detection circuitry system 115 located in the rear-end portion 119.

[0029] The central controller section 110 can generate error detection information and / or error correction information based on data received from the host 103. The central controller section 110 can perform error detection and / or error correction operations on data received from the host 103 or from the memory device 126. An example of an error detection operation is a Cyclic Redundancy Check (CRC) operation. CRC can be referred to as algebraic error detection. CRC may contain a check value generated using algebraic calculations performed on the data to be protected. CRC can detect accidental changes in data by comparing the check value stored in association with the data with a check value calculated based on the data. An example of an error correction operation is an Error Correction Code (ECC) operation. ECC encoding refers to encoding data by adding redundant bits. ECC decoding refers to examining ECC-encoded data to check for any errors in the data. Generally, ECC not only detects errors but also corrects a subset of the errors it can detect.

[0030] Back-end portion 119 may include a media controller and a physical (PHY) layer coupling memory controller 100 to memory device 126. As used herein, the term "PHY layer" generally refers to the physical layer in the Open Systems Interconnection (OSI) model of a computing system. The PHY layer may be the first (e.g., lowest) layer of the OSI model and may be used to transmit data via a physical data transmission medium. In some embodiments, the physical data transmission medium may include channels 125-1, ..., 125-N. Channel 125 may include a sixteen-pin data bus and a two-pin Data Mask Inversion (DMI) bus, as well as other possible buses. Back-end portion 119 may exchange (e.g., transmit or receive) data with memory device 126 via data pins and exchange error detection information, RAID information, and / or error correction information with memory device 126 via DMI pins. The exchange of error detection information and / or error correction information may occur simultaneously with data exchange.

[0031] An example of memory device 126 is a dynamic random access memory (DRAM) operating according to a protocol such as Low Power Double Data Rate (LPDDRx), which may be referred to herein as an LPDDRx DRAM device, LPDDRx memory, etc. The "x" in LPDDRx refers to any generation of the protocol (e.g., LPDDR5).

[0032] In some embodiments, the memory controller 100 may include a management unit 134 for initializing, configuring, and / or monitoring the characteristics of the memory controller 100. The management unit 134 may include an I / O bus for managing out-of-band data and / or commands, a management unit controller for executing instructions associated with initializing, configuring, and / or monitoring the characteristics of the memory controller, and a management unit memory for storing data associated with initializing, configuring, and / or monitoring the characteristics of the memory controller 100. As used herein, the term "out-of-band" generally refers to a transmission medium different from the primary transmission medium of the network. For example, out-of-band data and / or commands may be data and / or commands transmitted to the network using a different transmission medium than that used to transmit data within the network.

[0033] Figure 2 This is a functional block diagram of a memory controller 200 having a first configuration according to several embodiments of the present disclosure. For example... Figure 2 As shown, the front-end portion 204 may include: an interface 206 comprising a plurality of I / O channels 202-1, 202-2, ..., 202-M; and an interface management circuitry 208 for managing the interface 206. An example of the interface 206 is a Peripheral Component Interconnect High Speed ​​(PCIe) 5.0 interface. In some embodiments, the memory controller 200 may receive access requests via the interface 206 according to a nondeterministic memory protocol such as the CXL protocol, involving at least one of cache memory 212 and memory devices (e.g., dies) 226-1, 226-2, ..., 226-(N-1), 226-N. The interface 206 may receive access requests from the host (e.g., ...) via I / O channels 202. Figure 1 The host 103 shown receives data. The interface management circuitry 208 can use a nondeterministic protocol, such as the CXL protocol, to manage the interface 206 and may be referred to as the CXL interface management circuitry 208. The CXL interface management circuitry 208 may be coupled to the host via the PCIe interface 206.

[0034] Central controller 210 (also referred to herein as data management circuitry 210) may be coupled to interface management circuitry 208. Data management circuitry 210 may be configured to cause the execution of memory operations. Data management circuitry 210 may include at least one of error detection circuitry 211 (e.g., "CRC circuitry") and error correction circuitry 216. Error detection circuitry 211 may be configured to perform error detection operations on data. For example, error detection circuitry 211 may be configured to generate a checksum by algebraic calculation of data received from interface management circuitry 208 and transmit the checksum to at least one of cache memory 212, buffer 213, and media control circuitry 220. The checksum may be referred to as CRC data or error detection data.

[0035] In at least one embodiment, the error detection circuitry is configured to perform an error detection operation on data received from the interface management circuitry before the data is cached and / or manipulated by the error correction circuitry 216. Another example of the error detection operation is to generate a checksum by performing algebraic calculations on the data received from the media control circuitry, and to compare the checksum with a checksum received from the media control circuitry 220 to determine whether the data contains an error (e.g., whether the two checksums are not equal).

[0036] Data management circuitry system 210 may include cache memory (cache) 212 to store data, error detection information, error correction information, and / or metadata associated with the execution of memory operations. An example of cache memory 212 is a group-associated cache memory with thirty-two (32) paths comprising multiple cache lines. The cache line size may be equal to or greater than the access granularity of memory controller 200 (e.g., 64 bytes for the CXL protocol). For example, each cache line may contain 256 bytes of data. In another example, each cache line may contain 512 bytes of data. The size of read and write requests in the CXL memory system may be 64 bytes. Therefore, data items in cache memory 212 may have 64 bytes of data. Each cache line may include 256 bytes. Therefore, multiple 64-byte requests may be stored in each cache line. In response to a request from the host, memory controller 200 may write 256 bytes of data to memory device 226. In some embodiments, 256 bytes of data may be written into a 64-byte information block. Using cache memory 212 to store data associated with read or write operations increases the speed and / or efficiency of data access because cache memory 212 can prefetch data and store data in multiple 64-byte blocks if it is not in the cache. Instead of searching a separate memory device, data can be read from cache memory 212. Less time and energy are used to access prefetched data compared to the time and energy required when the memory system must search for data before accessing it.

[0037] The data management circuitry 210 may include a buffer 213 to store data, error detection information, error correction information, and / or metadata that are operated on by another component of the data management circuitry 210 (e.g., error detection circuitry 211, error correction circuitry 216, and low-power chip killer circuitry). The buffer 213 may allow temporary storage of information, for example, when the other component of the data management circuitry 210 is busy. In some embodiments, cache memory 212 may be used to temporarily store data, and buffer 213 may be used to temporarily store other information associated with the data, such as error detection information, error correction information, and / or metadata.

[0038] The data management circuitry may include a low-power chip kill (LPCK) circuitry (not specified). For example, the LPCK circuitry may be coupled between error detection circuitry 211 and error correction circuitry 216. The LPCK circuitry may be configured to perform a chip kill operation on the data. The term "chip kill" typically refers to protecting a memory system (e.g., Figure 1The memory system 101 shown is protected against errors in the form of faults in any single memory device 226 (chip) and multi-bit errors from any part of a single memory chip. The LPCK circuitry increases data stability and corrects for errors in the data. The LPCK circuitry can provide LPCK protection across a subset of memory devices 226 (e.g., to a first subset of memory devices 226-1, 226-2 and a second subset of memory devices 226-(N-1), 226-N individually) or across all memory devices 226 together.

[0039] An example chip-hunting implementation of a memory controller 200 comprising an eleven-channel 225 bus with a width of 176 bits coupled to eleven memory devices 226 may include eight memory devices for writing data to the eleven memory devices 226 and three memory devices for writing parity data to the eleven memory devices 226. Four codewords may be written, each consisting of eleven four-bit symbols, wherein each symbol belongs to a different memory device 226. A first codeword may include a first four-bit symbol of each memory device 226, a second codeword may include a second four-bit symbol of each memory device 226, a third codeword may include a third four-bit symbol of each memory device 226, and a fourth codeword may include a fourth four-bit symbol of each memory device 226.

[0040] Three parity symbols allow the LPCK circuitry to correct at most one symbol error and detect at most two symbol errors in each codeword. If only two parity symbols are added instead of three, the LPCK circuitry can correct at most one symbol error but detect only one. In some embodiments, data symbols and parity symbols can be written to or read from memory device 226 in parallel. If every bit symbol in the die fails, only the bit symbols from the memory device 226 in the codeword will fail. This allows memory contents to be reconstructed even if one memory device 226 fails completely. LPCK is considered "instantaneous correction" because data is corrected without impacting performance by performing a repair operation. The LPCK circuitry may include combinational logic using a feedforward process.

[0041] In contrast, a Redundant Array of Independent Disks (RAID) is considered a “check and recover correction” because it initiates a repair process to recover erroneous data. In some embodiments, the data management circuitry 210 includes a RAID circuitry (not shown). For example, the data management circuitry 210 may include a RAID circuitry instead of an LPCK circuitry. Depending on a particular implementation, the RAID circuitry may provide one or more of data mirroring, data parity checking, striping, and combinations thereof. The RAID circuitry may work in conjunction with the error detection circuitry 211 to provide check and recover correction, while the LPCK provides immediate correction. More specifically, the error detection circuitry may detect errors in the data, and the RAID circuitry may recover correct data in response. In at least one embodiment, the check and recover correction provided by the error detection circuitry 211 and the RAID circuitry complements the error correction provided by the error correction circuitry 216. For example, if data read from the memory device 226 has errors that the error correction circuitry 216 can correct, then the error correction circuitry can correct the errors without further data recovery by the RAID circuitry. However, if an error that the error correction circuitry 216 cannot correct still exists, the data can be recovered by the RAID circuitry. As another example, an error may escape detection by the error correction circuitry 216 but be detected by the error detection circuitry 211. In this example, the underlying data can be recovered by the RAID circuitry.

[0042] like Figure 2 As shown, the data management circuitry 210 may include error correction circuitry systems 216-1 and 216-2, which are configured to perform error correction operations on the data (e.g., ECC encoding and / or ECC decoding of the data). In embodiments that do not include cache 212 and buffer 213 (not specifically described), error correction circuitry system 216 may be coupled to error detection circuitry system 211.

[0043] Although two error correction circuits 216 are described, the embodiments are not limited thereto. Embodiments may include only one error correction circuit 216 or more than two error correction circuits 216 in the data management circuitry system 210. In at least one embodiment, the memory controller 200 may include an equal number of error correction circuits 216-1, 216-2 as media controllers 221-1, 221-2. Media controllers 221-1, 221-2 may each include a corresponding channel controller and a memory controller. For example, media controller 221-2 may include a channel controller 221-3 and a memory controller 221-4. In at least one embodiment, data may be protected by the error detection circuitry system 211, the LPCK circuitry system, and / or the error correction circuitry system 216 before being written to the memory device 226.

[0044] Data management circuitry 210 may include a cache memory 212 and a buffer 213 coupled between interface management circuitry 208 and error correction circuitry 216. The number of error detection circuits and / or error correction circuits may be equal to the number of PHY memory interfaces 224-1, 224-2, ..., 224-(N-1), 224-N. In such embodiments, the correlation between error correction circuits, error detection circuits, and memory devices is 1:1:1. However, if... Figure 2 Other configurations, such as those described herein, are possible.

[0045] In various embodiments, a controller coupled to one or more of several memory devices includes at least a first row hammer detector among a plurality of row hammer detectors. As used herein, a row hammer detector refers to hardware and / or software or other logic that permits the detection of row hammer events. In various embodiments, the row hammer detector may be included in or coupled to a register or storage device. For example, the row hammer detector may increment a row counter corresponding to a row address stored in a data structure in a register or storage device coupled to the controller containing the row hammer detector. Thus, the row hammer detector can determine when a target row experiences repeated access within a threshold time period.

[0046] The plurality of hammer detectors may include a first hammer detector and a second hammer detector. For example, the plurality of hammer detectors may include a total of two hammer detectors (e.g., a first hammer detector and a second hammer detector). However, the plurality of hammer detectors may include any number of hammer detectors. For example, the plurality of hammer detectors may include a total of three hammer detectors (a first hammer detector, a second hammer detector, and a third hammer detector), and other possibilities.

[0047] As detailed herein, each of the plurality of row hammer detectors is distinct from memory device 226 and is instead contained in central controller 210 located remotely from memory device 226. In some embodiments, the plurality of row hammer detectors distinct from memory device 226 includes a first row hammer detector and a second row hammer detector contained in memory controller 200. For example, in various embodiments, at least one row hammer detector is contained in central controller 210, channel controllers 221-3, memory controllers 221-4, or combinations thereof, as detailed herein.

[0048] For example, such as Figure 2 As described herein, the hammer detection circuit system 215 may include, for example, a first hammer detector (such as...). Figure 2 A row hammer detector (identified by "RHD1") may be located in the central controller 210 of the memory controller 200. That is, in various embodiments, at least a first row hammer detector is included in the central controller 210. Including at least a first row hammer detector in the central controller 210 can reduce the number of events, but increase the rate at which detection must be performed within a given time period. For example, the number of events elsewhere (outside the central controller 210) may be higher, at least in part, due to the number of channels (e.g., 16 channels) and / or the number of memory units involved in the events; however, the given rate at which detection must be performed may be relatively low and correspond to a given portion of the events in a particular channel / memory unit. Therefore, in some embodiments, it may be necessary to use a first row hammer detector located at the central controller 210 for initial detection of row hammer events, and then provide subsequent row hammer detection of the media controller 221-1 in, for example, the channel controller 221-3 and / or the memory controller 221-4. In this manner, rapid initial detection of potential row hammer events can be achieved by a first row hammer detector (RHD1) located at the central controller 210 and subsequently confirmed by a second row hammer detector (RHD2) located in a component of the media controller 221-2 (e.g., channel controller 221-3 or memory controller 221-4), promoting timely, effective, and accurate row hammer detection compared to other methods employing individual row hammer detectors. However, the first and / or second row hammer detectors may be located elsewhere in the memory controller 200. For example, the first row hammer detector (RHD1) may be included in the central controller 210, channel controller 221-3, or memory controller 221-4. Similarly, the second row hammer detector (RHD2) may be included in the central controller 210, channel controller 221-3, or memory controller 221-4. For example, in some embodiments, the first row hammer detector is included in the central controller 210 and the second row hammer detector is included in the channel controller 221-3, such as... Figure 2As described in the document. However, in some embodiments, the first hammer detector is included in the central controller 210 and the second hammer detector is included in the storage controller 221-4.

[0049] In some embodiments, the first and second row hammer detectors may each be located in a central controller 210 between the interface management circuitry 208 and the physical interface 224 configured to couple to a memory device. In some embodiments, at least the first row hammer detector is included in a channel controller 221-3. For example, the first row hammer detector may be included in the channel controller 221-3 and the second row hammer detector may be included in the memory controller 221-4.

[0050] although Figure 2 The first hammer detector is described as being contained in a different controller than the second hammer detector, but other configurations are possible. For example, in some embodiments, each of the first and second hammer detectors may be located in a central controller 210 or in a media controller 221-2 (e.g., in a channel controller 221-3 or a memory controller 221-4). For example, in various embodiments, each of the first and second hammer detectors may be located in a central controller 210.

[0051] like Figure 2 As shown, the memory controller 200 may include a back-end portion 219, which includes a media control circuitry 220 coupled to the data management circuitry 210. The media control circuitry 220 may include media controllers 221-1 and 221-2. The back-end portion 219 may include a physical (PHY) layer 222 having PHY memory interfaces 224-1, 224-2, ..., 224-(N-1), 224-N. Each physical interface 224 is configured to couple to a corresponding memory device 226.

[0052] PHY layer 222 may be a memory interface configured for deterministic memory protocols, such as an LPDDRx memory interface. Each of the PHY memory interfaces 224 may include corresponding data pins 227 and DMI pins 229. For example, each PHY memory interface 224 may include sixteen data pins 227 "[15:0]" and two DMI pins 229 "[1:0]". Media control circuitry 220 may be configured to exchange data with the corresponding memory device 226 via data pins 227. Media control circuitry 220 may be configured to exchange error correction information, error detection information, and / or metadata via DMI pins 229, rather than via data pins 227. DMI pins 229 can provide several functions, such as data masking, data bus transposition, and parity checking for read operations, by setting a mode register. The DMI bus uses bidirectional signaling. In some cases, each transmitted byte of data has a corresponding signal sent via DMI pins 229 for data selection. In at least one embodiment, data can be exchanged simultaneously with error correction information, RAID information, and / or error detection information. For example, 64 bytes of data can be exchanged (transmitted or received) via data pin 227, while 35 bits of error detection information (and metadata) and 21 bits of error correction information are exchanged via DMI pin 229. Such embodiments reduce the overhead on the DQ bus for transmitting error correction information, error detection information, and / or metadata.

[0053] The back-end portion 219 can couple the PHY layer portion 222 to the memory banks 230-1, 230-2, ..., 230-(N-1), 230-N of the memory devices 226-1, 226-2, ..., 226-(N-1), 226-N. Each memory device 226 includes at least one memory cell array. In some embodiments, the memory devices 226 may be different types of memory. The media control circuitry system 220 can be configured to control at least two different types of memory. For example, memory devices 226-1, 226-2 may be LPDDRx memory operating according to a first protocol, and memory devices 226-(N-1), 226-N may be LPDDRx memory operating according to a second protocol different from the first protocol. In this example, media controller 221-1 may be configured to control a first subset of memory devices 226-1 and 226-2 according to a first protocol, and media controller 221-2 may be configured to control a second subset of memory devices 226-(N-1) and 226-N according to a second protocol. In a particular example, memory devices 226-1 and 226-2 may have an onboard error correction circuitry system. Although not specifically described, for some embodiments, media control circuitry system 220 may comprise a single media controller 221.

[0054] As used herein, the term "substantially" means that a characteristic does not need to be absolute, but is close enough to achieve the advantages of the characteristic. For example, "substantially simultaneous" is not limited to operations that are performed absolutely simultaneously and can include timing that is intended to be simultaneous but may not be exactly simultaneous due to manufacturing limitations. For example, due to read / write latency that can be manifested by various interfaces (e.g., LPDDR5 versus PCIe), media controllers utilized "substantially simultaneously" may not start or end precisely at the same time. For example, memory controllers can be used such that they write data to memory devices at the same time regardless of whether one of the media controllers starts or terminates before the others.

[0055] The memory controller 200 may include a management unit 234 configured to initialize, configure, and / or monitor the characteristics of the memory controller 200. In some embodiments, the management unit 234 includes a system management (SM) bus 238. The SM bus 238 may manage out-of-band data and / or commands. The SM bus 238 may be a serial presence detection portion. In some embodiments, the SM bus 238 may be a single-ended simple two-wire bus for lightweight communication purposes. The management unit 234 may include a CPU subsystem 240 that may act as a controller for the management unit to execute instructions associated with initializing, configuring, and / or monitoring the characteristics of the memory controller 200. The management unit 234 may include a hybrid circuit system 242, such as local memory storing code and / or data associated with managing and / or monitoring the characteristics of the memory controller 200. The endpoints of the management unit 234 may be exposed to a host system (e.g., Figure 1 The host 103 shown in the diagram manages data. In some embodiments, the characteristics monitored by the management unit 234 may include the voltage supplied to the memory controller 200 and / or the temperature measured by an external sensor. The management unit 234 may include interconnects 236, such as an Advanced High Performance Bus (AHB), to couple different components of the management unit 234.

[0056] Management unit 234 may include circuitry for managing in-band data (e.g., data transmitted via a primary transmission medium within a network, such as a local area network (LAN)). In some embodiments, CPU subsystem 240 may be compliant with Joint Test Action Group (JTAG) standards and based on internal integrated circuits (I... 2 C or I 3 C) Controllers for protocol and auxiliary I / O circuitry system operation. JTAG typically refers to an industry standard used for post-manufacturing verification and testing of printed circuit system boards. 2C typically refers to a serial protocol used for two-wire interfaces to connect low-speed devices such as microcontrollers, I / O interfaces, and other similar peripherals in embedded systems. In some embodiments, an auxiliary I / O circuitry may couple the management unit 234 to the memory controller 200. Furthermore, firmware for operating the management unit may be stored in the hybrid circuitry 242. In some embodiments, the hybrid circuitry 242 may be a flash memory, such as flash NOR memory or other persistent flash memory devices.

[0057] Figure 3 This is a functional block diagram of a memory controller 300 with a second configuration according to several embodiments of the present disclosure. Figure 3 Similar to Figure 2 The difference is that the location of the second hammer detector (RHD2) in the hammer detection circuit system 315 is contained in the central controller 310 instead of the media controller 321-2, and the additional circuit system in the form of the safety engine 314 exists in the central controller 310.

[0058] The security engine 314 may also be referred to as an encryption circuit system 314. The encryption circuit system 314 may be configured to encrypt data before storing it in the memory device 326 or cache memory 312 and / or decrypt it after reading encrypted data from the memory device 326 or cache memory 312. An example of the encryption circuit system 314 is an Advanced Encryption Standard (AES) circuit system. However, in some embodiments, an encryption circuit system may be omitted (e.g., similar to...). Figure 2 In the case of ), a memory controller 300 is provided.

[0059] As mentioned, the memory controller 300 may include a front-end section 304, a data management circuitry system 310, and a back-end section 319. The front-end section 304 may include: an interface 306 having multiple I / O channels 302-1, 302-2, ..., 302-M; and an interface management circuitry system 308 for managing the interface 306.

[0060] As mentioned, the data management circuitry 310 may include a cache memory (cache) 312 and a buffer 313 coupled between the error detection circuitry 311 and the error correction circuitry 316-1, 316-2. In some embodiments, the cache 312 is a set-associative cache, such as a set-associative cache memory with thirty-two (32) paths comprising a plurality of cache lines. The cache line size of the cache 312 may be equal to or greater than the access granularity of the memory controller 300 (e.g., 64 bytes for the CXL protocol). Thus, the size of each of the plurality of cache lines may be equal to or greater than the memory controller access granularity. For example, each cache line may contain 256 bytes of data, and other possibilities exist. In another instance, each cache line may contain 512 bytes of data.

[0061] The back-end portion 319 may include a media control circuitry system 320 and a PHY layer 322. The media control circuitry system 320 may include media controllers 321-1 and 321-2. The PHY layer 322 may include PHY memory interfaces 324-1, 324-2, ..., 324-(N-1), 324-N, configured to be coupled via channels 325-1, 325-2, ..., 325-(N-1), 325-N to memory banks 330-1, 330-2, ..., 330-(N-1), 330-N of memory devices 326-1, 326-2, ..., 326-(N-1), 326-N. Each of the PHY memory interfaces 324 may include a corresponding data pin 327 and a DMI pin 329. The memory controller 300 may include a management unit 334, which includes interconnects 336, an SM bus 338, a CPU subsystem 340, and a hybrid circuit system 342.

[0062] Figure 4 This is a functional flowchart 431 for several embodiments of this disclosure. At 432-1, a line activation command can be received. For example, an interface (e.g., such as...) Figure 2 The interface 206 described herein can be accessed via I / O channels (e.g., such as...) Figure 2 The I / O channel 202 described herein receives data from the host (e.g., receives a first signal indicating data associated with a memory access request). The signal may be transmitted to a controller, such as a central controller (e.g., as...). Figure 2 The central controller 210 described herein may be received by or intercepted by the controller. That is, the row activation command may be received by or intercepted by the controller. In some embodiments, the signal may be received or intercepted by the row hammer detector included in the row hammer detection circuit system 215.

[0063] At 432-2, row hammer detection can be performed using a first row hammer detector among multiple row hammer detectors located on the memory controller. For example, the first row hammer (RH) detector can perform row hammer detection by incrementing a row counter corresponding to a row address stored in a register or other memory device of a first data structure of the first row hammer detector. At 432-3, the incremented row counter can be compared with a row hammer threshold, such as a first row hammer threshold of the first row hammer detector. The comparison between the incremented row counter and the row hammer threshold allows determination of when the incremented row counter is less than, equal to, or greater than the row hammer threshold.

[0064] In response to determining that the incrementing row counter is less than the row hammer threshold, process 431 can proceed to 432-4. At 432-4, memory operations can be performed. For example, a signal indicating data can be transmitted to a cache and / or to a memory device. In this way, the host can perform memory operations (e.g., memory access requests) associated with cache 412 and / or die 426.

[0065] In response to determining that the incrementing row counter is greater than (or equal to) the row hammer threshold, process 431 may proceed to 432-5. At 432-5, a command to mitigate the row hammer may be issued. The command to mitigate the row hammer may be issued to the host, a portion of the memory controller, and / or the memory device.

[0066] Examples of commands that mitigate row hammer include performing refresh operations, such as refreshing the row address of the row activation command and / or one or more row addresses adjacent to the row activation command; changing the refresh mode / timing; sending "bad" / "toxic" data back to the host; causing an interrupt, such as an interrupt at the host; and / or providing a notification, such as a notification to the controller, and other potentially related commands. In any case, commands that mitigate row hammer can mitigate any effects associated with row hammer (e.g., charge leakage, data corruption, power consumption, computational burden, etc.).

[0067] For example, a command at the memory controller can cause a second row hammer detector, included among multiple row hammer detectors, to subsequently (after the first row hammer detector) perform row hammer detection. As mentioned, the second row hammer detector can be a different type of row hammer detector and / or can be located in a portion of the memory controller different from the first row hammer detector.

[0068] For example, the type of the first hammer detector may differ from the type of the second hammer detector. In some embodiments, the first hammer detector may contain a first type of probabilistic data structure and the second hammer detector may contain a second type of probabilistic data structure, different from the first type. For example, the first type of probabilistic data structure may be a Bloom filter and the second type of probabilistic data structure may be a minimum count filter. Using a Bloom filter as the first type of filter makes it easy to "filter" possible hammer events and avoid any missed detections. However, other types of filters, such as cuckoo filters, vacuum filters, etc., are possible.

[0069] As mentioned, a first filter (e.g., a Bloom filter) of the first hammer detector can act as an initial "screening" of possible hammer events, and a second filter (e.g., a minimum count filter) of the second hammer detector, which operates at a slower rate but has improved accuracy and / or filters a larger number of events, can be used to verify possible hammer events. That is, the first hammer detector can operate at a first rate (e.g., a given number of events per time interval) and the second hammer detector can operate at a second rate different from the first rate. For example, the first rate of the first hammer detector can be greater than the second rate of the second hammer detector. In this way, the first hammer detector can quickly "screen" possible hammer events, while the second hammer detector can accurately verify whether a possible hammer event is an actual hammer event (e.g., a normal memory access).

[0070] In some embodiments, a first row hammer detector may occupy a first amount of storage in the memory controller, and a second row hammer detector may occupy a second amount of storage in the memory controller that differs from the first amount. The difference in storage may be at least partially attributable to any difference between row hammer detectors of the corresponding type and / or row hammer detectors that process different amounts of events (e.g., data structures / tables of different sizes). For example, the data table of the first row hammer detector may be of a different size and / or a different type compared to the data table of the second row hammer detector. In some embodiments, the first row hammer detector may occupy a first amount of storage in the memory controller that is smaller than the second amount of storage occupied by the second row hammer detector in the memory controller, and other possibilities exist.

[0071] In some embodiments, the memory controller may store, for example, a single-port SRAM that stores a first data structure for the first row hammer detector, a second data structure for the second row hammer detector, or both. It is noteworthy that, compared to other methods that rely on the presence of a large CAM, the method described herein can utilize less storage, such as less than 2.5 megabytes of single-port SRAM, while still providing enhanced row hammer detection, as detailed herein.

[0072] At 432-5, row hammer detection can be performed using a second row hammer detector among multiple row hammer detectors located on the memory controller. For example, the second row hammer (RH) detector can be used to perform row hammer detection by incrementing a row counter corresponding to the row address stored in a second data structure of the second row hammer detector. At 432-6, the incremented row counter of the second row hammer detector can be compared with a row hammer threshold, such as the second row hammer threshold (SRHT) of the second row hammer detector.

[0073] In response to determining that the incrementing row counter is less than the second row hammer threshold, process 431 may proceed to 432-7. The second row hammer threshold may be the same as or different from the first row hammer threshold. For example, the second row hammer threshold may be different from the first row hammer detector (e.g., type, location, etc.) when it is different from the second row hammer detector. At 432-7, memory operations may be performed, as detailed herein.

[0074] In response to determining that the incrementing row counter is greater than (or equal to) the second row hammer threshold, process 431 may proceed to 432-8. At 432-8, a subsequent command (following the command issued at 432-5) may be issued to mitigate the row hammer. As mentioned, example commands for mitigating row hammer include commands associated with performing a refresh operation, changing the refresh mode / timing, sending “bad” / “toxic” data back to the host, causing an interrupt and / or providing a notification, and other possible commands.

[0075] Figure 5 This is a flowchart of a method for row hammer mitigation using a hierarchical detector, according to several embodiments of this disclosure. The methods described herein (e.g., regarding...) Figure 5 The process can be executed by processing logic that includes hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0076] At 550, the method may include a memory controller receiving an indication of having a memory device (e.g., such as...). Figure 1The method may involve signaling a row activation command for a row address in the memory device 126 described herein. For example, the method may include receiving signaling indicating a row activation command from a host via a CXL interface management circuitry of the memory controller. In some embodiments, the row activation command may be received at a central controller of the memory controller. For example, the controller, such as the central controller, may intercept the activation command (e.g., the activation command).

[0077] At position 552, the row counter corresponding to the row address can be incremented. The row counter can be incremented by a predetermined amount. For example, the row counter can be incremented by one or by a value greater than one. For example, the row counter can be incremented by one whenever the memory subsystem receives an access command with a row address. In some embodiments, the row counter corresponding to the row address in the data structure of the first row hammer detector among a plurality of row hammer detectors can be incremented.

[0078] The row counter can be stored in a data structure of the memory subsystem. In some embodiments, the data structure can be a probabilistic data structure. Examples of probabilistic data structures include Bloom filters and minimum count filters, as well as other possibilities. The data structure can be stored in the memory controller. For example, the data structure can be stored in the same part of the memory controller as the given row hammer detector that utilizes the data structure, as well as other possibilities. That is, the given row hammer detector can contain a corresponding data structure contained in or coupled to a register or storage device of the given row hammer detector.

[0079] At position 554, it can be determined whether the row counter is greater than the row hammer threshold (RHT), such as the first row hammer threshold of the first row hammer detector. This determination can be made at the controller of the memory subsystem, for example, at the controller that includes the first row hammer detector.

[0080] At position 556, in response to determining that the row counter is greater than the RHT, a command to mitigate the row hammer can be issued. For example, a flush command can be issued to the row address and / or other row addresses, such as to a row that is physically adjacent to the row address. However, other mitigation mechanisms, such as those detailed herein, are possible. Conversely, determining that the row counter is less than (or equal to) the RHT can indicate that there is no negative impact on processing the access command and that the access command can be permitted.

[0081] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of one or more embodiments of this disclosure. It should be understood that the above description has been carried out illustratively and not restrictively. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of one or more embodiments of this disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of this disclosure should be determined with reference to the appended claims together with the full scope of the equivalents given by such claims.

[0082] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than expressly stated in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim exists as a separate embodiment in itself.

Claims

1. A device for mitigating a line hammer using a layered detector, comprising: Several memory devices; and A memory controller coupled to one or more of the plurality of memory devices, the memory controller including an interface management circuitry and a first row hammer detector; as well as Second row hammer detector; And the memory controller is configured to: Receive signaling indicating the line activation command and the line address; Increment the row counter corresponding to the row address stored in the data structure of the first row hammer detector coupled to the memory controller; Determine that the incrementing row counter is greater than the first row hammer threshold; as well as In response to determining that the incrementing row counter is greater than the first row hammer threshold, a row hammer mitigation command is issued to perform row hammer detection using the second row hammer detector.

2. The device of claim 1, wherein the memory controller further comprises a central controller, a channel controller, a memory controller, or a combination thereof.

3. The device of claim 2, wherein the memory controller further includes a row hammer detection circuit system, the row hammer detection circuit system comprising a plurality of row hammer detectors, and wherein the plurality of row hammer detectors comprises at least three row hammer detectors.

4. The device of claim 3, wherein at least the first row hammer detector is included in the central controller.

5. The device of claim 4, wherein the second row hammer detector is included in the channel controller.

6. The device of claim 4, wherein the second row hammer detector is included in the storage controller.

7. The device of claim 4, wherein the second row hammer detector is included in the central controller.

8. The device of claim 2, wherein at least the first row hammer detector is included in the channel controller, and wherein the second row hammer detector is included in the memory controller.

9. A method for mitigating row hammers using a hierarchical detector, comprising: The interface management circuitry of the memory controller of the memory subsystem receives signaling indicating a row activation command with a row address, wherein the interface management circuitry is configured to use a nondeterministic memory protocol. The row counter corresponding to the row address stored in the data structure of the first row hammer detector, which is included in the memory controller, is incremented; At the memory controller, it is determined whether the incrementing row counter is greater than the first row hammer threshold of the first row hammer detector; as well as In response to determining that the incrementing row counter is greater than the first row hammer threshold, a row hammer mitigation command is issued to the second row hammer detector to perform row hammer detection using the second row hammer detector.

10. The method of claim 9, wherein issuing the hammer mitigation command further comprises issuing a command to initiate hammer detection using a third hammer detector included in the plurality of hammer detectors.

11. The method of claim 10, wherein the type of the first row hammer detector is different from the type of the second row hammer detector.

12. The method of claim 11, wherein the first row hammer detector occupies a first storage amount in the memory controller and the second row hammer detector occupies a second storage amount in the memory controller that is different from the first storage amount, and wherein the first storage amount is less than the second storage amount.

13. The method of claim 10, wherein performing the row hammer detection using the second row hammer detector further comprises: Increment the row counter corresponding to the row address in the data structure stored in the second row hammer detector; At the memory controller, it is determined whether the incrementing row counter is greater than the second row hammer threshold; as well as In response to determining that the incrementing row counter is greater than the second row hammer threshold, a subsequent row hammer mitigation command is issued to mitigate the row hammer.

14. A memory controller for row hammer mitigation using a stratification detector, comprising: An interface management circuit system is configured to use a nondeterministic memory protocol; First row of hammer detectors; as well as The second row hammer detector; and wherein the memory controller is configured to: The interface management circuitry system receives a signaling instruction indicating a row activation command having a row address in the memory device. Increment the row counter corresponding to the row address stored in the first data structure of the first row hammer detector; Determine when the incrementing row counter exceeds the first row hammer threshold of the first row hammer detector; as well as In response to determining that the incrementing row counter is greater than the first row hammer threshold, a row hammer mitigation command is issued to perform row hammer detection using the second row hammer detector.

15. The memory controller of claim 14, wherein the second row hammer detector is configured to: Increment the second row counter corresponding to the row address stored in the second data structure of the second row hammer detector; Determine that the incrementing second row counter is greater than the second row hammer threshold; and In response to determining that the incrementing second row counter is greater than the second row hammer threshold, a subsequent row hammer relief command is issued to relieve the row hammer.

16. The memory controller of claim 15, wherein the subsequent row hammer relief command is a refresh command, and wherein the first row hammer detector and the second row hammer detector are each located between the interface management circuitry and a physical interface configured to be coupled to a memory device.

17. The memory controller according to claim 15, wherein: The first hammer detector contains a probabilistic data structure of the first type; and The second row hammer detector contains a second type of probabilistic data structure.

18. The memory controller of claim 17, wherein the first type of probabilistic data structure is a Bloom filter, and wherein the second type of probabilistic data structure is a minimum count filter.

19. The memory controller of claim 18, wherein the memory device is without a row hammer detector.

20. The memory controller of claim 18, wherein the first row hammer detector is configured to operate at a first rate and the second row hammer detector is configured to operate at a second rate different from the first rate.

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