Memory devices and their operation methods

Abstract

This disclosure relates to a memory device and a method of operating the same, the memory device comprising: a plurality of memory cells connected to a plurality of word lines; peripheral circuitry configured to perform programming operations that store data in the plurality of memory cells; a weak word line information storage unit configured to store information about weak word lines among the plurality of word lines; and a programming operation controller configured to control the peripheral circuitry such that, based on a result of determining whether a selected word line corresponding to an address provided from a memory controller is a weak word line by comparing word lines based on information about weak word lines, a programming operation is performed in a first programming mode or a second programming mode.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to electronic devices, and more specifically, to a memory device and a method of operating the memory device. Background Technology

[0002] A memory system is a device that stores data under the control of a host device such as a computer or smartphone. A memory system may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices or non-volatile memory devices.

[0003] In non-volatile memory devices, stored data is retained even when power is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory.

[0004] Non-volatile memory devices include memory cells that store data. The data stored in a memory cell can be separated based on the degree of increase in the threshold voltage of the memory cell. In a three-dimensional (3D) memory cell structure, the characteristics of the memory cells may differ depending on their location. When the characteristics of the memory cells differ, even if the same voltage is applied to the memory cells, the degree of increase in their threshold voltage may also differ. Therefore, the magnitude and timing of the voltage applied during programming operations that store data in the memory cells can be set differently depending on the characteristics of the memory cells. Summary of the Invention

[0005] Various embodiments of this disclosure relate to a memory device capable of improving the threshold voltage distribution of memory cells during programming operations and a method of operating the memory device.

[0006] An embodiment of the memory device according to this disclosure may include: a plurality of memory cells connected to a plurality of word lines; peripheral circuitry configured to perform a word line test operation to determine weak word lines among the plurality of word lines; and a weak word line determiner. The weak word line determiner may be configured to control the peripheral circuitry such that, during the word line test operation, a result obtained by comparing the number of first cutoff cells identified by a first pre-programming operation with the number of second cutoff cells identified by a second pre-programming operation is stored in any one of the memory blocks. The first pre-programming operation is an operation of applying a pre-charge voltage to a source line commonly connected to the plurality of memory cells, and subsequently applying a pre-programming voltage to a selected word line among the plurality of word lines. The second pre-programming operation is an operation of applying a ground voltage to a source line, and subsequently applying a pre-programming voltage to the selected word line.

[0007] An embodiment of the memory device according to this disclosure may include: a plurality of memory cells connected to a plurality of word lines; peripheral circuitry configured to perform programming operations that store data in the plurality of memory cells; a weak word line information storage unit configured to store information about weak word lines among the plurality of word lines; and a programming operation controller. The programming operation controller may be configured to control the peripheral circuitry such that, by comparing word lines based on information about weak word lines, a programming operation is performed in a first programming mode or a second programming mode based on a result determining whether a selected word line corresponding to an address provided from a memory controller is a weak word line. The information about weak word lines includes information determined by comparing a first pre-programming operation with a second pre-programming operation, wherein the first pre-programming operation is an operation of applying a pre-charge voltage to a source line commonly connected to the plurality of memory cells and increasing the threshold voltage of the plurality of memory cells, and the second pre-programming operation is an operation of applying a ground voltage to the source line and increasing the threshold voltage of the plurality of memory cells.

[0008] A method for operating a memory device according to this disclosure may include the steps of: determining whether a selected word line is a weak word line by comparing a selected word line corresponding to an address provided from a memory controller with the weak word line based on information about weak word lines. The method may further include the steps of: determining a programming mode, based on the comparison result, either a first programming mode or a second programming mode, and performing a programming operation to store data in selected memory cells connected to the selected word line based on the programming mode. The information about weak word lines includes information determined by comparing a first pre-programming operation with a second pre-programming operation, wherein the first pre-programming operation applies a pre-charge voltage to a source line commonly connected to a plurality of memory cells and increases the threshold voltage of the plurality of memory cells, and the second pre-programming operation applies a ground voltage to the source line and increases the threshold voltage of the plurality of memory cells. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 It is shown Figure 1 A block diagram of the structure of the memory device.

[0011] Figure 3 It is shown Figure 2 A diagram of the structure of any one of the multiple storage blocks.

[0012] Figure 4 It is a graph showing the threshold voltage distribution of memory cells according to the programming operation of the memory device.

[0013] Figure 5This is a diagram illustrating the programming operations of a memory device.

[0014] Figure 6 This is a diagram illustrating the operation of a weak character line determiner according to an embodiment of the present disclosure.

[0015] Figure 7 This is a diagram illustrating the operation of determining weak word lines according to an embodiment of the present disclosure.

[0016] Figure 8 This is a diagram showing information about weak letter lines.

[0017] Figure 9 This is a diagram illustrating a first implementation of programming operations performed in a first programming mode or a second programming mode.

[0018] Figure 10 This is a diagram illustrating a second implementation of the programming operations performed in the first programming mode.

[0019] Figure 11 This is a diagram illustrating a second implementation of programming operations performed in a second programming mode.

[0020] Figure 12 This is a diagram illustrating a third implementation of the programming operations performed in the first programming mode.

[0021] Figure 13 This is a diagram illustrating a third implementation of programming operations performed in the second programming mode.

[0022] Figure 14 This is a diagram illustrating a fourth embodiment of programming operations performed in a first programming mode or a second programming mode.

[0023] Figure 15 This is a diagram illustrating a fifth embodiment of programming operations performed in a first programming mode or a second programming mode.

[0024] Figure 16 This is a flowchart illustrating a word line test operation for determining weak word lines according to an embodiment of the present disclosure.

[0025] Figure 17 This is a flowchart illustrating the programming operations of a memory device according to an embodiment of the present disclosure.

[0026] Figure 18 This is a block diagram illustrating a memory card system to which a memory system according to an embodiment of the present disclosure is applied.

[0027] Figure 19 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0028] The specific structural or functional descriptions of the embodiments of this disclosure described in this specification or application are provided as examples to illustrate implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be practiced in various forms and should not be construed as limited to the implementations described in this specification or application.

[0029] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a device for storing data under the control of a host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0031] Depending on the host interface used for communication with host 300, memory system 50 can be manufactured as any of various types of storage devices. For example, memory system 50 can be implemented as any of various types of storage devices, such as solid-state drives (SSDs), multimedia cards such as MMC, embedded MMC (eMMC), reduced-size MMC (RS-MMC) or micro-MMC, secure digital cards such as SD, mini-SD or micro-SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, compact flash memory (CF) cards, smart media cards, and memory sticks.

[0032] The memory system 50 can be manufactured in any of a variety of package types. For example, the memory system 50 can be manufactured in any of a variety of package types such as POP, SIP, SOC, MCP, COB, WFP, and WSP.

[0033] The memory device 100 can store data. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown), which includes a plurality of memory cells for storing data.

[0034] Each memory cell can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0035] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or a unit for reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0036] In embodiments, the memory of memory device 100 may be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory device, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). For ease of description, this specification assumes that memory device 100 uses NAND flash memory.

[0037] The memory device 100 can receive commands and addresses from the memory controller 200 and can access address-selected regions in the memory cell array. The memory device 100 can perform operations indicated by commands on the address-selected regions. For example, the memory device 100 can perform write operations (i.e., programming operations), read operations, and erase operations. During a write operation, the memory device 100 can program data into the address-selected regions. During a read operation, the memory device 100 can read data from the address-selected regions. During an erase operation, the memory device 100 can erase data stored in the address-selected regions.

[0038] In one embodiment, the memory device 100 may include a weak word line determiner 140 and a programming operation controller 150.

[0039] The weak word line determiner 140 determines the characteristics of each word line connected to a memory cell. Memory cells may have different characteristics depending on their manufacturing process. Furthermore, in a 3D memory cell structure, the characteristics of memory cells may differ depending on their location. Depending on the characteristics of the memory cells, the degree to which the voltage applied to the word line affects them may differ. Specifically, the degree to which the threshold voltage of a memory cell changes due to the voltage applied to the word line may differ. In an embodiment, the weak word line determiner 140 may determine the word line of a memory cell connected to a memory cell with a high degree of threshold voltage change as a weak word line. For example, during programming operations, the increase in threshold voltage of a memory cell connected to a weak word line may be greater than the increase in threshold voltage of memory cells connected to other word lines. The weak word line determiner 140 may store information about each weak word line among multiple word lines (i.e., weak word line information), which is information obtained by determining each weak word line. Detailed operation of the weak word line determiner 140 will be described later. Figure 6 and Figure 7 To describe.

[0040] The programming operation controller 150 controls programming operations performed on memory cells. A programming operation can be an operation that stores data in a memory cell. Specifically, a programming operation can be an operation that increases the threshold voltage of a memory cell based on the data to be stored in the memory cell. When a programming operation is performed, each memory cell can have a threshold voltage corresponding to any of a plurality of programming states. The plurality of programming states can be defined based on the number of data bits stored in a memory cell. For example, when programming data according to a three-level cell (TLC) scheme where three bits are stored in a memory cell, the plurality of programming states can indicate an erase state and first to seventh programming states. After performing a programming operation, the threshold voltage of the memory cell can be determined based on the data to be stored in the memory cell. Based on the data to be stored in the corresponding memory cell, each memory cell can have any of a plurality of programming states as the target programming state.

[0041] In this implementation, the programming operation may include multiple programming cycles. Each programming cycle may include a programming voltage application operation and a verification operation. The programming voltage application operation may be an operation of increasing the threshold voltage of the memory cell using a programming voltage. The verification operation may be an operation of using a verification voltage to identify whether the threshold voltage of the memory cell has reached the threshold voltage corresponding to the target programming state.

[0042] In this implementation, the programming operation controller 150 can perform a programming operation in either a first programming mode or a second programming mode based on weak word line information. The magnitude of the voltage applied during the programming operation can differ between the first and second programming modes. In this example, when the word line corresponding to the address input from the memory controller 200 is a weak word line, the programming operation controller 150 can perform the programming operation in the first programming mode. In this example, when the word line corresponding to the address input from the memory controller 200 is a normal word line, the programming operation controller 150 can perform the programming operation in the second programming mode.

[0043] The storage controller 200 controls the overall operation of the storage system 50.

[0044] When power is applied to the memory system 50, the memory controller 200 can run firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300, a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0045] In this embodiment, the storage controller 200 may receive data and logical block addresses (LBAs) from the host 300, and may convert the logical block addresses (LBAs) into physical block addresses (PBAs) that indicate the addresses of memory cells included in the memory device 100 and for which data is to be stored. In this specification, the terms "logical block address (LBA)" and "logical address" are used interchangeably. In this specification, the terms "physical block address (PBA)" and "physical address" are used interchangeably.

[0046] The storage controller 200 can control the storage device 100 to perform write, read, or erase operations in response to a request received from the host 300. During a write operation, the storage controller 200 can provide a write command, a physical block address, and data to the storage device 100. During a read operation, the storage controller 200 can provide a read command and a physical block address to the storage device 100. During an erase operation, the storage controller 200 can provide an erase command and a physical block address to the storage device 100.

[0047] In this implementation, the storage controller 200 may internally generate commands, addresses, and data regardless of whether a request is received from the host 300, and may send these commands, addresses, and data to the storage device 100. For example, the storage controller 200 may provide the storage device 100 with the necessary commands, addresses, and data to perform read and write operations involved in the execution of wear leveling, read recycling, garbage collection, etc.

[0048] In one implementation, the memory controller 200 may control two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme may be a scheme for controlling the memory devices 100 such that the operation of at least two memory devices 100 overlaps with each other.

[0049] The host 300 may communicate with the memory system 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Loaded DIMM (LRDIMM).

[0050] In an implementation, memory system 50 may include buffer memory (not shown). For example, buffer memory may temporarily store data received from host 300 or memory device 100, or may temporarily store metadata of memory device 100 (e.g., a mapping table). Buffer memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0051] Figure 2 It is shown Figure 1 A diagram showing the structure of the memory device 100.

[0052] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0053] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to address decoder 121 via row lines RL. Memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLm. Each of memory blocks BLK1 to BLKz may include multiple memory cells. In embodiments, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells are defined as a physical page. In other words, memory cell array 110 may include multiple pages. In embodiments of this disclosure, each of the memory blocks BLK1 to BLKz included in memory cell array 110 may include multiple dummy cells. For a dummy cell, one or more dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0054] Each memory cell of the memory device 100 can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0055] Peripheral circuitry 120 can drive memory cell array 110. In this example, under the control of control logic 130, peripheral circuitry 120 can drive memory cell array 110 to perform programming, reading, and erasing operations. In this example, under the control of control logic 130, peripheral circuitry 120 can apply various operating voltages to row lines RL and bit lines BL1 to BLm or discharge the applied voltages.

[0056] In an implementation, the peripheral circuitry 120 may include an address decoder 121, a voltage generator 122, a page buffer group 123, a data input / output circuit 124, and a sensing circuit 125.

[0057] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments of this disclosure, row lines RL may also include transistor select lines.

[0058] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0059] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 can select at least one of the memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address RADD in the received address ADDR. Address decoder 121 can select at least one word line WL of the selected memory block by applying a voltage supplied from voltage generator 122 to at least one word line WL based on the decoded row address RADD.

[0060] During programming operations, address decoder 121 may apply a programming voltage to the selected word line and a pass voltage with a level lower than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 may apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word line.

[0061] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage, which is higher than the read voltage, to the unselected word line.

[0062] The erase operation of memory device 100 is performed on a block-by-block basis. During the erase operation, the address ADDR input to memory device 100 includes the block address. Address decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0063] Address decoder 121 can decode the column address in the received address ADDR. The decoded column address can be transmitted to page buffer set 123. In an embodiment, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0064] Voltage generator 122 can use the external power supply voltage supplied to memory device 100 to generate multiple operating voltages Vop. Voltage generator 122 can operate under the control of control logic 130.

[0065] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 can be used as the operating voltage of the memory device 100.

[0066] In this implementation, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. Voltage generator 122 can use either an external or internal power supply voltage to generate multiple operating voltages Vop. Voltage generator 122 can generate various voltages required by the memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0067] The voltage generator 122 may include multiple pump capacitors for receiving an internal power supply voltage to generate multiple operating voltages Vop with various voltage levels, and multiple operating voltages Vop can be generated by selectively enabling the multiple pump capacitors under the control of control logic 130.

[0068] The generated operating voltage Vop can be supplied to the memory cell array 110 through the address decoder 121.

[0069] Page buffer group 123 includes first page buffer PB1 to m-th page buffer PBm. First page buffer PB1 to m-th page buffer PBm are respectively connected to memory cell array 110 via first bit line BL1 to m-th bit line BLm. First page buffer PB1 to m-th page buffer PBm operate under the control of control logic 130.

[0070] Page buffers PB1 through PBm can send / receive data DATA to / from data input / output circuit 124. During programming operations, page buffers PB1 through PBm receive the data DATA to be stored through data input / output circuit 124 and data line DL.

[0071] During programming operations, when a programming pulse is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA to be stored, received via the data input / output circuit 124, to the selected memory cell via bit lines BL1 to BLm. The memory cell in the selected page is programmed based on the received data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied may have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied may be maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm can read the data DATA stored in the selected memory cell via bit lines BL1 to BLm.

[0072] During a read operation, page buffer group 123 can read data DATA from the memory cell in the selected page via bit lines BL1 to BLm, and can store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0073] During an erase operation, page buffer group 123 may allow bit lines BL1 to BLm to float. In one embodiment, page buffer group 123 may include column select circuitry.

[0074] In one implementation, when data stored in some of the multiple page buffers included in the page buffer group 123 is programmed into the memory cell array 110, the remaining page buffers can receive new data from the memory controller 200 and then store the new data.

[0075] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 operates under the control of the control logic 130.

[0076] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives data DATA to be stored from an external controller (not shown). During read operations, the data input / output circuit 124 outputs data DATA received from the first page buffer PB1 to the m-th page buffer PBm included in the page buffer group 123 to the external controller.

[0077] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current. In the example, when the magnitude of the sensed voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 can output a pass signal to the control logic 130. In the example, when the magnitude of the sensed voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 can output a failure signal to the control logic 130.

[0078] Control logic 130 can be connected to address decoder 121, voltage generator 122, page buffer group 123, data input / output circuitry 124, and sensing circuitry 125. Control logic 130 controls the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMDs) transmitted from external devices. Control logic 130 can be implemented as hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0079] Control logic 130 can control peripheral circuitry 120 by generating various types of signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, page buffer control signal PBSIGNALS to page buffer group 123, and enable bit VRYBIT to sensing circuit 125. Additionally, control logic 130 can determine whether the verification operation passed or failed in response to pass signal PASS or failure signal FAIL output from sensing circuit 125.

[0080] Figure 1 The weak character line determiner 140 and the programming operation controller 150 shown may be included in Figure 2 The control logic 130 shown.

[0081] The weak word line determiner 140 controls the peripheral circuitry 120 to perform a word line test operation to determine the weakest word lines among a plurality of word lines. The word line test operation may include a first pre-programming operation and a second pre-programming operation. The first pre-programming operation may be an operation to increase the threshold voltage of the memory cell by applying a pre-charge voltage to the common source line connected to the memory cell and applying a pre-programming voltage to the word line connected to the memory cell. The second pre-programming operation may be an operation to increase the threshold voltage of the memory cell by applying a ground voltage to the common source line connected to the memory cell and applying a pre-programming voltage to the word line connected to the memory cell.

[0082] Based on a comparison between the degree to which the threshold voltage of a memory cell increases through a first pre-programming operation and the degree to which the threshold voltage of a memory cell increases through a second pre-programming operation, the weak word line determiner 140 can determine the corresponding word line connected to the memory cell as a weak word line. The weak word line determiner 140 can store weak word line information, which is information obtained by determining each weak word line among a plurality of word lines.

[0083] The programming operation controller 150 controls the peripheral circuitry 120 to perform programming operations on the memory cells. The programming operation controller 150 controls the peripheral circuitry 120 to apply the operating voltage Vop to be used in the programming operation to the row lines RL and bit lines BL1 to BLm.

[0084] Figure 3 It is shown Figure 2 A diagram showing the structure of any one of the multiple storage blocks BLK1 to BLKz.

[0085] Reference Figure 3 Multiple word lines arranged in parallel can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKi may include multiple string STs connected between bit lines BL1 to BLm and a common source line (CSL). Bit lines BL1 to BLm can be connected to their respective string STs, and the common source line (CSL) can be collectively connected to a string ST. String STs can be configured in the same way, so a string ST connected to the first bit line BL1 will be described in detail as an example.

[0086] The string ST may include a source selection transistor SST connected in series between a common source line CSL and a first bit line BL1, a plurality of memory cells MC1+1 to MCm and a plurality of dummy memory cells D_MC1 to D_MC1 and D_MCm+1 to D_MCn, and a drain selection transistor DST. At least one source selection transistor SST and at least one drain selection transistor DST may be included in a string ST.

[0087] The source of the source-select transistor SST can be connected to the common source line CSL, and the drain of the drain-select transistor DST can be connected to the first bit line BL1. Memory cells MC1+1 to MCm can be connected in series between the dummy memory cells D_MC1 to D_MC1 adjacent to the source-select transistor SST and the dummy memory cells D_MCm+1 to D_MCn adjacent to the drain-select transistor DST. The dummy memory cells D_MC1 to D_MC1 adjacent to the source-select transistor SST can be connected in series between memory cells MC1+1 to MCm and the source-select transistor SST. The dummy memory cells D_MCm+1 to D_MCn adjacent to the drain-select transistor DST can be connected in series between memory cells MC1+1 to MCm and the drain-select transistor DST. The gates of source select transistors (SSTs) in different string STs can be connected to source select line SSL, and the gates of drain select transistors (DSTs) in different string STs can be connected to drain select line DSL. The gates of memory cells MC1+1 to MCm can be connected to multiple word lines WL1 to WLm, respectively. Multiple dummy memory cells D_MC1 to D_MC1 and D_MCm+1 to D_MCn can be connected to multiple dummy word lines D_WL1 to D_WL1 and D_WLm+1 to D_WLn, respectively. A group of memory cells connected to the same word line among the memory cells in different string STs can be referred to as a "physical page (PPG)". Therefore, memory block BLKi can include the same number of physical pages (PPGs) as the number of word lines WL1+1 to WLm.

[0088] A memory cell can store one bit of data. This cell is typically designated as a "single-level cell (SLC)". In this case, a physical page (PPG) can store the data corresponding to a logical page (LPG). The data corresponding to a logical page (LPG) can include the same number of data bits as the number of cells included in a physical page (PPG).

[0089] A memory cell can store two or more bits of data. In this case, a physical page (PPG) can store data corresponding to two or more logical pages (LPGs).

[0090] Figure 4 It is a graph showing the threshold voltage distribution of memory cells according to the programming operation of the memory device.

[0091] exist Figure 4 In the graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells (cell count).

[0092] Reference Figure 4The threshold voltage distribution of a memory cell can be changed from the initial state to the final programmed state according to the programming operation.

[0093] exist Figure 4 The text describes the programming of data using a TLC scheme that stores three bits of data in a single memory cell.

[0094] The initial state can be a state where no programming operation is performed and the threshold voltage distribution of the memory cell is in the erase state E.

[0095] The final programming state can be the threshold voltage distribution of the memory cells performing the programming operation. Each memory cell performing the programming operation can have a threshold voltage corresponding to any of a plurality of programming states. For example, when programming data according to a three-level cell (TLC) scheme where three bits of data are stored in one memory cell, the plurality of programming states can indicate an erase state E and first programming states PV1 to seventh programming states PV7. In an embodiment, each memory cell performing the programming operation can have a threshold voltage corresponding to either erase state E or first programming states PV1 to seventh programming states PV7. The threshold voltage of each memory cell in the initial state can be increased by the programming operation to a threshold voltage corresponding to either erase state E or first programming states PV1 to seventh programming states PV7.

[0096] Each memory cell can have either an erase state E or a programming state PV1 to PV7 as its target programming state. The target programming state can be determined based on the data to be stored in the corresponding memory cell. Through appropriate programming operations, the memory cell can have a threshold voltage corresponding to the target programming state in the final programming state.

[0097] Figure 5 This is a diagram illustrating the programming operations of a memory device.

[0098] exist Figure 5 In the graph, the horizontal axis indicates time, and the vertical axis indicates the voltage V applied to the word line. The voltage V applied to the word line can include the programming voltage Vpgm and the verification voltage V_vfy.

[0099] exist Figure 5 The present disclosure is described under the assumption that data is programmed using a TLC scheme that stores three bits of data in a single memory cell. However, the scope of this disclosure is not limited thereto, and a single memory cell may be programmed to store two bits of data or four or more bits of data.

[0100] Reference Figure 5The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. By executing the multiple programming cycles PL1 to PLn, the memory device 100 can perform programming operations such that each selected memory cell connected to a selected word line has a threshold voltage corresponding to any of a plurality of programming states. For example, when a single memory cell is programmed according to a TLC scheme, by executing the multiple programming cycles PL1 to PLn, the memory device 100 can perform programming operations such that the memory cell has a threshold voltage corresponding to any of the erase state E and the first programming states PV1 to the seventh programming states PV7.

[0101] Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step).

[0102] The programming voltage application operation (PGM step) can be an operation that applies a programming voltage to a selected word line connected to a selected memory cell. For example, memory device 100 may apply a first programming voltage Vpgm1 to the selected word line connected to the selected memory cell in a first programming cycle PL1. After the first programming voltage Vpgm1 is applied to the selected word line, the corresponding threshold voltage for the selected memory cell may be a threshold voltage corresponding to a target programming state among a plurality of programming states.

[0103] A verification operation (verification step) can be an operation of applying a verification voltage to a selected word line connected to a selected memory cell. A verification operation (verification step) can be an operation of determining whether the corresponding threshold voltage of the selected memory cell is the threshold voltage corresponding to a target programming state among multiple programming states. A verification operation (verification step) can be an operation of applying a verification voltage corresponding to the corresponding target programming state of the selected memory cell.

[0104] In this implementation, during the first programming cycle PL1, after the first programming voltage Vpgm1 is applied to the selected word line connected to the selected memory cell, the memory device 100 may apply first verification voltages V_vfy1 to seventh verification voltages V_vfy7 to the selected word line. In this case, the first verification voltage V_vfy1 can be used to perform a verification operation (verification step) on a memory cell having a first programming state as the target programming state. The second verification voltage V_vfy2 can be used to perform a verification operation (verification step) on a memory cell having a second programming state as the target programming state. The third verification voltage V_vfy3 can be used to perform a verification operation (verification step) on a memory cell having a third programming state as the target programming state. The fourth verification voltage V_vfy4 can be used to perform a verification operation (verification step) on a memory cell having a fourth programming state as the target programming state. The fifth verification voltage V_vfy5 can be used to perform a verification operation (verification step) on a memory cell having a fifth programming state as the target programming state. The sixth verification voltage V_vfy6 can be used to perform a verification operation (verification step) on a memory cell having a sixth programming state as the target programming state. A verification operation (verification step) can be performed on a memory cell with a seventh programming state as the target programming state using a seventh verification voltage V_vfy7. The magnitudes of the verification voltages V_vfy1 to V_vfy7 can increase in the direction from the first verification voltage V_vfy1 to the seventh verification voltage V_vfy7. Specifically, for the magnitudes of the verification voltages V_vfy1 to V_vfy7, the first verification voltage V_vfy1 can be the lowest, and the seventh verification voltage V_vfy7 can be the highest. The number of verification voltages is not limited to this embodiment.

[0105] It can be determined that the memory cells that have passed the verification operation (verification step) using the corresponding verification voltages V_vfy1 to V_vfy7 have a threshold voltage corresponding to the target programming state. The memory cells that have passed the verification operation (verification step) can be programmed disabled in the second programming cycle PL2. The programming disable voltage can be applied to the bit line connected to the programming disable memory cell.

[0106] It can be determined that memory cells for which verification steps using the corresponding verification voltages V_vfy1 to V_vfy7 have failed do not have the threshold voltage corresponding to the target programming state. Memory cells for which verification steps have failed can execute the second programming cycle PL2.

[0107] In the second programming cycle PL2, the memory device 100 may apply a second programming voltage Vpgm2, which is a unit voltage ΔVpgm higher than the first programming voltage Vpgm1, to the selected word line connected to the selected memory cell. Thereafter, the memory device 100 may perform the verification operation (verification step) of the second programming cycle PL2 in the same manner as the verification operation (verification step) of the first programming cycle PL1.

[0108] Subsequently, the memory device 100 may execute subsequent programming cycles a preset number of times in the same manner as the second programming cycle PL2.

[0109] In this implementation, a programming operation may fail if it is not completed within a preset number of programming loops. A programming operation may succeed if it is completed within the preset number of programming loops. Whether a programming operation is complete can be determined based on whether all selected memory cells have passed the verification operation (verification step). If all selected memory cells have passed the verification operation (verification step), subsequent programming loops may not be executed.

[0110] In this implementation, the programming voltage can be determined based on the Incremental Step Pulse Programming (ISPP) method. As programming cycles PL1 to PLn repeat, the level of the programming voltage can be increased or decreased in stages (i.e., by step voltage). The number of times the programming voltage is applied, the voltage level of the programming voltage, the voltage application time, etc., used in each programming cycle can be determined in various forms under the control of the storage controller 200.

[0111] Figure 6 This is a diagram illustrating the operation of a weak character line determiner according to an embodiment of the present disclosure.

[0112] Reference Figure 6 The weak word line determiner 140 can control the peripheral circuitry 120 to perform word line test operations on multiple memory cells. During the word line test operation, a first pre-programming operation (Pre-PGM1 and Pre-Verify1), an erase operation, a second pre-programming operation (Pre-PGM2 and Pre-Verify2), a weak word line determination operation (Comparing), and an erase operation (Erase) can be performed sequentially.

[0113] The first pre-programming operation (Pre-PGM1 and Pre-Verify1) may include a first pre-programming voltage application operation Pre-PGM1 and a first pre-verification operation Pre-Verify1. The first pre-programming voltage application operation Pre-PGM1 may include a pre-charge period, a programming pulse period Pgm Pulse, and a discharge period Discharge.

[0114] The second pre-programming operation (Pre-PGM2 and Pre-Verify2) may include a second pre-programming voltage application operation Pre-PGM2 and a second pre-verification operation Pre-Verify2. The second pre-programming voltage application operation Pre-PGM2 may include a pre-charge period, a programming pulse period Pgm Pulse, and a discharge period Discharge.

[0115] First pre-programmed voltage application operation Pre-PGM1 and second pre-programmed voltage application operation Pre-PGM2 refer to Figure 6 The description of the first pre-verification operation Pre-Verify1 and the second pre-verification operation Pre-Verify2 will be referred to later. Figure 7 describe.

[0116] The period from t1 to t4 can be the period during which the first pre-programming voltage application operation Pre-PGM1 is performed. The period from t1 to t2 can be the pre-charge period. The pre-charge period can be the period during which the channel regions of multiple memory cells are pre-charged. During the period from t1 to t2, the weak word line determiner 140 can apply a pre-charge voltage Vpre to the common source line CSL. During the period from t1 to t2, the weak word line determiner 140 can apply a turn-on voltage Von to the source select line SSL. Here, the turn-on voltage Von can be a voltage higher than the threshold voltage of the source select transistor connected to the source select line. The weak word line determiner 140 can increase the channel potential of multiple memory cells by applying the pre-charge voltage Vpre to the common source line CSL.

[0117] The period from t2 to t3 can be the programming pulse period Pgm Pulse. The programming pulse period Pgm Pulse can be a period during which the threshold voltages of multiple memory cells increase. During the period from t2 to t3, the weak word line determiner 140 can apply a pre-programming voltage pre_Vp to the selected word line Sel_WL. During the period from t2 to t3, the weak word line determiner 140 can apply a pass voltage Vpass to the unselected word line Unsel_WL. During the period from t2 to t3, the weak word line determiner 140 can apply a ground voltage Gnd to the common source line CSL. During the period from t2 to t3, the weak word line determiner 140 can apply a ground voltage Gnd to the source select line SSL.

[0118] The period from t3 to t4 can be the discharge period. During the period from t3 to t4, the weak word line determiner 140 can apply a ground voltage Gnd to the selected word line Sel_WL. During the period from t3 to t4, the weak word line determiner 140 can apply a ground voltage Gnd to the unselected word line Unsel_WL.

[0119] During the time period from t4 to t5, the weak word line determiner 140 can perform the first pre-verification operation Pre-Verify1 and the erase operation Erase.

[0120] The period from t5 to t8 can be the period for performing the second pre-programmed voltage application operation Pre-PGM2. Specifically, the period from t5 to t6 can be the pre-charge period. During the period from t5 to t6, the weak word line determiner 140 can apply a ground voltage Gnd to the common source line CSL. During the period from t5 to t6, the weak word line determiner 140 can apply a ground voltage Gnd to the source selection line SSL.

[0121] The period from t6 to t7 can be the programming pulse period Pgm Pulse. During the period from t6 to t7, the weak word line determiner 140 can apply a pre-programmed voltage pre_Vp to the selected word line Sel_WL. During the period from t6 to t7, the weak word line determiner 140 can apply a pass voltage Vpass to the unselected word line Unsel_WL.

[0122] The period from t7 to t8 can be the discharge period. During the period from t7 to t8, the weak word line determiner 140 can apply a ground voltage Gnd to the selected word line Sel_WL. During the period from t7 to t8, the weak word line determiner 140 can apply a ground voltage Gnd to the unselected word line Unsel_WL.

[0123] After time t8, the weak word line determiner 140 can perform the second pre-verification operation Pre-Verify2, the weak word line determination operation Comparing, and the erase operation Erase.

[0124] Figure 7 This is a diagram illustrating the operation of determining weak word lines according to an embodiment of the present disclosure.

[0125] exist Figure 7 In the graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells (cell count).

[0126] Figure 7 The upper part of the graph can indicate the threshold voltage distribution of the memory cell that performs the first pre-programmed voltage application operation. Figure 7 The curve in the middle of the graph can indicate the threshold voltage distribution of memory cells in the erase state E. Figure 7The lower part of the graph indicates the threshold voltage distribution of the memory cell when the second pre-programming voltage application operation is performed. The degree to which the threshold voltage of the memory cell increases due to the first pre-programming voltage application operation may be greater than the degree to which the threshold voltage of the memory cell increases due to the second pre-programming voltage application operation.

[0127] Reference Figure 7 The upper part of the graph indicates that the weak word line determiner 140 can perform a first pre-verification operation after performing a first pre-programming voltage application operation. The weak word line determiner 140 can perform a first pre-verification operation that identifies the threshold voltage of the memory cell increased by the first pre-programming voltage application operation. The weak word line determiner 140 can use a pre-verification voltage pre_vfy to identify the threshold voltage of the memory cell during the first pre-verification operation. The weak word line determiner 140 can count the number Num pb1 of first cutoff cells whose threshold voltage is higher than the pre-verification voltage pre_vfy during the first pre-verification operation. In one embodiment, the weak word line determiner 140 can store the number Numb1 of first cutoff cells identified by the first pre-verification operation in a page buffer. In another embodiment, the weak word line determiner 140 can perform an erase operation after performing the first pre-programming operation.

[0128] Reference Figure 7 The lower part of the graph shows that the weak word line determiner 140 can perform a second pre-verification operation after performing a second pre-programming voltage application operation. The weak word line determiner 140 can perform a second pre-verification operation that identifies the threshold voltage of the memory cell increased by the second pre-programming voltage application operation. The weak word line determiner 140 can use the pre-verification voltage pre_vfy to identify the threshold voltage of the memory cell during the second pre-verification operation. The weak word line determiner 140 can count the number Num pb2 of second cutoff cells whose threshold voltage is higher than the pre-verification voltage pre_vfy during the second pre-verification operation. In an embodiment, the weak word line determiner 140 can store the number Numb2 of second cutoff cells identified by the second pre-verification operation in a page buffer.

[0129] Subsequently, the weak word line determiner 140 can perform a weak word line determination operation to determine whether a word line connected to a memory cell is a weak word line based on the number of first cutoff cells Num pb1 and the number of second cutoff cells Num pb2. Specifically, the weak word line determiner 140 can determine word lines connected to memory cells whose difference between the number of first cutoff cells Num pb1 and the number of second cutoff cells Num pb2 is greater than a reference number of cutoff cells Ref pb as weak word lines. On the other hand, the weak word line determiner 140 can determine word lines connected to memory cells whose difference between the number of first cutoff cells Num pb1 and the number of second cutoff cells Num pb2 is less than or equal to the reference number of cutoff cells Ref pb as normal word lines. In an embodiment, the weak word line determiner 140 can perform an erase operation after performing the weak word line determination operation.

[0130] The weak word line determiner 140 can determine whether each of a plurality of word lines is a weak word line by performing a first pre-programming operation and a second pre-programming operation. In an embodiment, the weak word line determiner 140 can store the weak word line information obtained by determining whether the plurality of word lines are weak word lines in a storage container. Figure 2 The storage block can be any one of the multiple storage blocks BLK1 to BLKz shown. This storage block can be a content-addressable memory block (CAM block). For example, a CAM block can store programming voltage information required to perform programming operations on the memory device 100, addresses of bad memory blocks, etc. In an embodiment, the weak word line determiner 140 may include... Figure 2 The weak word line information storage unit 141 stores weak word line information read from the one storage block. The weak word line determiner 140 can provide the weak word line information to the programming operation controller 150.

[0131] Figure 8 This is a diagram showing information about weak letter lines.

[0132] Reference Figure 8The memory cell array can be a structure in which multiple memory cells are stacked along a first channel region CH1 and a second channel region CH2. The first channel region CH1 may include a first memory cell. The second channel region CH2 may include a second memory cell. Each of a plurality of word lines WL1 to WLn may be connected to a memory cell. Word lines located at the lower part of the first channel region CH1 and word lines located at the lower part of the second channel region CH2 may be weak word lines Wk_WL. For example, the first word line WL1 and the second word line WL2, the (i+2)th word line WLi+2 and the (i+3)th word line WLi+3 may be weak word lines Wk_WL. Word lines connected to memory cells located at the lower part of the first channel region CH1 and the second channel region CH2 may be weak word lines Wk_WL. The weak word line determiner 140 may store information about the word lines located at the corresponding lower part of the first channel region CH1 and the second channel region CH2 as information about each weak word line (i.e., weak word line information). In the embodiment, although Figure 8 As not shown, a dummy word line may be included between the drain select line DSL and the nth word line WLn. In an embodiment, a dummy word line may be included between the source select line SSL and the first word line WL1. In an embodiment, a dummy word line may be included between the (i+1)th word line WLi+1 and the (i+2)th word line WLi+2.

[0133] Figure 9 This is a diagram illustrating a first implementation of programming operations performed in a first programming mode or a second programming mode.

[0134] exist Figure 9 In the graph, the horizontal axis indicates time, and the vertical axis indicates the pre-charge voltage Vpre applied to the common source line.

[0135] The programming operation controller 150 can receive programming commands, addresses, and data from the memory controller, and then execute programming operations. The programming operation controller 150 can perform programming operations on selected memory cells connected to selected word lines corresponding to the addresses received from the memory controller.

[0136] The programming operation controller 150 can determine the programming operation mode as either a first programming mode (Pgm mode 1) or a second programming mode (Pgm mode 2) based on weak word line information received from the weak word line determiner 140. In one embodiment, when the selected word line is determined to be a weak word line based on the weak word line information, the programming operation controller 150 can perform the programming operation in the first programming mode. In another embodiment, when the selected word line is determined to be a normal word line based on the weak word line information, the programming operation controller 150 can perform the programming operation in the second programming mode.

[0137] Reference Figure 9The programming operation may include multiple programming cycles PL1 to PLn. In the programming voltage application operation (PGM step), the programming operation controller 150 may apply a precharge voltage Vpre to the common source line and then apply a programming voltage to the selected word line.

[0138] In the first programming mode (Pgm mode 1), the programming operation controller 150 can apply a pre-charge voltage Vpre to the common source line starting from any of the multiple programming cycles PL1 to PLn. This programming cycle can be a preset programming cycle. For example, in the first programming mode (Pgm mode 1), the programming operation controller 150 can apply the pre-charge voltage Vpre to the common source line starting from the (i+2)th programming cycle PLi+2 of the multiple programming cycles PL1 to PLn.

[0139] In the second programming mode, Pgm mode 2, the programming operation controller 150 can apply the precharge voltage Vpre to the common source line starting from the programming cycle preceding this programming cycle. For example, in the second programming mode, Pgm mode 2, the programming operation controller 150 can apply the precharge voltage Vpre to the common source line starting from the i-th programming cycle PLi among multiple programming cycles PL1 to PLn. That is, the number of programming cycles in which the precharge voltage Vpre is applied to the common source line in the first programming mode, Pgm mode 1, is less than the number of programming cycles in which the precharge voltage Vpre is applied to the common source line in the second programming mode, Pgm mode 2. The number of programming cycles in which the precharge voltage Vpre is applied to the common source line during programming operations on memory cells connected to weak word lines is less than the number of programming cycles in which the precharge voltage Vpre is applied to the common source line during programming operations on memory cells connected to normal word lines.

[0140] Figure 10 This is a diagram illustrating a second implementation of the programming operations performed in the first programming mode.

[0141] Figure 11 This is a diagram illustrating a second implementation of programming operations performed in a second programming mode.

[0142] Reference Figure 10 and Figure 11 Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step). The programming voltage application operation (PGM step) may include a precharge period, a programming pulse period (Pgm Pulse), and a discharge period (Discharge).

[0143] Reference Figure 10The programming operation controller 150 can perform programming operations in the first programming mode, Pgm mode 1. The time period from t1 to t2 can be a pre-charge period. During the time period from t1 to t2, the programming operation controller 150 can apply a turn-on voltage Von to the selected word line Sel_WL within a first time pre_t1, and then apply a ground voltage Gnd to the selected word line Sel_WL. During the time period from t1 to t2, the programming operation controller 150 can apply a turn-on voltage Von to the unselected word line Unsel_WL within a first time pre_t1, and then apply a ground voltage Gnd to the unselected word line Unsel_WL. During the time period from t1 to t2, the programming operation controller 150 can apply a pre-charge voltage Vpre to the common source line CSL within a first time pre_t1, and then apply a ground voltage Gnd to the common source line CSL. During the time period from t1 to t2, the programmable operation controller 150 can apply the turn-on voltage Von to the source select line SSL in the first time pre_t1, and thereafter apply the ground voltage Gnd to the source select line SSL.

[0144] Reference Figure 11 The programming operation controller 150 can perform programming operations in the second programming mode, Pgm mode 2. During the time period from t1 to t2, the programming operation controller 150 can apply a turn-on voltage Von to the selected word line Sel_WL within the second time period pre_t2, and thereafter apply a ground voltage Gnd to the selected word line Sel_WL. During the time period from t1 to t2, the programming operation controller 150 can apply a turn-on voltage Von to the unselected word line Unsel_WL within the second time period pre_t2, and thereafter apply a ground voltage Gnd to the unselected word line Unsel_WL. During the time period from t1 to t2, the programming operation controller 150 can apply a pre-charge voltage Vpre to the common source line CSL within the second time period pre_t2, and thereafter apply a ground voltage Gnd to the common source line CSL. During the time period from t1 to t2, the programmable operation controller 150 may apply the turn-on voltage Von to the source select line SSL during the second time pre_t2, and thereafter apply the ground voltage Gnd to the source select line SSL.

[0145] The first time interval pre_t1 can be shorter than the second time interval pre_t2. In the first programming mode Pgm mode1, the time for the precharge voltage Vpre to be applied to the common source line CSL can be shorter than the time for the precharge voltage Vpre to be applied to the common source line CSL in the second programming mode Pgm mode2. That is, the time for the channel region of the memory cell to be precharged in the first programming mode Pgm mode1 can be shorter than the time for the channel region of the memory cell to be precharged in the second programming mode Pgm mode2. In programming operations performed on memory cells connected to weak word lines, the time for the precharge voltage Vpre to be applied to the common source line CSL can be shorter than the time for programming operations performed on memory cells connected to normal word lines.

[0146] Reference Figure 10 and Figure 11 The time period from t2 to t3 can be the programming pulse period Pgm Pulse. During the time period from t2 to t3, the programming operation controller 150 can apply a pass voltage Vpass to the selected word line Sel_WL, and thereafter apply a programming voltage Vpgm to the selected word line Sel_WL. During the time period from t2 to t3, the programming operation controller 150 can apply a pass voltage Vpass to the unselected word line Unsel_WL.

[0147] Reference Figure 10 and Figure 11 The period from t3 to t4 can be the discharge period. During the period from t3 to t4, the programmable controller 150 can apply a ground voltage Gnd to the selected word line Sel_WL. During the period from t3 to t4, the programmable controller 150 can apply a ground voltage Gnd to the unselected word line Unsel_WL.

[0148] Figure 12 This is a diagram illustrating a third implementation of the programming operations performed in the first programming mode.

[0149] Figure 13 This is a diagram illustrating a third implementation of programming operations performed in the second programming mode.

[0150] exist Figure 12 and Figure 13 In the middle, omission and Figure 10 and Figure 11 The same component is described repeatedly.

[0151] Reference Figure 12 and Figure 13The programming voltage application operation (PGM step) may include a precharge period, a programming pulse period (Pgm Pulse), and a discharge period (Discharge).

[0152] Reference Figure 12 The programming operation controller 150 can perform programming operations in the first programming mode, Pgm mode 1. The time period from t1 to t2 can be a pre-charging period. During the time period from t1 to t2, the programming operation controller 150 can apply an on-state voltage Von to the selected word line Sel_WL, and then apply a ground voltage Gnd to the selected word line Sel_WL. During the time period from t1 to t2, the programming operation controller 150 can apply an on-state voltage Von to the word line adj_WL adjacent to the selected word line, and then apply a ground voltage Gnd to the word line adj_WL. During the time period from t1 to t2, the programming operation controller 150 can apply an on-state voltage Von to the first unselected word line group Unsel_WL1, and then apply a ground voltage Gnd to the first unselected word line group Unsel_WL1. In one implementation, during the time period from t1 to t2, the programming operation controller 150 may apply a turn-on voltage Von to the first unselected word line group Unsel_WL1 and the second unselected word line group Unsel_WL2, and subsequently apply a ground voltage Gnd to them. In another implementation, during the time period from t1 to t2, the programming operation controller 150 may apply a ground voltage Gnd to the first unselected word line group Unsel_WL1 and the second unselected word line group Unsel_WL2. The first unselected word line group Unsel_WL1 may be a word line adjacent to the source select line SSL. The third unselected word line group Unsel_WL3 may be a word line adjacent to the drain select line. During the time period from t1 to t2, the programming operation controller 150 may apply a pre-charge voltage Vpre to the common source line CSL, and subsequently apply a ground voltage Gnd to it. During the time period from t1 to t2, the programmable operation controller 150 can apply the turn-on voltage Von to the source selection line SSL and thereafter apply the ground voltage Gnd to it.

[0153] Reference Figure 13The programming operation controller 150 can perform programming operations in the second programming mode, Pgm mode 2. During the time period from t1 to t2, the programming operation controller 150 can apply a turn-on voltage Von to the selected word line Sel_WL, and then apply a ground voltage Gnd to it. During the time period from t1 to t2, the programming operation controller 150 can apply a turn-on voltage Von to the word line adj_WL adjacent to the selected word line, and then apply a ground voltage Gnd to it. During the time period from t1 to t2, the programming operation controller 150 can apply a ground voltage Gnd to the remaining word lines r_WL among the multiple word lines, excluding the selected word line and the adjacent word line. During the time period from t1 to t2, the programming operation controller 150 can apply a pre-charge voltage Vpre to the common source line CSL, and then apply a ground voltage Gnd to it. During the time period from t1 to t2, the programming operation controller 150 can apply a turn-on voltage Von to the source selection line SSL, and then apply a ground voltage Gnd to it.

[0154] In the first programming mode (Pgm mode 1), during the precharge period, the on-state voltage Von can be applied to the remaining word lines r_WL, excluding the word lines adjacent to the selected word line. In the second programming mode (Pgm mode 2), during the precharge period, the ground voltage Gnd can be applied to the remaining word lines r_WL, excluding the word lines adjacent to the selected word line. During programming operations on memory cells connected to weak word lines, when the precharge voltage Vpre is applied to the common source line CSL, the on-state voltage Von can be applied to the remaining word lines. During programming operations on memory cells connected to normal word lines, when the precharge voltage Vpre is applied to the common source line CSL, the ground voltage Gnd can be applied to the remaining word lines.

[0155] Figure 14 This is a diagram illustrating a fourth embodiment of programming operations performed in a first programming mode or a second programming mode.

[0156] exist Figure 14 In this section, only the differences between the first programming mode and the second programming mode will be described in detail, including the programming pulse period Pgm Pulse in the programming voltage application operation (PGM step).

[0157] Reference Figure 14In the first programming mode Pgm mode 1, the programming operation controller 150 can apply a first pass voltage Vpass1 to the selected word line Sel_WL, and then apply a programming voltage Vpgm to it. In the first programming mode Pgm mode 1, the programming operation controller 150 can apply the first pass voltage Vpass1 to the unselected word line Unsel_WL. In the first programming mode Pgm mode 1, the programming operation controller 150 can apply the first pass voltage Vpass1 to the word line adjacent to the selected word line and the dummy word line D_WL among the unselected word lines. In an embodiment, in the first programming mode Pgm mode 1, the programming operation controller 150 can apply a second pass voltage Vpass2, higher than the first pass voltage Vpass1, to the word line adjacent to the selected word line and the dummy word line D_WL among the unselected word lines, and can apply the first pass voltage Vpass1 to the remaining word lines other than the adjacent word lines among the unselected word lines. For example, the dummy word line D_WL can be... Figure 3 The dummy word lines D_WL1 to D_WLI and D_WLm+1 to D_WLn are shown. In the example, the dummy word line D_WL can be set to... Figure 8 The word line between the (i+1)th word line WLi+1 and the (i+2)th word line WLi+2 shown.

[0158] In the second programming mode Pgm mode2, the programming operation controller 150 can apply a second pass voltage Vpass2 to the selected word line Sel_WL, and subsequently apply a programming voltage Vpgm to it. In the second programming mode Pgm mode2, the programming operation controller 150 can also apply the second pass voltage Vpass2 to the unselected word line Unsel_WL. In the second programming mode Pgm mode2, the programming operation controller 150 can also apply the second pass voltage Vpass2 to the dummy word line D_WL.

[0159] The magnitude of the second pass voltage Vpass2 can be greater than the magnitude of the first pass voltage Vpass1. In the first programming mode Pgm mode1, the programming operation controller 150 can apply the first pass voltage Vpass1 to the unselected word line Unsel_WL and the dummy word line D_WL when the programming voltage Vpgm is applied to the selected word line Sel_WL. In the second programming mode Pgm mode2, the programming operation controller 150 can apply a second pass voltage Vpass2, which is higher than the first pass voltage Vpass1, to the unselected word line Unsel_WL and the dummy word line D_WL when the programming voltage Vpgm is applied to the selected word line Sel_WL.

[0160] Figure 15 This is a diagram illustrating a fifth embodiment of programming operations performed in a first programming mode or a second programming mode.

[0161] exist Figure 15 In this section, only the differences between the first programming mode and the second programming mode will be described in detail, including the programming pulse period Pgm Pulse in the programming voltage application operation (PGM step).

[0162] Reference Figure 15 In the first programming mode Pgm mode1, the programming operation controller 150 can apply a first pass voltage Vpass1 to the selected word line Sel_WL, and then apply a programming voltage Vpgm to it. In the first programming mode Pgm mode1, the programming operation controller 150 can apply the first pass voltage Vpass1 to the word line adj_WL adjacent to the selected word line. In the first programming mode Pgm mode1, the programming operation controller 150 can apply the first pass voltage Vpass1 to the remaining word lines r_WL among the unselected word lines, excluding the word lines adjacent to the selected word line.

[0163] In the second programming mode, Pgm mode 2, the programming operation controller 150 can apply a first pass voltage Vpass1 to the selected word line Sel_WL, and then apply a programming voltage Vpgm to it. In the second programming mode, Pgm mode 2, the programming operation controller 150 can apply the first pass voltage Vpass1 to the word line adj_WL adjacent to the selected word line, and then apply a second pass voltage Vpass2 to it, which is higher than the first pass voltage Vpass1. In the second programming mode, Pgm mode 2, the programming operation controller 150 can apply the first pass voltage Vpass1 to the remaining word lines r_WL.

[0164] In the first programming mode (Pgm mode 1), the programming operation controller 150 can apply a first pass voltage (Vpass 1) to the adjacent word line (adj_WL) when the programming voltage (Vpgm) is applied to the selected word line (Sel_WL). In the second programming mode (Pgm mode 2), the programming operation controller 150 can apply a second pass voltage (Vpass 2), which is higher than the first pass voltage (Vpass 1), to the adjacent word line (adj_WL) when the programming voltage (Vpgm) is applied to the selected word line (Sel_WL).

[0165] Figure 16 This is a flowchart illustrating a word line test operation for determining weak word lines according to an embodiment of the present disclosure.

[0166] Reference Figure 16In step S1601, the memory device 100 may count the number of first cutoff cells identified by the first pre-programming operation among a plurality of memory cells. The memory device 100 may store the number of first cutoff cells in a page buffer. In an embodiment, the memory device 100 may perform an erase operation on the plurality of memory cells after executing step S1601.

[0167] In step S1603, the memory device 100 may count the number of second cutoff cells identified by the second pre-programming operation among a plurality of memory cells. The memory device 100 may store the number of second cutoff cells in a page buffer. In an embodiment, the memory device 100 may perform an erase operation on the plurality of memory cells after executing step S1603.

[0168] In step S1605, the memory device 100 determines whether the difference between the number of first cutoff units and the number of second cutoff units is greater than a reference number of cutoff units. When the difference between the number of first cutoff units and the number of second cutoff units is greater than the reference number of cutoff units, step S1607 can be executed. When the difference between the number of first cutoff units and the number of second cutoff units is less than or equal to the reference number of cutoff units, step S1609 can be executed.

[0169] In step S1607, when the difference between the number of the first cutoff cells and the number of the second cutoff cells is greater than the reference number of cutoff cells, the memory device 100 may determine the word lines connected to the plurality of memory cells as weak word lines.

[0170] In step S1609, when the difference between the number of the first cutoff cells and the number of the second cutoff cells is less than or equal to the reference number of cutoff cells, the memory device 100 can determine the word lines connected to the plurality of memory cells as normal word lines.

[0171] Figure 17 This is a flowchart illustrating the programming operations of a memory device according to an embodiment of the present disclosure.

[0172] Reference Figure 17 In step S1701, the memory device 100 may receive commands, addresses, and data from the memory controller. The commands received from the memory controller may be programming commands.

[0173] In step S1703, the memory device 100 can determine whether the word line corresponding to the address received from the memory controller is a weak word line by comparing word lines. The word line corresponding to the address can be a selected word line. When the word line corresponding to the address received from the memory controller is a weak word line, step S1705 can be executed. The word line corresponding to the address can be a selected word line. When the word line corresponding to the address received from the memory controller is not a weak word line, step S1707 can be executed.

[0174] In step S1705, the memory device 100 can perform programming operations in the first programming mode.

[0175] In step S1707, the memory device 100 can perform programming operations in the second programming mode.

[0176] Figure 18 This is a block diagram illustrating a memory card system to which a memory system according to an embodiment of the present disclosure is applied.

[0177] Reference Figure 18 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0178] Storage controller 2100 is coupled to memory device 2200. Storage controller 2100 can access memory device 2200. For example, storage controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Storage controller 2100 can provide an interface between memory device 2200 and host computer. Storage controller 2100 can run firmware for controlling memory device 2200. Storage controller 2100 can be configured according to the above reference. Figure 1 The memory controller 200 described is implemented in the same manner. The memory device 2200 can be implemented in accordance with the above reference. Figure 1 The memory device 100 described is implemented in the same manner.

[0179] In some implementations, the storage controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and error correction circuitry.

[0180] Storage controller 2100 can communicate with external devices via connector 2300. Storage controller 2100 can communicate with external devices (e.g., a host) based on specific communication standards or protocols. In embodiments, storage controller 2100 can communicate with external devices via at least one of various communication standards or protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe). In embodiments, connector 2300 can be defined by at least one of the aforementioned communication standards or protocols.

[0181] In an implementation, the memory device 2200 may be implemented using any of a variety of non-volatile memory types such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), spin-transfer torque magnetic RAM (STT-MRAM), etc.

[0182] The storage controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the storage controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association: PCMCIA), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC), or universal flash memory (UFS).

[0183] Figure 19 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure.

[0184] Reference Figure 19 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0185] Application processor 4100 may run components, operating systems (OS), or user programs included in user system 4000. In some embodiments, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-chip (SoC).

[0186] Memory module 4200 can be used to provide main memory, working memory, buffer memory, or cache memory for user system 4000. Memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In embodiments, application processor 4100 and memory module 4200 may be packaged based on a stacked package (POP) and then provided as a single semiconductor package.

[0187] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi. In some embodiments, network module 4300 may be included in application processor 4100.

[0188] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send data stored in storage module 4400 to application processor 4100. In embodiments, storage module 4400 can be implemented using a non-volatile semiconductor memory device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In embodiments, storage module 4400 can be provided as a removable storage medium (i.e., a removable drive) such as a memory card or an external drive of user system 4000.

[0189] In an implementation, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above. Figure 1 The memory device 100 described herein operates in the same manner. The memory module 4400 can operate in accordance with the above-described reference. Figure 1The memory system 50 described operates in the same manner.

[0190] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In embodiments, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0191] According to embodiments of the present disclosure, a memory device is provided that can improve the threshold voltage distribution of memory cells during programming operations. Additionally, according to the present disclosure, a method for operating the memory device is provided.

[0192] Cross-reference of related applications

[0193] This application claims priority to Korean Patent Application No. 10-2022-0067421, filed with the Korean Intellectual Property Office on June 2, 2022, the full disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple memory cells, which are connected to multiple word lines; The peripheral circuit performs a word line test operation to determine the weakest word line among the plurality of word lines; as well as A weak word line determiner controls the peripheral circuitry such that, during the word line test operation, the result obtained by comparing the number of first cutoff cells identified through a first pre-programming operation with the number of second cutoff cells identified through a second pre-programming operation is stored in any memory block. The first pre-programming operation involves applying a pre-charge voltage to the source lines commonly connected to the plurality of memory cells, and subsequently applying a pre-programming voltage to a selected word line among the plurality of word lines. The second pre-programming operation is the operation of applying a ground voltage to the source line and then applying the pre-programmed voltage to the selected word line.

2. The memory device according to claim 1, wherein, The weak word line determiner controls the peripheral circuit such that when the difference between the number of the first cutoff unit and the number of the second cutoff unit is greater than the reference number of cutoff units, the result information indicating that the selected word line is the weak word line is stored in the storage block.

3. The memory device according to claim 2, wherein, The weak word line determiner controls the peripheral circuitry such that when the difference between the number of the first cutoff unit and the number of the second cutoff unit is less than or equal to the reference number of the cutoff unit, result information indicating that the selected word line is a normal word line is stored in the storage block.

4. The memory device according to claim 3, wherein, Each of the first pre-programming operation and the second pre-programming operation includes a pre-verification operation that uses a pre-verification voltage to identify a threshold voltage connected to a selected memory cell of the selected word line, and Each of the number of the first cutoff cells and the number of the second cutoff cells is the number of memory cells in the selected memory cells whose threshold voltage is higher than the pre-verification voltage.

5. A memory device comprising: Multiple memory cells, which are connected to multiple word lines; Peripheral circuitry that performs programming operations to store data in the plurality of memory units; A weak word line information storage unit stores information about weak word lines among the plurality of word lines; as well as A programming operation controller controls the peripheral circuitry to perform a programming operation in a first programming mode or a second programming mode, based on a result of determining whether a selected word line corresponding to an address provided from the memory controller is a weak word line by comparing word lines based on information about the weak word lines. The information regarding the weak word line includes information determined by comparing a first pre-programming operation with a second pre-programming operation, wherein the first pre-programming operation is to apply a pre-charge voltage to the source line commonly connected to the plurality of memory cells and increase the threshold voltage of the plurality of memory cells, and the second pre-programming operation is to apply a ground voltage to the source line and increase the threshold voltage of the plurality of memory cells.

6. The memory device according to claim 5, wherein, The information regarding the weak word line includes information determined based on a comparison of the number of first cutoff units identified by the first preprogramming operation with the number of second cutoff units identified by the second preprogramming operation.

7. The memory device according to claim 6, wherein, The information regarding the weak word lines includes information about word lines connected to memory cells whose difference between the number of the first cutoff cells and the number of the second cutoff cells is greater than a reference number of cutoff cells.

8. The memory device according to claim 5, wherein, The plurality of memory cells include a first memory cell included in a first channel region and a second memory cell included in a second channel region disposed above the first channel region, and The information regarding the weak word lines includes information about word lines connected to memory cells located in the corresponding lower portions of the first and second channel regions.

9. The memory device according to claim 5, wherein, The programming operation controller controls the peripheral circuit so that when the selected word line is a weak word line, the programming operation is performed in the first programming mode, and when the selected word line is a normal word line, the programming operation is performed in the second programming mode.

10. The memory device according to claim 9, wherein, The programming operations include multiple programming loops, and The programming operation controller controls the peripheral circuit such that, in the first programming mode, the pre-charge voltage is applied to the source line starting from any programming cycle in the programming loop, and in the second programming mode, the pre-charge voltage is applied to the source line starting from the programming loop preceding the first programming loop.

11. The memory device according to claim 9, wherein, The programmable controller controls the peripheral circuit, such that: In the first programming mode, the pre-charge voltage is applied to the source line during a first time period, and thereafter the programming voltage is applied to the selected word line, and In the second programming mode, the pre-charge voltage is applied to the source line during a second period shorter than the first period, and thereafter the programming voltage is applied to the selected word line.

12. The memory device according to claim 9, wherein, The programmable controller controls the peripheral circuit, such that: In the first programming mode, when the pre-charge voltage is applied to the source line, the on-state voltage is applied to the unselected word line among the plurality of word lines, and In the second programming mode, when the precharge voltage is applied to the source line, the ground voltage is applied to the unselected word line.

13. The memory device according to claim 9, wherein, The programmable controller controls the peripheral circuit, such that: In the first programming mode, when a programming voltage is applied to the selected word line, a first pass voltage is applied to the unselected word line among the plurality of word lines, and In the second programming mode, when the programming voltage is applied to the selected word line, a second pass voltage higher than the first pass voltage is applied to the unselected word line.

14. The memory device according to claim 9, wherein, The programmable controller controls the peripheral circuit, such that: In the first programming mode, when a programming voltage is applied to the selected word line, a first pass voltage is applied to the unselected word line among the plurality of word lines, and In the second programming mode, when the programming voltage is applied to the selected word line, a second through voltage higher than the first through voltage is applied to the word line adjacent to the selected word line among the plurality of word lines, and the first through voltage is applied to the remaining word lines among the plurality of word lines other than the selected word line and the word line adjacent to the selected word line.

15. A method of operating a memory device, the memory device comprising a plurality of memory cells coupled to a plurality of word lines, the method comprising the steps of: Based on information about weak word lines, it is determined whether the selected word line is a weak word line by comparing the selected word line corresponding to the address provided from the storage controller with the weak word line. Based on the comparison results, the programming mode is determined to be either the first programming mode or the second programming mode; as well as Based on the aforementioned programming mode, a programming operation is performed to store data in a selected memory cell connected to the selected word line. The information regarding the weak word line includes information determined by comparing a first pre-programming operation with a second pre-programming operation, wherein the first pre-programming operation applies a pre-charge voltage to the source line commonly connected to the plurality of memory cells and increases the threshold voltage of the plurality of memory cells, and the second pre-programming operation applies a ground voltage to the source line and increases the threshold voltage of the plurality of memory cells.

16. The method according to claim 15, wherein, The information regarding the weak word lines includes information about word lines connected to memory cells whose difference between the number of first cutoff cells identified by the first preprogramming operation and the number of second cutoff cells identified by the second preprogramming operation is greater than a reference number of cutoff cells.

17. The method according to claim 15, wherein, The step of determining the programming mode as either the first programming mode or the second programming mode includes the following steps: When the selected word line is a weak word line, the programming mode is determined as the first programming mode, and when the selected word line is a normal word line, the programming mode is determined as the second programming mode.

18. The method according to claim 17, wherein, The programming operations include multiple programming loops, and The number of programming cycles in which the precharge voltage is applied to the source line in the first programming mode is less than the number of programming cycles in which the precharge voltage is applied to the source line in the second programming mode.

19. The method according to claim 17, wherein, In the first programming mode, the channel regions of the plurality of memory cells are precharged for a shorter period of time than in the second programming mode.

20. The method of claim 17, wherein, The first programming mode includes applying an on-state voltage to an unselected word line among the plurality of word lines while the pre-charge voltage is applied to the source line, and The second programming mode includes applying a ground voltage to the remaining word lines of the plurality of word lines, excluding the selected word line and the word line adjacent to the selected word line, when the pre-charge voltage is applied to the source line.

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