Memory device and operating method thereof

Abstract

A memory device and an operating method thereof can be provided herein. The memory device can include a plurality of memory cells, a peripheral circuit configured to perform a verify operation that identifies threshold voltages of the plurality of memory cells using a first verify voltage and a second verify voltage, and a program operation controller configured to control the peripheral circuit to apply, after termination of the verify operation and during a period in which a program voltage is applied to the plurality of memory cells, a first control signal to a page buffer coupled with a first memory cell having a threshold voltage higher than the first verify voltage and lower than the second verify voltage, and a second control signal having a voltage level lower than the first control signal to the page buffer.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to electronic devices, and more specifically, to a memory device and a method of operating the memory device. Background Technology

[0002] Programming is an operation that increases the threshold voltage of a memory cell. Because the physical characteristics of memory cells differ, the degree to which the threshold voltage of each memory cell increases during programming varies. Therefore, in order to form a threshold voltage distribution of memory cells with the same programming state as the target programming state in a narrow shape during programming, the memory device applies voltages of different magnitudes to the bit lines based on the magnitude of the corresponding threshold voltage of the memory cells. However, as the spacing between the lines used for bit line routing becomes increasingly smaller, coupling phenomena attributable to parasitic capacitances between the bit lines may occur when voltages of different magnitudes are applied to the bit lines. Furthermore, when coupling occurs between bit lines, the voltage applied to the bit lines may not increase to the desired level. Summary of the Invention

[0003] Embodiments of this disclosure may provide a memory device. The memory device may include: a plurality of memory cells; peripheral circuitry configured to perform a verification operation that identifies a threshold voltage of the plurality of memory cells using a first verification voltage and a second verification voltage, the second verification voltage being higher than the first verification voltage; and a programming operation controller configured to control the peripheral circuitry, after the verification operation terminates and during a period when a programming voltage is applied to the plurality of memory cells, to apply a first control signal having a first voltage magnitude to a page buffer connected to a first memory cell among the plurality of memory cells, the first memory cell having a threshold voltage higher than the first verification voltage and lower than the second verification voltage, and to apply a second control signal having a second voltage magnitude lower than the first voltage magnitude to the page buffer.

[0004] Embodiments of this disclosure may provide a method for operating a memory device. The method may include the following steps: performing a verification operation to identify threshold voltages of a plurality of memory cells using a first verification voltage and a second verification voltage, the second verification voltage being higher than the first verification voltage; after the verification operation terminates and during a period when a programming voltage is applied to the plurality of memory cells: applying a first control signal having a first voltage magnitude to a page buffer connected to a first memory cell among the plurality of memory cells, the first memory cell having a threshold voltage higher than the first verification voltage and lower than the second verification voltage; and applying a second control signal having a second voltage magnitude lower than the first voltage magnitude to the page buffer connected to the first memory cell. Attached Figure Description

[0005] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0006] Figure 2 It is shown Figure 1 A diagram of the structure of a memory device.

[0007] Figure 3 It is shown Figure 2 A diagram showing the structure of any one of the multiple storage blocks BLK1 to BLKz.

[0008] Figure 4 This is a graph showing the threshold voltage distribution of memory cells based on the programming operations of the memory device.

[0009] Figure 5 This is a diagram illustrating the programming operations of a memory device.

[0010] Figure 6 This is a diagram illustrating the DPGM operation of a memory device.

[0011] Figure 7 This is a diagram illustrating the operation of a page buffer circuit according to an embodiment of the present disclosure.

[0012] Figure 8 This is a diagram illustrating the application of programming voltage during the programming operation of a memory device.

[0013] Figure 9 This is a diagram illustrating the application of a programming voltage during the programming operation of a memory device according to an embodiment of the present disclosure.

[0014] Figure 10 This is a flowchart illustrating programming operations according to embodiments of the present disclosure.

[0015] Figure 11 This is a block diagram illustrating a memory card system to which a memory system according to an embodiment of the present disclosure is applied.

[0016] Figure 12 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0017] The specific structural or functional descriptions of the embodiments of this disclosure described in this specification or application are provided as examples to illustrate implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be practiced in various forms and should not be construed as limited to the implementations described in this specification or application.

[0018] Various embodiments of this disclosure relate to a memory device capable of improving the threshold voltage distribution of memory cells during programming operations and a method of operating the memory device.

[0019] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0020] Reference Figure 1 The memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a device for storing data under the control of a host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0021] Based on the host interface, which serves as a communication scheme with the host 300, the memory system 50 can be manufactured as any of a variety of storage devices. For example, the memory system 50 can be implemented as any of a variety of storage devices, such as solid-state drives (SSDs), multimedia cards such as MMC, embedded MMC (eMMC), reduced-size MMC (RS-MMC) or micro-MMC, secure digital cards such as SD, mini-SD or micro-SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, compact flash memory (CF) cards, smart media cards, and memory sticks.

[0022] The memory system 50 can be manufactured in any of a variety of package types. For example, the memory system 50 can be manufactured in any of a variety of package types such as POP, SIP, SOC, MCP, COB, WFP, and WSP.

[0023] The memory device 100 can store data. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) comprising a plurality of memory cells for storing data.

[0024] Each memory cell can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0025] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or a unit for retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0026] In embodiments, the memory device 100 may be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). For ease of description, this specification assumes that the memory device 100 is NAND flash memory.

[0027] The memory device 100 can receive commands and addresses from the memory controller 200 and can access address-selected regions in the memory cell array. The memory device 100 can perform operations indicated by commands on the address-selected regions. For example, the memory device 100 can perform write operations (i.e., programming operations), read operations, and erase operations. During a write operation, the memory device 100 can program data into the address-selected regions. During a read operation, the memory device 100 can read data from the address-selected regions. During an erase operation, the memory device 100 can erase data stored in the address-selected regions.

[0028] In one embodiment, the memory device 100 may include a programming operation controller 140.

[0029] The programming operation controller 140 controls programming operations performed on memory cells. A programming operation can be an operation that stores data in a memory cell. Specifically, a programming operation can be an operation that increases the threshold voltage of a memory cell based on the data to be stored in the memory cell. When a programming operation is performed, each memory cell can have a threshold voltage corresponding to any of a plurality of programming states. The plurality of programming states can be defined based on the number of data bits stored in a memory cell. For example, when data is programmed according to a three-level cell (TLC) scheme where three bits are stored in a memory cell, the plurality of programming states can indicate an erase state and first to seventh programming states. After the programming operation is performed, the threshold voltage of the memory cell can be determined based on the data to be stored in the memory cell. Based on the data to be stored in the corresponding memory cell, each memory cell can have any of a plurality of programming states as the target programming state.

[0030] In this implementation, the programming operation may include multiple programming cycles. Each programming cycle may include a programming voltage application operation and a verification operation. The programming voltage application operation may be an operation of increasing the threshold voltage of the memory cell using a programming voltage. The verification operation may be an operation of using a verification voltage to identify whether the threshold voltage of the memory cell has reached the threshold voltage corresponding to the target programming state.

[0031] The programming operation controller 140 can determine the voltage to be applied to the bit line connected to the memory cell during the programming voltage application operation based on the threshold voltage of the memory cell identified using the verification voltage. For example, during the verification operation, when the threshold voltage of the memory cell has a voltage higher than the verification voltage corresponding to the target programming state, the memory cell can be identified as having reached the target programming state. Memory cells with a threshold voltage corresponding to the target programming state can prevent their threshold voltage from increasing further. Here, during the programming voltage application operation, the programming operation controller 140 can apply a programming disable voltage to the bit line connected to the memory cell with a threshold voltage corresponding to the target programming state. In the example, during the verification operation, when the threshold voltage of the memory cell is lower than the verification voltage corresponding to the target programming state, the memory cell can be identified as not yet having reached the target programming state. The threshold voltage of memory cells whose threshold voltage has not yet reached the threshold voltage corresponding to the target programming state should be increased further. Here, during the programming voltage application operation, the programming operation controller 140 can apply a programming enable voltage to the bit line connected to the memory cell that does not have a threshold voltage corresponding to the target programming state.

[0032] In this implementation, the verification operation may be an operation that uses multiple verification voltages to identify the threshold voltage of a memory cell. The programming operation controller 140 may determine the magnitude of the voltage to be applied to the bit line connected to the memory cell during the programming voltage application operation based on the magnitude of the threshold voltage of the memory cell identified using the multiple verification voltages. For example, in a dual-verification PGM (DPGM) operation using two verification voltages to identify the threshold voltage of the memory cell, during the programming voltage application operation, a programming enable voltage may be applied to the bit line connected to a memory cell having a threshold voltage lower than the pre-verification voltage. During the programming voltage application operation, a pre-charge voltage may be applied to the bit line connected to a memory cell having a threshold voltage higher than the pre-verification voltage but lower than the main verification voltage. The magnitude of the main verification voltage may be greater than the magnitude of the pre-verification voltage. The main verification voltage may be a threshold voltage corresponding to a target programming state of the memory cell. The pre-charge voltage may be greater than the magnitude of the programming enable voltage.

[0033] The storage controller 200 controls the overall operation of the storage system 50.

[0034] When power is applied to the memory system 50, the memory controller 200 can run firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300, a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0035] In this embodiment, the storage controller 200 may receive data and logical block addresses (LBAs) from the host 300, and may convert the logical block addresses (LBAs) into physical block addresses (PBAs) that indicate the addresses of memory cells included in the memory device 100 and for which data is to be stored. In this specification, the terms "logical block address (LBA)" and "logical address" are used interchangeably. In this specification, the terms "physical block address (PBA)" and "physical address" are used interchangeably.

[0036] The storage controller 200 can control the storage device 100 to perform write, read, or erase operations in response to a request received from the host 300. During a write operation, the storage controller 200 can provide a write command, a physical block address, and data to the storage device 100. During a read operation, the storage controller 200 can provide a read command and a physical block address to the storage device 100. During an erase operation, the storage controller 200 can provide an erase command and a physical block address to the storage device 100.

[0037] In this implementation, the storage controller 200 can internally generate commands, addresses, and data regardless of whether a request is received from the host 300, and can send the commands, addresses, and data to the storage device 100. For example, the storage controller 200 can provide the storage device 100 with the necessary commands, addresses, and data to perform read and write operations involved in the execution of wear leveling, read recycling, garbage collection, etc.

[0038] In one implementation, the memory controller 200 may control two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 based on an interleaving scheme to improve operational performance. The interleaving scheme may be a scheme for controlling the memory devices 100 such that the operation of at least two memory devices 100 overlaps with each other.

[0039] The host 300 may communicate with the memory system 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Loaded DIMM (LRDIMM).

[0040] In an implementation, memory system 50 may include buffer memory (not shown). For example, buffer memory may temporarily store data received from host 300 or memory device 100, or may temporarily store metadata of memory device 100 (e.g., a mapping table). Buffer memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0041] Figure 2 It is shown Figure 1 A diagram of the structure of a memory device.

[0042] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0043] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 121 via row lines RL. The memory blocks BLK1 to BLKz are connected to the page buffer group 123 via bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include multiple memory cells. In embodiments, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells are defined as a physical page. In other words, the memory cell array 110 may include multiple pages. In embodiments of this disclosure, each of the memory blocks BLK1 to BLKz included in the memory cell array 110 may include multiple dummy cells. For a dummy cell, one or more dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0044] Each memory cell of the memory device 100 can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0045] Peripheral circuitry 120 can drive memory cell array 110. In this example, under the control of control logic 130, peripheral circuitry 120 can drive memory cell array 110 to enable programming, reading, and erasing operations. In this example, under the control of control logic 130, peripheral circuitry 120 can apply various operating voltages to row lines RL and bit lines BL1 to BLm, or can discharge the applied voltages.

[0046] The peripheral circuitry 120 may include an address decoder 121, a voltage generator 122, a page buffer group 123, a data input / output circuit 124, and a sensing circuit 125.

[0047] Address decoder 121 can be connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments of this disclosure, row lines RL may also include transistor select lines.

[0048] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 can receive address ADDR from control logic 130.

[0049] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 can select at least one of the memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address RADD in the received address ADDR. Address decoder 121 can select at least one word line WL of the selected memory block by applying a voltage supplied from voltage generator 122 to at least one word line WL based on the decoded row address RADD.

[0050] During programming operations, address decoder 121 may apply a programming voltage to the selected word line and a pass voltage of a level lower than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 may apply a verification voltage to the selected word line and a verification pass voltage of a level higher than the verification voltage to the unselected word line.

[0051] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and can apply a read pass voltage of a higher level than the read voltage to the unselected word line.

[0052] The erase operation of memory device 100 can be performed on a block-by-block basis. During the erase operation, the address ADDR input to memory device 100 may include a block address. Address decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, address decoder 121 may apply a ground voltage to the word line connected to the selected memory block.

[0053] Address decoder 121 can decode the column address in the received address ADDR. The decoded column address can be transmitted to page buffer set 123. In an embodiment, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0054] Voltage generator 122 can use the external power supply voltage supplied to memory device 100 to generate multiple operating voltages Vop. Voltage generator 122 can operate under the control of control logic 130.

[0055] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 can be used as the operating voltage of the memory device 100.

[0056] In this implementation, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. Voltage generator 122 can use either an external or internal power supply voltage to generate multiple operating voltages Vop. Voltage generator 122 can generate various voltages required by the memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0057] The voltage generator 122 may include multiple pump capacitors that receive an internal power supply voltage to generate multiple operating voltages Vop with various voltage levels, and multiple operating voltages Vop can be generated by selectively enabling the multiple pump capacitors under the control of control logic 130.

[0058] The generated operating voltage Vop can be supplied to the memory cell array 110 through the address decoder 121.

[0059] Page buffer group 123 includes first page buffer PB1 to m-th page buffer PBm. First page buffer PB1 to m-th page buffer PBm can be connected to memory cell array 110 via first bit line BL1 to m-th bit line BLm respectively. First page buffer PB1 to m-th page buffer PBm can operate under the control of control logic 130.

[0060] Page buffers PB1 through PBm can send / receive data DATA to / from data input / output circuit 124. During programming operations, page buffers PB1 through PBm can receive the data DATA to be stored via data input / output circuit 124 and data line DL.

[0061] During programming operations, when a programming pulse is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA to be stored, received via the data input / output circuit 124, to the selected memory cell via bit lines BL1 to BLm. The memory cell in the selected page can be programmed based on the received data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm can read the data DATA stored in the selected memory cell via bit lines BL1 to BLm.

[0062] During a read operation, page buffer group 123 can read data DATA from the memory cell in the selected page via bit lines BL1 to BLm, and can store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0063] During an erase operation, page buffer group 123 may allow bit lines BL1 to BLm to float. In one embodiment, page buffer group 123 may include column select circuitry.

[0064] In one implementation, when data stored in some of the multiple page buffers included in the page buffer group 123 is programmed into the memory cell array 110, the remaining page buffers can receive new data from the memory controller 200 and then store the new data.

[0065] The data input / output circuit 124 can be connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 can operate under the control of the control logic 130.

[0066] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives data DATA to be stored from an external controller (not shown). During read operations, the data input / output circuit 124 may output data DATA received from the first page buffer PB1 to the m-th page buffer PBm included in the page buffer group 123 to the external controller.

[0067] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current. In the example, when the magnitude of the sensed voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 can output a pass signal to the control logic 130. In the example, when the magnitude of the sensed voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 can output a failure signal to the control logic 130.

[0068] Control logic 130 can be connected to address decoder 121, voltage generator 122, page buffer group 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 controls the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0069] Control logic 130 can control peripheral circuitry 120 by generating various types of signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, page buffer control signal PBSIGNALS to page buffer group 123, and enable bit VRYBIT to sensing circuit 125. Additionally, control logic 130 can determine whether the verification operation passed or failed in response to pass signal PASS or failure signal FAIL output from sensing circuit 125.

[0070] Figure 1 The programmable operation controller 140 shown may be included in Figure 2 The control logic 130 shown.

[0071] The programming operation controller 140 controls the peripheral circuitry 120 to apply the operating voltage to be used during programming operations to the row lines RL and bit lines BL1 to BLm. The programming operation controller 140 can determine the voltage to be applied to the bit lines connected to the memory cells during programming voltage application operations based on the threshold voltage of the memory cells identified as a result of a verification operation. In one embodiment, the programming operation controller 140 can provide the page buffer group 123 with a page buffer control signal PBSIGNALS required to apply programming enable voltage, precharge voltage, and programming disable voltage to the bit lines connected to the memory cells, based on the threshold voltage of the memory cells. Each of the page buffers PB1 to PBm included in the page buffer group 123 can increase the potential of the corresponding bit line to the programming enable voltage, precharge voltage, or programming disable voltage in response to the page buffer control signal PBSIGNALS received from the control logic 130.

[0072] Figure 3 It is shown Figure 2 A diagram showing the structure of any one of the multiple storage blocks BLK1 to BLKz.

[0073] Storage block BLKi can indicate Figure 2 The storage block BLKi shown is any one of the storage blocks BLK1 to BLKz.

[0074] Reference Figure 3Multiple word lines arranged in parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). Specifically, the memory block BLKi may include multiple serial lines (STs) connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be individually connected to serial lines ST, and the source line SL can be collectively connected to serial lines ST. Serial lines ST can be configured equivalently; therefore, a serial line ST connected to the first bit line BL1 will be described in detail as an example.

[0075] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A single string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include more memory cells than the memory cells MC1 to MC16 shown in the figure.

[0076] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, and the gate of the drain select transistor DST included in different string STs can be connected to the drain select line DSL. The gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16 respectively. A group of memory cells included in different string STs and connected to the same word line can be referred to as a "physical page (PG)". Therefore, the memory block BLKi can include the same number of physical pages (PG) as the number of word lines WL1 to WL16.

[0077] A memory cell can store one bit of data. This cell is typically designated as a "single-level cell (SLC)". In this case, a physical page (PG) can store the data corresponding to a logical page (LPG). The data corresponding to a logical page (LPG) can include the same number of data bits as the number of cells included in a physical page (PG).

[0078] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store data corresponding to two or more logical pages (LPG).

[0079] Figure 4 This is a graph showing the threshold voltage distribution of memory cells based on the programming operations of the memory device.

[0080] exist Figure 4In the graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells (cell count).

[0081] Reference Figure 4 The threshold voltage distribution of memory cells can be changed from the initial state to the final programmed state based on programming operations.

[0082] exist Figure 4 The text describes the programming of data under the assumption that the data is stored in a TLC scheme with three bits of data stored in a single memory cell.

[0083] The initial state can be a state where no programming operation is performed and the threshold voltage distribution of the memory cell is in the erase state E.

[0084] The final programming state can be the threshold voltage distribution of the memory cells performing the programming operation. Each memory cell performing the programming operation can have a threshold voltage corresponding to any of a plurality of programming states. For example, when programming data according to a three-level cell (TLC) scheme where three bits of data are stored in one memory cell, the plurality of programming states can indicate an erase state E and first programming states PV1 to seventh programming states PV7. In an embodiment, each memory cell performing the programming operation can have a threshold voltage corresponding to any of the first programming states PV1 to seventh programming states PV7 or erase state E. The threshold voltage of each memory cell in the initial state can be increased by the programming operation to the threshold voltage corresponding to any of the first programming states PV1 to seventh programming states PV7 or erase state E.

[0085] Each memory cell can have any one of the programming states PV1 to PV7 or an erase state E as the target programming state. The target programming state can be determined based on the data to be stored in the corresponding memory cell. Through appropriate programming operations, the memory cell can have a threshold voltage corresponding to the target programming state in the final programming state.

[0086] Figure 5 This is a diagram illustrating the programming operations of a memory device.

[0087] exist Figure 5 In the graph, the horizontal axis indicates time, and the vertical axis indicates the voltage V applied to the word line. The voltage V applied to the word line can include the programming voltage Vpgm and the verification voltage V_vfy.

[0088] exist Figure 5 The present disclosure is described under the assumption that data is programmed using a TLC scheme that stores three bits of data in a single memory cell. However, the scope of this disclosure is not limited thereto, and a single memory cell may be programmed to store two or fewer bits of data or four or more bits of data.

[0089] Reference Figure 5 The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. By executing the multiple programming cycles PL1 to PLn, the memory device 100 can perform programming operations such that each selected memory cell connected to a selected word line has a threshold voltage corresponding to any of a plurality of programming states. For example, when a single memory cell is programmed according to a TLC scheme, by executing the multiple programming cycles PL1 to PLn, the memory device 100 can perform programming operations such that the memory cell has a threshold voltage corresponding to any of the erase state E and the first programming states PV1 to the seventh programming states PV7.

[0090] Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step).

[0091] The programming voltage application operation (PGM step) can be an operation that applies a programming voltage to a selected word line connected to a selected memory cell. For example, memory device 100 may apply a first programming voltage Vpgm1 to the selected word line connected to the selected memory cell in a first programming cycle PL1. After the first programming voltage Vpgm1 is applied to the selected word line, the corresponding threshold voltage for the selected memory cell may be a threshold voltage corresponding to a target programming state among a plurality of programming states.

[0092] A verification operation (verification step) can be an operation of applying a verification voltage to a selected word line connected to a selected memory cell. A verification operation (verification step) can be an operation of determining whether the corresponding threshold voltage of the selected memory cell is the threshold voltage corresponding to a target programming state among multiple programming states. A verification operation (verification step) can be an operation of applying a verification voltage corresponding to the corresponding target programming state of the selected memory cell.

[0093] In this implementation, during the first programming cycle PL1, after the first programming voltage Vpgm1 is applied to the selected word line connected to the selected memory cell, the memory device 100 may apply first verification voltages V_vfy1 to seventh verification voltages V_vfy7 to the selected word line. In this case, the first verification voltage V_vfy1 can be used to perform a verification operation (verification step) on a memory cell having a first programming state as the target programming state. The second verification voltage V_vfy2 can be used to perform a verification operation (verification step) on a memory cell having a second programming state as the target programming state. The third verification voltage V_vfy3 can be used to perform a verification operation (verification step) on a memory cell having a third programming state as the target programming state. The fourth verification voltage V_vfy4 can be used to perform a verification operation (verification step) on a memory cell having a fourth programming state as the target programming state. The fifth verification voltage V_vfy5 can be used to perform a verification operation (verification step) on a memory cell having a fifth programming state as the target programming state. The sixth verification voltage V_vfy6 can be used to perform a verification operation (verification step) on a memory cell having a sixth programming state as the target programming state. A verification operation (verification step) can be performed on a memory cell with a seventh programming state as the target programming state using a seventh verification voltage V_vfy7. The magnitudes of the verification voltages V_vfy1 to V_vfy7 can be increased from the first verification voltage V_vfy1 to the seventh verification voltage V_vfy7. Specifically, for the magnitudes of the verification voltages V_vfy1 to V_vfy7, the first verification voltage V_vfy1 can be the lowest, and the seventh verification voltage V_vfy7 can be the highest. However, the number of verification voltages is not limited to this embodiment.

[0094] It can be determined that the memory cells that have passed the verification operation (verification step) using the corresponding verification voltages V_vfy1 to V_vfy7 have a threshold voltage corresponding to the target programming state. The memory cells that have passed the verification operation (verification step) can be programmed disabled in the second programming cycle PL2. The programming disable voltage can be applied to the bit line connected to the programmed disabled memory cell.

[0095] It can be determined that memory cells for which verification steps using the corresponding verification voltages V_vfy1 to V_vfy7 have failed do not have the threshold voltage corresponding to the target programming state. Memory cells for which verification steps have failed can execute the second programming cycle PL2.

[0096] In the second programming cycle PL2, the memory device 100 may apply a second programming voltage Vpgm2, which is a unit voltage ΔVpgm higher than the first programming voltage Vpgm1, to the selected word line connected to the selected memory cell. Thereafter, the memory device 100 may perform the verification operation (verification step) of the second programming cycle PL2 in the same manner as the verification operation (verification step) of the first programming cycle PL1.

[0097] Subsequently, the memory device 100 may execute subsequent programming cycles a preset number of times in the same manner as the second programming cycle PL2.

[0098] In this implementation, a programming operation may fail if it is not completed within a preset number of programming loops. A programming operation may succeed if it is completed within the preset number of programming loops. Whether a programming operation is complete can be determined based on whether all selected memory cells have passed a verification operation (verification step). If all selected memory cells have passed the verification operation (verification step), subsequent programming loops may not be executed.

[0099] In this implementation, the programming voltage can be determined based on the Incremental Step Pulse Programming (ISPP) method. As programming cycles PL1 to PLn repeat, the level of the programming voltage can be increased or decreased in stages (i.e., by step voltage). The number of times the programming voltage is applied, the voltage level of the programming voltage, the voltage application time, etc., used in each programming cycle can be determined in various forms under the control of the storage controller 200.

[0100] Figure 6 This is a diagram illustrating the DPGM operation of a memory device.

[0101] exist Figure 6 In the graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells (cell count).

[0102] Reference Figure 6 Dual Validation PGM (DPGM) operation can be an operation that uses two or more validation voltages to identify the threshold voltage of a memory cell during a validation operation. Specifically, DPGM operation can be an operation that uses two or more validation voltages to verify whether the threshold voltage of a memory cell has reached the threshold voltage corresponding to the target programming state. The two or more validation voltages may include a pre-validation voltage Vvfyp and a main validation voltage Vvfym.

[0103] Figure 6 The programming state P shown can be Figure 4 Any one of the first programming states PV1 to the seventh programming state PV7 shown. Figure 5Each of the verification voltages V_vfy1 to V_vfy7 shown may include a pre-verification voltage Vvfyp and a main verification voltage Vvfym.

[0104] In this implementation, the main verification voltage Vvfym can be a threshold voltage corresponding to the programming state P. The main verification voltage Vvfym can also be a threshold voltage corresponding to the target programming state of the memory cell. For example, the main verification voltage Vvfym can be... Figure 5 The verification voltages shown are any one of V_vfy1 to V_vfy7.

[0105] In an implementation, the threshold voltage of the memory cell at which the programming voltage application operation terminates in any of the plurality of programming cycles can be the threshold voltages of the first cell (Cell1) through the third cell (Cell3). During a verification operation performed after the programming voltage application operation terminates, the memory device 100 may perform a DPGM operation to identify the threshold voltage of the memory cell using a pre-verification voltage Vvfyp and a main verification voltage Vvfym. During the verification operation, the memory device 100 may perform a DPGM operation to identify the degree of increase in the threshold voltage of the memory cell using the pre-verification voltage Vvfyp and the main verification voltage Vvfym.

[0106] In this implementation, after the programming voltage application operation terminates in any programming cycle, the first cell, Cell1, may have a threshold voltage lower than the pre-verification voltage Vvfyp. The second cell, Cell2, may have a threshold voltage higher than the pre-verification voltage Vvfyp and lower than the main verification voltage Vvfym. The third cell, Cell3, may have a threshold voltage higher than the main verification voltage Vvfym.

[0107] In the implementation, the target programming state for the first cell (Cell1) to the third cell (Cell3) is: Figure 6 The description is based on the assumption of the programming state P shown. That is, the threshold voltages of the first cell (Cell1) to the third cell (Cell3) can be increased to the threshold voltages corresponding to the programming state P.

[0108] During the programming voltage application operation, the threshold voltage of the first cell, Cell 1, can increase further towards the threshold voltage corresponding to the programming state P compared to the threshold voltage of the second cell, Cell 2. Here, the first cell, Cell 1, can be the cell to be programmed (PGM cell). Compared to the threshold voltage of the first cell, Cell 2, the threshold voltage of the second cell can increase less towards the threshold voltage corresponding to the programming state P. Here, the second cell, Cell 2, can be a DPGM cell. Since the threshold voltage of the third cell, Cell 3, already has the threshold voltage corresponding to the programming state P, the threshold voltage may no longer increase. Here, the third cell, Cell 3, can be a disable cell.

[0109] That is, after the programming voltage application operation terminates, the degree to which the threshold voltages of the first cell (Cell1) to the third cell (Cell3) increase can differ from each other. Furthermore, during the verification operation, the degree to which the threshold voltages of the first cell (Cell1) to the third cell (Cell3) increase can be identified using the pre-verification voltage Vvfyp and the main verification voltage Vvfym. Subsequently, during repeated programming voltage application operations, the magnitude of the voltage applied to the corresponding bit lines connected to the first cell (Cell1) to the third cell (Cell3) can be determined based on the magnitude of the threshold voltages of the first cell (Cell1) to the third cell (Cell3).

[0110] Figure 7 This is a diagram illustrating the operation of a page buffer circuit according to an embodiment of the present disclosure.

[0111] Figure 7 The page buffer circuit 700 shown can be Figure 2 Any one of the page buffers PBi included in the page buffer group 123 shown.

[0112] Reference Figure 7 The page buffer circuit 700 may include a precharger 710, a discharger 720, and a latch assembly 730. The precharger 710, discharger 720, and latch assembly 730 may be connected between bit line BL and data line DL. Bit line BL may be connected to a memory cell. Data corresponding to the target programming state of the memory cell can be input via data line DL.

[0113] The precharger 710 can precharge the voltage of bit line BL during programming voltage application operation. In one embodiment, when the memory cell connected to bit line BL is a programmable cell (PGM cell), the precharger 710 can apply a programming enable voltage to bit line BL. The programming enable voltage can be a ground voltage. When the memory cell connected to bit line BL is a disabled cell, the precharger 710 can apply a programming disable voltage to bit line BL. The programming disable voltage can be a power supply voltage. When the memory cell connected to bit line BL is a DPGM cell, the precharger 710 can apply a precharge voltage to bit line BL. The precharge voltage can be lower than the programming disable voltage and higher than the programming enable voltage. The precharger 710 can respond to... Figure 1The programming operation controller 140 shown increases the voltage of bit line BL upon receiving a precharge control signal PBSENSE. For example, the voltage of bit line BL may increase to a precharge voltage in response to the precharge control signal PBSENSE. Specifically, the degree of voltage increase in bit line BL may vary depending on the magnitude of the precharge control signal PBSENSE. The greater the magnitude of the precharge control signal PBSENSE, the greater the degree of voltage increase in bit line BL. In this embodiment, the precharge control signal PBSENSE may be from... Figure 2 The control logic 130 provides any one of the page buffer control signals PBSIGNALS to the page buffer group 123.

[0114] The discharger 720 can reduce the voltage of bit line BL to ground voltage. In one embodiment, the discharger 720 can discharge the potential of bit line BL, which has been increased to the programming disable voltage or precharge voltage, to ground voltage.

[0115] The latch component 730 can store data corresponding to a threshold voltage of a memory cell identified using multiple verification voltages. The latch component 730 can also store data obtained by sensing the potential change of the bit line when a corresponding verification voltage is applied to the memory cell connected to the bit line BL. In one embodiment, the latch component 730 can store data identifying whether the memory cell connected to the bit line BL is a programmable cell (PGM cell), a DPGM cell, or a disabled cell.

[0116] Figure 8 This is a diagram illustrating the application of programming voltage during the programming operation of a memory device.

[0117] Reference Figure 8 The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step).

[0118] The programming voltage application step (PGM step) included in each of the multiple programming cycles PL1 to PLn may include a precharge period, a programming pulse period (Pgm Pulse), and a discharge period.

[0119] The period from t1 to t2 can be a precharge period. The precharge period can be the period during which bit line BL is precharged. During the precharge period, the precharge control signal PBSENSE can rise to a first control voltage Vpb1. The voltage of bit line BL (inhibit cell) connected to the inhibit cell can increase to the programming inhibit voltage VCC in response to the precharge control signal PBSENSE. During the precharge period, the memory device 100 can apply a programming enable voltage Gnd to bit line BL (PGM cell) connected to the cell to be programmed. Afterward, the precharge control signal PBSENSE can drop from the first control voltage Vpb1 to ground. Here, bit line BL (inhibit cell) connected to the inhibit cell and bit line BL (PGM cell) connected to the cell to be programmed can be floated. The voltage of bit line BL (inhibit cell) connected to the inhibit cell and bit line BL (PGM cell) connected to the cell to be programmed can be maintained.

[0120] The time period from t2 to t3 can be the programmed pulse period Pgm Pulse. During the programmed pulse period Pgm Pulse, Figure 5 The programming voltages Vpgm1 to Vpgmn shown can be applied to the selected word line Sel_WL connected to the selected memory cell. The programming pulse period Pgm Pulse can be the period during which data is stored in the selected memory cell. For example, during the programming pulse period Pgm Pulse, the memory device 100 may apply a voltage Vpass to the selected word line Sel_WL connected to the selected memory cell for a preset time, and then apply the programming voltage Vpgm to the selected word line Sel_WL. During the programming pulse period Pgm Pulse, the memory device 100 may maintain the voltage of the bit line BL (PGM cell) connected to the cell to be programmed at the ground voltage Gnd. During the programming pulse period Pgm Pulse, the memory device 100 may maintain the voltage of the bit line BL (inhibit cell) connected to the inhibit cell at the programming inhibit voltage VCC.

[0121] During the programming pulse period Pgm Pulse, the precharge control signal PBSENSE can rise to the second control voltage Vpb2. The potential of the bit line BL (DPGM cell) connected to the DPGM cell can increase in response to the precharge control signal PBSENSE. Specifically, the voltage of the bit line BL (DPGM cell) connected to the DPGM cell can increase to either a first precharge voltage Vm1 or a second precharge voltage Vm2. In the example, when the memory cell adjacent to the DPGM cell is an inhibited cell, the voltage of the bit line BL (DPGM cell) connected to the DPGM cell can increase to the first precharge voltage Vm1. In the example, when the memory cell adjacent to the DPGM cell is a programmable cell (PGM cell), the voltage of the bit line BL (DPGM cell) connected to the DPGM cell can increase to the second precharge voltage Vm2. The first precharge voltage Vm1 can be higher than the second precharge voltage Vm2.

[0122] The potential of bit line BL (DPGM cell) connected to the DPGM cell can be increased to the target level TBL due to the second control voltage Vpb2. However, due to the coupling phenomenon caused by the parasitic capacitance between bit line BL (DPGM cell) and its adjacent bit lines, the voltage of bit line BL (DPGM cell) connected to the DPGM cell may not increase to the target level TBL. In this case, when the memory cell adjacent to the DPGM cell is a programmable cell (PGM cell), the aforementioned coupling phenomenon caused by parasitic capacitance may be more severe than in the case of a disabled cell. Therefore, the magnitude of the increased voltage of bit line BL (DPGM cell) connected to the DPGM cell can vary based on the degree to which the threshold voltage of the memory cell connected to the bit line adjacent to bit line BL (DPGM cell) connected to the DPGM cell needs to be increased. In detail, the magnitude of the increased voltage on the bit line BL (DPGM cell) connected to the DPGM cell can vary depending on whether the memory cell connected to the bit line adjacent to the bit line connected to the DPGM cell is a programmable cell (PGM cell) or a disabled cell.

[0123] The period from t3 to t4 can be a discharge period. During the discharge period, the memory device 100 can apply a ground voltage Gnd to the selected word line Sel_WL. During the discharge period, the memory device 100 can apply the ground voltage Gnd to the bit line BL (PGM cell) connected to the cell to be programmed, the bit line BL (inhibit cell) connected to the inhibit cell, and the bit line BL (DPGM cell) connected to the DPGM cell.

[0124] Figure 9 This is a diagram illustrating the application of a programming voltage during the programming operation of a memory device according to an embodiment of the present disclosure.

[0125] Figure 9 Lieutenant General (omitted) Figure 8 The configuration is the same as the repeated description of the configuration.

[0126] Reference Figure 9 The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step).

[0127] The programming voltage application step (PGM step) included in each of the multiple programming cycles PL1 to PLn may include a precharge period, a programming pulse period Pgm Pulse, and a discharge period Discharge.

[0128] The period from t1 to t2 can be a pre-charging period. The pre-charging period can be the period during which the bit line BL is pre-charged.

[0129] The time period from t2 to t3 can be the programming pulse period Pgm Pulse. During the programming pulse period Pgm Pulse, the precharge control signal PBSENSE can rise to the second-1 control voltage Vpb2-1. The precharge control signal PBSENSE can rise to the second-1 control voltage Vpb2-1 within a preset time period, and then decrease to the second-2 control voltage Vpb2-2. The second-1 control voltage Vpb2-1 can be lower than the first control voltage Vpb1. The second-1 control voltage Vpb2-1 can be higher than the second control voltage Vpb2, such as... Figure 8 As shown. The voltage of bit line BL (DPGM unit) connected to the DPGM unit can increase to a first pre-charge voltage Vm1 or a second pre-charge voltage Vm2 in response to the pre-charge control signal PBSENSE. Specifically, when the bit line adjacent to bit line BL (DPGM unit) connected to the DPGM unit is bit line BL (inhibit unit) connected to an inhibit unit, bit line BL (DPGM unit) connected to the DPGM unit can increase to the first pre-charge voltage Vm1 in response to the pre-charge control signal PBSENSE. That is, due to the second-first control voltage Vpb2-1, the voltage of bit line BL (DPGM unit) connected to the DPGM unit can reach the target level TBL. Furthermore, due to the second-first control voltage Vpb2-1, the voltage of bit line BL (DPGM unit) connected to the DPGM unit can reach a higher voltage than the voltage of bit line BL (DPGM unit). Figure 8The first precharge voltage Vm1 reaches the target level TBL earlier and faster. When the bit line adjacent to the bit line BL (DPGM cell) connected to the DPGM cell is the bit line BL (PGM cell) connected to the cell to be programmed, the voltage of the bit line BL (DPGM cell) connected to the DPGM cell can increase to the second precharge voltage Vm2 in response to the precharge control signal PBSENSE. Figure 9 The second pre-charge voltage Vm2 shown can have a higher voltage than Figure 8 The voltage of the second precharge voltage Vm2 shown. That is, the memory device 100 can increase the voltage of the bit line BL (DPGM cell) connected to the DPGM cell to a voltage closer to the target level TBL by driving the precharge control signal PBSENSE. Furthermore, the memory device 100 can increase the voltage of the bit line BL (DPGM cell) connected to the DPGM cell to a voltage closer to the target level TBL by driving the precharge control signal PBSENSE. Figure 9 The difference between the magnitude of the first pre-charge voltage Vm1 and the magnitude of the second pre-charge voltage Vm2 shown can be less than Figure 8 The difference between the magnitude of the first pre-charge voltage Vm1 and the magnitude of the second pre-charge voltage Vm2 is shown. Additionally, the voltage on the bit line BL (DPGM cell) connected to the DPGM cell is increased to a voltage closer to the target level TBL, thus improving the threshold voltage distribution of the DPGM cell.

[0130] Figure 10 This is a flowchart illustrating programming operations according to embodiments of the present disclosure.

[0131] Reference Figure 10 In step S1001, the memory device 100 may use a first verification voltage and a second verification voltage to identify the threshold voltage of the memory cell. The second verification voltage may be higher than the first verification voltage.

[0132] In step S1003, the memory device 100 may apply a first control signal having a first voltage magnitude to a page buffer connected to a first memory cell having a threshold voltage higher than a first verification voltage and lower than a second verification voltage within a first time period. The first memory cell may be a DPGM cell. In an embodiment, the memory device 100 may apply the first control signal to the page buffer connected to the first memory cell, and then apply a programming voltage to the word line connected to the first memory cell.

[0133] In step S1005, when the threshold voltage of the second memory cell adjacent to the first memory cell is lower than the first verification voltage, the memory device 100 may apply a programming enable voltage to the bit line connected to the second memory cell. The second memory cell may be the cell to be programmed (PGM cell). In an embodiment, the memory device 100 may apply the programming enable voltage to the bit line connected to the second memory cell, and then apply a first control signal to the page buffer connected to the first memory cell.

[0134] In step S1007, the memory device 100 may apply a second control signal having a second voltage magnitude lower than the first voltage magnitude to the page buffer connected to the first memory cell.

[0135] Figure 11 This is a block diagram illustrating a memory card system to which a memory system according to an embodiment of the present disclosure is applied.

[0136] Reference Figure 11 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0137] Storage controller 2100 is coupled to memory device 2200. Storage controller 2100 can access memory device 2200. For example, storage controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Storage controller 2100 can provide an interface between memory device 2200 and host computer. Storage controller 2100 can run firmware for controlling memory device 2200. Storage controller 2100 can be configured according to the above reference. Figure 1 The memory controller 200 described is implemented in the same manner. The memory device 2200 can be implemented in accordance with the above reference. Figure 1 The memory device 100 described is implemented in the same manner.

[0138] In some implementations, the storage controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and error correction circuitry.

[0139] Storage controller 2100 can communicate with external devices via connector 2300. Storage controller 2100 can communicate with external devices (e.g., a host) based on specific communication standards or protocols. In embodiments, storage controller 2100 can communicate with external devices via at least one of various communication standards or protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe). In embodiments, connector 2300 can be defined by at least one of the aforementioned communication standards or protocols.

[0140] In implementations, the memory device 2200 may be implemented as any of a variety of non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0141] The storage controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the storage controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association: PCMCIA), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC), or universal flash memory (UFS).

[0142] Figure 12 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure.

[0143] Reference Figure 12 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0144] Application processor 4100 may run components, operating systems (OS), or user programs included in user system 4000. In some embodiments, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-chip (SoC).

[0145] Memory module 4200 can be used as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, application processor 4100 and memory module 4200 may be packaged based on a stacked package (POP) and then provided as a single semiconductor package.

[0146] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi. In some embodiments, network module 4300 may be included in application processor 4100.

[0147] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send data stored in storage module 4400 to application processor 4100. In embodiments, storage module 4400 can be implemented as a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In embodiments, storage module 4400 can be provided as a removable storage medium (i.e., a removable drive) such as a memory card or an external drive of user system 4000.

[0148] In an implementation, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above. Figure 1 The memory device 100 described herein operates in the same manner. The memory module 4400 can operate in accordance with the above-described reference. Figure 1 The memory system 50 described operates in the same manner.

[0149] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In embodiments, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0150] According to this disclosure, a memory device capable of improving the threshold voltage distribution of memory cells during programming operations and a method for operating the memory device are provided.

[0151] Cross-references to related applications

[0152] This application claims priority to Korean Patent Application No. 10-2022-0067450, filed with the Korean Intellectual Property Office on June 2, 2022, the full disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple memory units; An external circuit that performs a verification operation to identify threshold voltages of the plurality of memory cells using a first verification voltage and a second verification voltage, wherein the second verification voltage is higher than the first verification voltage; as well as A programming operation controller controls the peripheral circuitry after the verification operation terminates and during the period when a voltage and a programming voltage are sequentially applied to the word lines connected to the plurality of memory cells: When the pass voltage is applied to the word line, a first control signal having a first voltage magnitude is applied to a page buffer connected to a first memory cell among the plurality of memory cells, the first memory cell having a threshold voltage higher than the first verification voltage and lower than the second verification voltage, and When the programming voltage is applied to the word line, a second control signal with a second voltage magnitude lower than the first voltage magnitude is applied to the page buffer.

2. The memory device according to claim 1, wherein, The threshold voltage of the second memory cell adjacent to the first memory cell among the plurality of memory cells has a voltage lower than the first verification voltage, and The programming operation controller controls the peripheral circuit to apply a programming enable voltage to the bit line connected to the second memory cell after the verification operation is terminated.

3. The memory device according to claim 2, wherein, The programming operation controller controls the peripheral circuit to apply the programming enable voltage to the bit line connected to the second memory cell, and then applies the first control signal to the page buffer connected to the first memory cell.

4. The memory device according to claim 3, wherein, The programming operation controller controls the peripheral circuit to apply the first control signal to the page buffer connected to the first memory cell, and then applies the programming voltage to the word line connected to the plurality of memory cells.

5. The memory device according to claim 4, wherein, The voltage of the bit line connected to the first memory cell increases to the pre-charge voltage in response to the first control signal and the second control signal, and The precharge voltage has a higher voltage than the programming enable voltage.

6. The memory device according to claim 5, wherein, The programming enable voltage is the ground voltage.

7. The memory device according to claim 6, wherein, The second verification voltage is a threshold voltage corresponding to the target programming state of the plurality of memory cells.

8. The memory device according to claim 1, wherein, The threshold voltage of the second memory cell adjacent to the first memory cell among the plurality of memory cells has a voltage higher than the second verification voltage, and The programming operation controller controls the peripheral circuit to apply a programming disable voltage to the bit line connected to the second memory cell after the verification operation is terminated.

9. The memory device according to claim 8, wherein, The voltage of the bit line connected to the first memory cell increases to the pre-charge voltage in response to the first control signal and the second control signal, and The precharge voltage has a voltage lower than the programmed prohibition voltage.

10. The memory device according to claim 9, wherein, The programming-prohibited voltage is the power supply voltage.

11. A method of operating a memory device, the method comprising the steps of: A verification operation is performed to identify threshold voltages of multiple memory cells using a first verification voltage and a second verification voltage, wherein the voltage of the second verification voltage is higher than the voltage of the first verification voltage. After the verification operation is terminated and during the period when the voltage and programming voltage are sequentially applied to the word lines connected to the plurality of memory cells: When the pass voltage is applied to the word line, a first control signal having a first voltage magnitude is applied to a page buffer connected to a first memory cell among the plurality of memory cells, the first memory cell having a threshold voltage higher than the first verification voltage and lower than the second verification voltage; and When the programming voltage is applied to the word line, a second control signal having a second voltage magnitude lower than the first voltage magnitude is applied to the page buffer connected to the first memory cell.

12. The method according to claim 11, wherein, The threshold voltage of the second memory cell adjacent to the first memory cell is lower than the first verification voltage, and The method further includes the following steps: After the verification operation is terminated, a programming enable voltage is applied to the bit line connected to the second memory cell.

13. The method of claim 12, further comprising the step of: The programming enable voltage is applied to the bit line connected to the second memory cell, and then the first control signal is applied to the page buffer connected to the first memory cell.

14. The method of claim 13, further comprising the step of: The pass voltage is applied to the word line, and then the programming voltage is applied to the word line.

15. The method according to claim 14, wherein, The voltage of the bit line connected to the first memory cell increases to the pre-charge voltage in response to the first control signal and the second control signal, and The precharge voltage has a higher voltage than the programming enable voltage.

16. The method according to claim 15, wherein, The second verification voltage is a threshold voltage corresponding to the target programming state of the plurality of memory cells.

17. The method according to claim 11, wherein, The threshold voltage of the second memory cell adjacent to the first memory cell has a voltage higher than the second verification voltage, and The method further includes the following steps: After the verification operation is terminated, a programming disable voltage is applied to the bit line connected to the second memory cell.

18. The method according to claim 17, wherein, The voltage of the bit line connected to the first memory cell increases to the pre-charge voltage in response to the first control signal and the second control signal, and The precharge voltage has a voltage lower than the programmed prohibition voltage.

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