Inductive amplifier inductive boundary detection method and electronic device

Abstract

The present disclosure provides a sensing amplifier sensing boundary detection method and electronic equipment, the method comprising: writing first data and second data into a first storage unit and a second storage unit connected by a first bit line respectively, the first storage unit and the second storage unit being connected to adjacent first and second word lines respectively, the first bit line being connected to a first sensing amplifier; performing a reverse write operation on the first storage unit and the second storage unit; performing a write operation on a storage unit connected by a second bit line, the first word line and the second word line, the two adjacent write operations having a preset row precharge time, the second bit line being connected to a second sensing amplifier, the second sensing amplifier and the first sensing amplifier being located in the same sensing amplifier array; reading the second storage unit, and when the first data is not correctly read, determining that the preset row precharge time is a row precharge time boundary value of the first sensing amplifier. The embodiments of the present disclosure can accurately detect the sensing capability of the sensing amplifier.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit testing technology, and more specifically, to a method and electronic device for detecting the sensing boundary of an inductive amplifier. Background Technology

[0002] A sense amplifier (SA) is a differential amplifier with its two inputs connected to the bit line BL and the complementary bit line / BL, respectively. It amplifies the weak voltage difference between BL and / BL. As a crucial circuit in memory, the sense amplifier's ability to detect weak voltage differences—its sense margin—is a vital indicator of memory performance. Therefore, a method is needed to accurately detect the sense amplifier's sensing capability.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a method and electronic device for detecting the sensing boundary of an inductive amplifier, so as to improve the accuracy of detecting the sensing capability of the inductive amplifier.

[0005] According to a first aspect of this disclosure, a method for detecting the sensing boundary of an inductive amplifier is provided, comprising: writing first data and second data to a first storage cell and a second storage cell connected by a first bit line, respectively, wherein the first storage cell and the second storage cell are respectively connected to adjacent first word lines and second word lines, and the first bit line is connected to a first inductive amplifier; performing a reverse write operation on the first storage cell and the second storage cell, wherein the reverse write operation includes reversing the second data in the first storage cell and reversing the first data in the second storage cell; performing a write operation on a storage cell connected by a second bit line, the first word line, and the second word line, wherein there is a preset row precharge time between two adjacent write operations, wherein the second bit line is connected to a second inductive amplifier, and the second inductive amplifier and the first inductive amplifier are located in the same inductive amplifier array; reading the second storage cell, and when the first data is not read correctly, determining that the preset row precharge time is the row precharge time boundary value of the first inductive amplifier.

[0006] In an exemplary embodiment of this disclosure, there are multiple first bit lines, and the second bit line is the next first bit line after the currently operated first bit line. Writing first data and second data to the first and second storage units connected by the first bit line respectively includes: writing the first data and second data to the first and second storage units connected by multiple sets of first bit lines in a first order, wherein each set of first bit lines includes a first number of adjacent first bit lines, and the first order is determined according to the bit line number in the multiple sets of first bit lines from smallest to largest; the write operation to the storage units connected by the second bit line, the first word line, and the second word line includes: performing the reverse write operation on the first and second storage units connected by the second bit line, wherein the second bit line is one of the multiple first bit lines.

[0007] In one exemplary embodiment of this disclosure, before reading the second storage cell, the method further includes: performing the reverse write operation on the plurality of sets of first storage cells and second storage cells connected by first bit lines in a second order, the second order being the opposite of the first order.

[0008] In one exemplary embodiment of this disclosure, the method further includes: when the first data is correctly read in each of the second storage cells, reducing the preset row precharge time and re-detecting.

[0009] In one exemplary embodiment of this disclosure, during the reverse write operation, the write time of the first data is controlled to a preset write delay, so that the second storage unit experiences insufficient first data write.

[0010] In one exemplary embodiment of this disclosure, the first data is 1 and the second data is 0; or, the first data is 0 and the second data is 1.

[0011] In one exemplary embodiment of this disclosure, the first quantity is equal to the burst length of the storage array under test, and the storage array under test is the storage array containing the first storage cell and the second storage cell.

[0012] In one exemplary embodiment of this disclosure, the first storage unit and the second storage unit include all storage units connected to the bit lines corresponding to all the sensing amplifiers under test.

[0013] In one exemplary embodiment of this disclosure, all memory cells adjacent to the first memory cell on the same first bit line are the second memory cells.

[0014] In one exemplary embodiment of this disclosure, the first storage unit and the second storage unit are disposed on the same word line.

[0015] In one exemplary embodiment of this disclosure, one or more first storage cells are adjacent to each other on the same first bit line, one or more second storage cells are adjacent to each other, and at least one second storage cell is adjacent to the first storage cell.

[0016] In one exemplary embodiment of this disclosure, the first inductive amplifier is connected to a test voltage.

[0017] In one exemplary embodiment of this disclosure, when the first data is 1, the power supply voltage in the test voltage is lower than the power supply voltage when the memory array under test is operating normally; when the first data is 0, the ground voltage in the test voltage is higher than the ground voltage of the memory array under test.

[0018] According to a second aspect of this disclosure, an electronic device is provided, comprising: a memory; and a processor coupled to the memory, the processor being configured to perform the method as described in any one of the foregoing methods based on instructions stored in the memory.

[0019] According to a third aspect of this disclosure, a computer-readable storage medium is provided having a program stored thereon that, when executed by a processor, implements the method as described in any of the preceding claims.

[0020] This embodiment of the present disclosure writes different data to the first and second memory cells connected by the first bit line, first word line, and second word line of the first sensing amplifier, and performs write operations on the memory cells connected by the second bit line, first word line, and second word line that affect the operation of the first bit line. By reducing the row precharge time between write operations, the row precharge time corresponding to the first memory cell can be reduced when the first bit line and the second bit line work together. This results in the first bit line retaining the data influence of the first memory cell, reducing the sensing boundary of the first sensing amplifier to the second memory cell when the first bit line works together, increasing the probability of the first sensing amplifier failing to sense the second memory cell, and detecting the row precharge time boundary value of the first sensing amplifier more quickly, with higher detection efficiency.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the storage array under test in an exemplary embodiment of this disclosure.

[0023] Figure 2 This is a schematic diagram of the circuit structure of the inductive amplifier in an embodiment of this disclosure.

[0024] Figure 3A and Figure 3B This is through the embodiments disclosed herein. Figure 2 The circuit shown is a schematic diagram of the process of reading a memory cell.

[0025] Figure 4A yes Figure 3A This diagram illustrates the scenario where reading data "0" fails.

[0026] Figure 4B yes Figure 3B This diagram illustrates the scenario where reading the data "1" fails.

[0027] Figure 5 This is a flowchart of the inductive amplifier sensing boundary detection method in an embodiment of this disclosure.

[0028] Figures 6A to 6C This is a schematic diagram showing the arrangement of the first and second storage units.

[0029] Figure 7A and Figure 7B This is a schematic diagram of performing a reverse write operation on the first and second memory cells connected by multiple bit lines.

[0030] Figure 8 This is a schematic diagram of the reverse write operation in an embodiment of this disclosure.

[0031] Figure 9A and Figure 9B These are schematic diagrams showing the states of the first and second storage units connected by the first bit line in step S3.

[0032] Figure 10 This is a schematic diagram of the test process for testing the entire storage array according to an embodiment of this disclosure.

[0033] Figure 11 This is a block diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0035] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0036] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic diagram of the storage array under test in an exemplary embodiment of this disclosure.

[0038] refer to Figure 1 The storage array 100 may include: m bit lines BL1 to BLm, n word lines WL1 to WLn, and m*n storage cells 11. Each storage cell 11 is connected to one word line WL* and one bit line BL* ("*" represents any number). One word line WL* connects to m storage cells 11, and one bit line BL* connects to n storage cells 11. The m bit lines BL1 to BLm extend along the X direction and are arranged along the Y direction; the n word lines WL1 to WLn extend along the Y direction and are arranged along the X direction. Where m and n are both positive integers greater than or equal to 2.

[0039] Each bit line BL* is connected to an inductive amplifier SA*, which is also connected to a local data line LIO* (not shown). This is used to transfer data from the local data line LIO* to the bit line BL*, or to read data from the bit line BL* to the local data line LIO*.

[0040] Figure 2This is a schematic diagram of the circuit structure of the inductive amplifier in an embodiment of this disclosure.

[0041] refer to Figure 2 The memory cell 21 includes a first transistor M1 and a storage capacitor C. The first transistor M1 can be, for example, an N-type transistor. The source of the first transistor M1 is connected to the storage capacitor C, the drain is connected to the bit line BL, and the gate is connected to the word line WL. A column select unit 22, an equalization unit 23, and a sensing amplifier 24 are sequentially arranged on the bit line BL.

[0042] The column select unit 22 includes a second transistor M2, which is an N-type transistor. Its source is connected to the local input / output signal line LIO (Local Input / Output), its drain is connected to the bit line BL, and its gate is connected to the column select signal line YS (YSelect), also known as the column select signal line CSL (Column Select). The column select signal line YS is used to control the transfer of data from the bit line BL to the local input / output signal line LIO (to complete data reading) or to transfer data from the local input / output signal line LIO to the bit line BL (to complete data writing).

[0043] The equalization unit 23 includes a third transistor M3, a fourth transistor M2, and a fifth transistor M5. All three transistors are N-type transistors, and their gates are connected to the bit line equalization signal VEQ (Voltage of Equalizer). The source of the third transistor M3 and the drain of the fourth transistor M2 are both connected to the bit line pre-charge voltage V. BLP (Voltage of Bit Line Precharge), the drain of the third transistor M3 is connected to the bit line BL, and the source of the fourth transistor M2 is connected to the complementary bit line / BL.

[0044] The sense amplifier (SA) 22 is a differential amplifier with its two input terminals connected to the bit line BL and the complementary bit line / BL, respectively, to amplify the voltage difference between the bit line BL and the complementary bit line / BL. The sense amplifier 24 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor 222. The sixth transistor M6 and the seventh transistor M7 are both N-type transistors, while the eighth transistor M8 and the ninth transistor 222 are both P-type transistors. One end of the sixth transistor M6 is connected to the bit line BL through the first node N1, and the other end is connected to the low-potential node NCS. The low-potential node NCS is connected to the second voltage Vss, and the control terminal of the sixth transistor M6 is connected to the complementary bit line / BL. One end of the seventh transistor M7 is connected to the complementary bit line / BL through the second node N2, and the other end is connected to the low-potential node NCS. The control terminal of the seventh transistor M7 is connected to the bit line BL. One end of the eighth transistor M8 is connected to the bit line BL through the first node N1, and the other end is connected to the high-potential node PCS. The high-potential node PCS is connected to the second voltage Vary. The control terminal of the eighth transistor M8 is connected to the complementary bit line / BL. One end of the ninth transistor M9 is connected to the complementary bit line / BL through the second node N2, and the other end is connected to the high-potential node PCS. The control terminal of the ninth transistor M9 is connected to the bit line BL.

[0045] Figure 3A and Figure 3B This is through the embodiments disclosed herein. Figure 2 The circuit shown is a schematic diagram of the process of reading a memory cell.

[0046] refer to Figure 3A and Figure 3B Before performing data reading, the bit line equalization signal VEQ turns on the three transistors M3, M4, and M5 in the equalization unit 23, making the bit line BL and the complementary bit line / BL equal to the bit line precharge voltage V. BLP Upon arrival of the activation signal ACT, the bit line equalization signal VEQ is turned off, allowing a voltage difference between the bit line BL and the complementary bit line / BL. Next, the word line WL is turned on, reaching logic "1", and the first transistor M1 in memory cell 21 is activated. The activation signal ACT is used to control the sensing amplifier 24 to enter the operating state at the start of read and write operations.

[0047] exist Figure 3A If the storage cell 21 stores the data "0", then the storage capacitor C is at a low level, and the bit line BL leaks current to the storage capacitor C through the first transistor M1. The voltage on the bit line BL is changed by V BLPAs the voltage begins to drop, when the sensing amplifier 24 is turned on (SA ON), if the voltage drop on bit line BL causes the voltage difference ΔV between bit line BL and its complementary bit line / BL to reach a level detectable by sensing amplifier 24, then sensing amplifier 24 directly sets the bit line to the second voltage Vss and the complementary bit line to the first voltage Vary, thus amplifying the bit line voltage variation. The process during which the voltage on bit line BL changes but has not yet been amplified (i.e., from WL ON time point to SA ON time point) is called the charge sharing process, and the duration of the charge sharing process is called the sensing delay time (SDT).

[0048] Continue to refer to Figure 2 The specific amplification process of the inductive amplifier 24 is as follows: when the potential of the bit line BL drops by ΔV to V... BLP At -ΔV, the voltage across the complementary bit line / BL remains V. BLP The two input terminals of the inductive amplifier 24 are connected to bit line BL and complementary bit line / BL, respectively. At this time, the control terminal voltage V of the sixth transistor M6 is... BLP The voltage V at the control terminal of the seventh transistor M7 is greater than the voltage at the control terminal. BLP -ΔV.

[0049] If ΔV is large enough, greater than or equal to a threshold ΔVth, the gate voltage of the ninth transistor M9 is low, causing it to quickly turn on and the seventh transistor M7 to quickly turn off. This rapidly pulls the voltage of the second node N2 to the first voltage Vary, turning off the eighth transistor M8 controlled by the second node N2 and turning on the sixth transistor M6. At this time, the first node N1 is connected to the second voltage Vss through the conducting sixth transistor M6, meaning the voltage of bit line BL equals the second voltage Vss, and the voltage of the complementary bit line / BL equals the first voltage Vary. Thus, the voltage difference ΔV caused by leakage current from bit line BL to storage capacitor C is amplified by the sensing amplifier 24, and the potential of bit line BL equals the second voltage Vss, while the potential of the complementary bit line / BL equals the first voltage Vary. The voltage difference ΔVth that enables the sensing amplifier 24 to perform its amplification function is called the sensing margin of the sensing amplifier 24.

[0050] After the inductive amplification process is completed, the bit line BL is at a stable second voltage Vss. At this time, the word line WL is not turned off, and the storage capacitor C will continue to leak current through the bit line BL. After a certain period of time, the charge of the storage capacitor C can be restored to the state before the read operation. This stage is called the data recovery stage.

[0051] After the data write-back phase ends, a high-level pulse appears on the column selection signal line YS in response to the read control signal RD. This YS signal enables column selection unit 22 (YS ON), allowing the voltage of bit line BL to be read onto the local input / output signal line LIO. If the potential of bit line BL is the first voltage Vary, the read result is "1"; if the potential of bit line BL is the second voltage Vss, the read result is "0". The time between the activation signal ACT and the read signal RD is tRCD. tRCD is the delay time between RAS (Row Address Strobe) and CAS (Column Address Strobe). CAS and RAS together determine memory addressing. Within the tRCD time, there are three phases: charge sharing, inductive amplification, and data write-back.

[0052] After the column select signal YS is turned off (YS OFF), the sensing amplifier 24 responds to the precharge signal PRE to enter the preparation stage for the next read. At this time, the word line WL is turned off (WL OFF), the sensing amplifier 24 is turned off (SA OFF), and the bit line equalization signal VEQ is turned on (VEQ ON), so that both the bit line BL and the complementary bit line / BL recover to the bit line equalization voltage V. BLP This continues until the next activation signal ACT is received, regardless of whether the next activation signal ACT represents the start of reading or the start of writing.

[0053] The time from the precharge signal PRE to the next activation signal ACT is called the row precharge time tRP, which characterizes the speed at which the DRAM array recovers to the precharge state, especially the bit line in the array charging from a high or low level to the bit line precharge voltage V. BLP The time required. From Figure 3A As can be seen, when the tRP time is shortened, the bit line BL recovery time is insufficient, and the voltage is affected by the state when the precharge signal PRE appears, being higher or lower than the bit line precharge voltage V. BLP .

[0054] exist Figure 3B When word line WL is ON, if the data stored in memory cell 21 is "1", then the storage capacitor C is at a high level. The storage capacitor C leaks current to the bit line BL through the first transistor M1, and the voltage on the bit line BL is changed by V. BLPWhen the voltage rises, if the voltage difference ΔV between the bit line BL and the complementary bit line / BL reaches a level that the induction amplifier 24 can detect, the induction amplifier 24 will directly place the bit line BL at the first voltage Vary and the complementary bit line / BL at the second voltage Vss, thereby amplifying the bit line voltage variation.

[0055] Specifically, when the voltage of bit line BL starts to rise, the potential of the first node N1 is higher than that of the second node N2. If this voltage difference ΔV is greater than the sensing boundary ΔVth of the inductive amplifier 24, then after the inductive amplifier 24 is turned on, the conduction degree of the seventh transistor M7 is greater than that of the sixth transistor M6. The second node N2 is pulled to the second voltage Vss first through the seventh transistor M7 with the greater conduction degree, causing the eighth transistor M8 to turn on and the sixth transistor M6 to turn off. The potential of the first node N1 quickly rises to the first voltage Vary, the ninth transistor M9 is turned off, the seventh transistor M7 is turned on, and the potential of the second node N2 is fixed at the second voltage Vss. At this point, when reading the voltage of bit line BL through the column select signal YS, the first voltage Vary can be read, that is, the reading result is "1".

[0056] Figure 4A yes Figure 3A This diagram illustrates the scenario where reading data "0" fails.

[0057] Figure 4B yes Figure 3B This diagram illustrates the scenario where reading the data "1" fails.

[0058] refer to Figure 4A If the voltage difference ΔV between bit line BL and complementary bit line / BL does not reach the sensing boundary ΔVth of sensing amplifier 24, then when sensing amplifier 24 is turned on (SA ON), the voltage of the first node N1 is insufficient to turn on the ninth transistor M9 first, and can only control the seventh transistor M7 to discharge slowly. The voltage of the second node N2 slowly decreases, the conduction level of the eighth transistor M8 slowly increases, and the voltage of the first node N1 rises. Finally, the voltage of the second node N2 drops to the level that controls the eighth transistor M8 to conduct, causing the voltage of the first node N1 to rise to the first voltage Vary, which in turn causes the ninth transistor M9 to turn off and the seventh transistor M7 to turn on. The voltage of the second node N2 is equal to the second voltage Vss. At this time, the voltage on bit line BL is the first voltage Vary, i.e., data "1", and reading data "0" fails.

[0059] refer to Figure 4BIf the voltage difference ΔV between bit line BL and complementary bit line / BL does not reach the sensing boundary ΔVth of sensing amplifier 24, then when sensing amplifier 24 is turned on (SAON), the voltage of the first node N1 is insufficient to turn on the seventh transistor M7 first. The sixth transistor M6 and the seventh transistor M7 leak almost simultaneously, and the potentials of the first node N1 and the second node N2 drop simultaneously. Since the potential in the storage capacitor C is low at this time, bit line BL also needs to share charge with the storage capacitor C, causing the potential of bit line BL to drop faster until it drops to the level that turns on the ninth transistor M9. This causes the voltage of the second node N2 to be quickly pulled to the first voltage Vary, resulting in the eighth transistor M8 turning off and the sixth transistor M6 turning on. The potential of the first node N1 is fixed at the second voltage Vss. At this time, the voltage on bit line BL is the second voltage Vss, i.e., data "0", and reading data "1" fails.

[0060] The data writing process is basically similar to the data reading process.

[0061] During the data writing process, after the activation signal ACT arrives, the bit line equalization signal VEQ is turned off (VEQ OFF), and the word line WL is turned on (WL ON), entering the charge sharing stage between the bit line BL and the storage capacitor C. As the sensing amplifier 24 turns on (SAON), it amplifies the voltage fluctuations on the bit line BL, i.e., the sensing amplification stage. After the sensing amplification stage ends, the voltage on the bit line BL stabilizes, entering the data recovery stage (Restore). At this time, in response to the write control signal WR, a column select pulse appears on the column select signal line YS (YS ON), transferring data from the local input / output signal line LIO to the bit line BL, causing a voltage fluctuation on the bit line BL. This voltage fluctuation is amplified by the sensing amplifier 24, pulling the bit line BL and the complementary bit line / BL to new potentials, enabling the bit line BL to share charge with the storage capacitor C, resetting the data in the storage capacitor C, i.e., the data writing process. The data writing process ends when the precharge signal PRE arrives. Afterwards, the bit line equalization signal VEQ is turned on (VEQ OFF), the word line WL is turned off (WL OFF), and the bit line BL and complementary bit line / BL return to VEQ. BLP This continues until the next activation signal (ACT) arrives.

[0062] During this period, the time between the write control signal WR and the precharge signal PRE is the write time tWR. From the charge sharing process between the precharge signal PRE and the bit line BL and the storage capacitor C, it can be seen that the write time tWR affects the charge state in the storage capacitor C. If the write time tWR is small, insufficient data writing to the storage capacitor C is likely to occur; that is, when the process of writing data "1" ends, the charge in the storage capacitor C is insufficient, or when the process of writing data "0" ends, the residual charge in the storage capacitor C is relatively large.

[0063] Next, a method for detecting the sensing boundary ΔVth of the inductive amplifier 24 according to an embodiment of the present disclosure will be introduced.

[0064] Figure 5 This is a flowchart of the inductive amplifier sensing boundary detection method in an embodiment of this disclosure.

[0065] refer to Figure 5 Method 500 may include:

[0066] Step S1: Write first data and second data to the first storage cell and the second storage cell connected to the first bit line, respectively. The first storage cell and the second storage cell are respectively connected to the adjacent first word line and the second word line. The first bit line is connected to the first sensing amplifier.

[0067] Step S2, perform reverse write operation on the first storage unit and the second storage unit. The reverse write operation includes reverse writing the second data to the first storage unit and reverse writing the first data to the second storage unit.

[0068] Step S3: A write operation is performed on the memory cell connected by the second bit line, the first word line, and the second word line. There is a preset row precharge time between two adjacent write operations. The second bit line is connected to the second sensing amplifier. The second sensing amplifier and the first sensing amplifier are located in the same sensing amplifier array.

[0069] Step S4: Read the second storage unit. If the first data is not read correctly, determine that the preset row precharge time is the row precharge time boundary value of the first inductive amplifier.

[0070] exist Figure 5 In the illustrated embodiment, when the first data is 1 and the second data is 0, the sensing boundary of the inductive amplifier for data 1 can be detected, i.e., the line precharge time boundary value; when the first data is 0 and the second data is 1, the sensing boundary of the inductive amplifier for data 0 can be detected, i.e., the line precharge time boundary value. For ease of explanation, A will be used to represent the first data and B to represent the second data below.

[0071] The steps of method 500 will be described in detail below.

[0072] In step S1, first data and second data are written to the first storage unit and the second storage unit connected to the first bit line, respectively. The first storage unit and the second storage unit are connected to adjacent first word lines and second word lines, respectively. The sequence number of the first word line is less than the sequence number of the second word line. The first bit line is connected to the first inductive amplifier.

[0073] In such Figure 1In the memory array 100 shown, each sensing amplifier can serve as a first sensing amplifier, and correspondingly, each bit line BL connected to it can serve as a first bit line. Memory cells connected to adjacent word lines on the first bit line can serve as first memory cells and second memory cells. That is, there can be multiple first bit lines, and the number of first memory cells and second memory cells connected to each first bit line can be the same or different.

[0074] The first storage unit and the second storage unit include all storage units connected to the bit lines corresponding to all the sensor amplifiers under test, wherein each sensor amplifier under test is a first sensor amplifier, and the bit line corresponding to the sensor amplifier under test is the first bit line.

[0075] Figures 6A to 6C This is a schematic diagram showing the arrangement of the first and second storage units.

[0076] refer to Figure 6A and Figure 6B In one embodiment, the first storage unit for writing first data A and the second storage unit for writing second data B can be arranged at intervals on the first bit line, that is, the storage units adjacent to the first storage unit on the same first bit line are all second storage units, and the storage units adjacent to the second storage unit on the same first bit line are all first storage units.

[0077] refer to Figure 6C In another embodiment, the first storage unit and the second storage unit may also be arranged in multiple adjacent positions, that is, on the same first bit line, one or more first storage units are adjacent, one or more second storage units are adjacent, and at the same time, at least one second storage unit is adjacent to the first storage unit.

[0078] The first word line and the second word line do not refer to fixed word lines, but rather to adjacent word lines that connect the first memory cell and the second memory cell, respectively. In one embodiment, the memory cells connected to the first word line are all first memory cells, and the memory cells connected to the second word line are all second memory cells. The first word line is, for example, an even-numbered word line (WL0, 2, 4...), and the second word line is, for example, an odd-numbered word line (WL1, 3, 5...). Figure 6A In another embodiment, a memory cell connected by a word line can contain either a first memory cell or a second memory cell (e.g., ...). Figure 6B ).

[0079] Apart from Figures 6A to 6C The test pattern (topo) of the first and second storage cells shown may also include other test patterns, and this disclosure does not impose any special restrictions on them.

[0080] When multiple word lines exist, the process of writing first data to the first storage unit and second data to the second storage unit in step S1 can use the Y-Page method. The Y-Page method involves opening a word line, writing data to all storage units connected to that word line, and closing the word line and opening the next word line after all storage units connected to that word line have completed the data writing.

[0081] In step S2, a reverse write operation is performed on the first storage unit and the second storage unit. The reverse write operation includes writing the second data back to the first storage unit and writing the first data back to the second storage unit.

[0082] This step is used to perform a reverse write operation on all the aforementioned first and second memory cells, regardless of whether there is one or more bit lines, or the number of first and second memory cells.

[0083] It is important to emphasize that when there are multiple first bit lines, or even when testing the entire storage array, it is necessary to perform reverse write operations on the first bit lines in groups so that subsequent first bit lines can be used as second bit lines for operation (see the following description for the principle).

[0084] In one embodiment, the reverse write operation can be performed on the first and second memory cells connected by multiple sets of first bit lines in a first order. Each set of first bit lines includes a first number of adjacent first bit lines, and the first order is determined according to the bit line numbers in the multiple sets of first bit lines from smallest to largest. The first number is, for example, equal to the burst length of the memory array under test, which is the memory array containing the first and second memory cells.

[0085] Figure 7A and Figure 7B This is a schematic diagram of performing a reverse write operation on the first and second memory cells connected by multiple bit lines.

[0086] refer to Figure 7A and Figure 7B Taking the first and second memory cells as an example where they are spaced one-to-one on the first bit line, and assuming the burst length of the memory array under test is 8, then the first set of first bit lines are BL0 to BL7, the second set of first bit lines are BL8 to BL15, and so on. First, a reverse write operation is performed on the first and second memory cells connected by the first set of first bit lines BL0 to BL7 (e.g., ...). Figure 7A Then, reverse write operations are performed on the first and second memory cells connected by the first bit lines BL8 to BL15 of the second group (e.g., ...). Figure 7BThis process continues, and will not be shown again. That is, the first and second memory units are reversed using the X-Fast write method. The X-Fast write method involves opening a word line and sequentially writing the data of one Burst-length memory unit on that word line (also known as writing a Burst data unit), then closing that word line, and then opening the next word line and sequentially writing the data of one Burst-length memory unit on that word line, until all memory units connected to all word lines on the same bit line are sequentially opened and written.

[0087] In one embodiment, during the write-back operation, the write time tWR of the first data is controlled to a preset write delay so that the second storage cell experiences insufficient write of the first data.

[0088] Figure 8 This is a schematic diagram of the reverse write operation in an embodiment of this disclosure.

[0089] refer to Figure 8 When the first data is 1 and the second data is 0, the second storage unit stores the data "0" before the write-back operation and stores the data "1" after the write-back operation. Figure 2 The circuit shown can be configured to perform a reverse write operation on the second memory cell, which may include:

[0090] After the activation signal ACT arrives, the bit line equalization signal VEQ is turned on (VEQ ON), the word line WL is turned on (WL ON), and the second memory cell is connected ( Figure 2 During the charge sharing phase between the bit line BL of the memory cell 21 and the second memory cell, the potential on the bit line BL decreases. After the sensing amplifier 24 is turned on, the sensing amplification phase begins, and the bit line BL is pulled to the second voltage Vss, while the complementary bit line / BL is pulled to the first voltage Vary. After the bit line BL voltage stabilizes, the data write-back phase begins. When the write control signal WR arrives, a column select pulse (YS ON) appears on the column select signal line YS. The first data "1" on the local input / output signal line LIO is transmitted to the bit line BL, and the potential of the bit line BL is pulled high. At the same time, the bit line BL discharges the storage capacitor C, raising the potential in the storage capacitor C, causing the potential of the bit line BL to rise slowly to the first voltage Vary corresponding to the first data "1". If the write time tWR of the first data "1" is insufficient, that is, the precharge signal PRE arrives too early, the bit line BL will not have fully risen to the first voltage Vary, and the charge of the storage capacitor C will be insufficient, meaning the first data "1" will not be written sufficiently.

[0091] The same applies when the first data is 0 and the second data is 1. If the precharge signal PRE arrives early, there will still be residual charge in the storage capacitor C, meaning that the first data "0" is not written sufficiently.

[0092] Insufficient initial data writing increases the probability of subsequent sensing failures, as detailed below.

[0093] In step S3, a write operation is performed on the memory cell connected by the second bit line, the first word line, and the second word line. There is a preset row precharge time between two adjacent write operations. The second bit line is connected to the second sensing amplifier, and the second sensing amplifier and the first sensing amplifier are located in the same sensing amplifier array.

[0094] The memory cells connected by the second bit line, the first word line, and the second word line are memory cells that share the same word line as the first memory cell and the second memory cell connected to the first bit line. Since the second sensing amplifier and the first sensing amplifier are located in the same sensing amplifier array, when the memory cell connected to the second bit line is operated, the first sensing amplifier will also enter a synchronous working state (i.e., it also has a charge sharing stage, a sensing amplification stage, and a data write-back stage), but it will not exchange data with the local input / output signal line LIO.

[0095] Figure 9A and Figure 9B These are schematic diagrams showing the states of the first and second storage cells connected by the first bit line in step S3. Figure 9A This is a schematic diagram of the state of the first storage unit. Figure 9B This is a schematic diagram of the state of the second storage unit.

[0096] refer to Figure 9A and Figure 9B Let the first memory cell connected to the first word line be connected to the first word line. The first data is 1 and the second data is 0. After performing the reverse write operation, the first memory cell stores the second data 0 and the second memory cell stores the first data 1.

[0097] When a write operation is performed on the memory cell connected to the second bit line and the first word line, the first sensing amplifier connected to the first bit line enters a synchronous working state. Since the first memory cell and the second memory cell are connected to the first word line and the second word line respectively, when the first word line and the second word line are enabled during the write operation, the first memory cell and the second memory cell will also exchange data with the first bit line.

[0098] exist Figure 9AAfter performing the write-back operation, the second data 0 is stored in the first memory cell. When writing to the memory cell connected to the second bit line, before the precharge signal PRE arrives, the potential of the first bit line BL remains equal to the second voltage Vss because the first bit line BL does not need to exchange data with the local input / output signal line LIO, maintaining this state during the data restore phase. After the precharge signal PRE arrives, the potential of the first bit line BL begins to rise. If it can drop to Vss before the next activation signal ACT arrives... BLP This will not affect the sensing of the first line BL to the next memory cell. If the preset row precharge time tRP is short, that is, the next activation signal ACT arrives earlier, the potential of the first line BL will be lower than V. BLP .

[0099] exist Figure 9B When the first line BL is continuously used to operate on the second memory cell, since the second memory cell stores the first data 1, the potential on the first line BL will rise during the charge sharing phase. However, because the initial potential of the first line BL is lower than V... BLP The potential on the first line BL remains low after rising, insufficient to... Figure 2 In the circuit shown, the seventh transistor M7 is turned on first, causing the first line BL to be pulled to the second voltage Vss (see details). Figure 4A , Figure 4B (and corresponding description). Since the first bit line BL no longer exchanges data with the local input / output signal line LIO, during the data write-back phase, the data in the second storage unit will be reset to 0 by the first bit line BL, which means the first data has been changed.

[0100] If the first data 0 in the second memory cell is not written sufficiently, there will be residual charge, and the potential drop on the first bit line BL will be smaller, further increasing the possibility that the first data in the second memory cell will be rewritten.

[0101] The same applies when the first data is 1 and the second data is 0, which will not be elaborated here.

[0102] Therefore, by shortening the preset row precharge time tRP, the sensing boundary of the sensing amplifier can be reduced, the probability of sensing amplifier failure can be increased, and the minimum row precharge time tRP that enables the sensing amplifier to successfully sense can be detected, i.e., the row precharge time boundary value.

[0103] By shortening the write time tWR of the first data in the second storage cell, and creating insufficient write in the second storage cell, the probability of sensing amplifier failure can be further increased, and the sensing boundary of sensing amplifier failure can be detected as soon as possible.

[0104] Based on the above principles, when the write time tWR is set to a longer value, the row precharge time boundary value is smaller (i.e., tRP is shorter); when the write time tWR is set to a shorter value, the row precharge time boundary value is larger (i.e., tRP is longer); when the write time tWR is set to a very short value, it will cause the second storage cell to fail to be sensed regardless of how the row precharge time is adjusted (i.e., the data in the second storage cell is overwritten). This write time can be set as the write time boundary value. Therefore, in some embodiments, the row precharge time boundary value corresponding to each write time tWR can be measured.

[0105] In addition, the minimum write time tWR that causes sensing failure can be measured for each preset row precharge time tRP, i.e., the write time boundary value. Of course, when tRP is set very short, it will cause the second storage cell to fail to be sensed no matter how much the write time tWR is extended. In this case, tRP also belongs to the row precharge time boundary value.

[0106] By measuring multiple sets of boundary value combinations (tWR, tRP) that just cause induction failure, an effective data basis can be provided for the analysis and design of induction amplifiers.

[0107] As can be seen from the above embodiments, when performing a write operation on the memory cell connected to the second bit line, the data being written is not important. What is important is that the memory cell being written to needs to have the same word line connected to the first memory cell and the second memory cell. Thus, when operating on the memory cell being written to, the first memory cell, the second memory cell and the first bit line are controlled to exchange data and enter the data write-back stage, so that the data in the second memory cell can be rewritten when the sensing fails.

[0108] In one embodiment, when multiple first bit lines exist, a first bit line that has not yet been operated can be used as a second bit line. For example, when testing the inductive amplifiers connected to the entire memory array, and performing reverse write operations on multiple sets of first and second memory cells connected by first bit lines, a set of first bit lines that has not yet been operated can be regarded as a second bit line. Subsequently, since this second bit line is one of multiple first bit lines, a reverse write operation can be performed on the first and second memory cells connected to this second bit line.

[0109] As can be seen from the above description, assuming there are x groups of first-line bits (x > 2), after sequentially performing reverse write operations on the entire storage array, the second storage unit connected to the first group of first-line bits enters a data write-back stage without exchanging data with LIO for x-1 times, the second storage unit connected to the second group of first-line bits enters a data write-back stage without exchanging data with LIO for x-2 times, and so on. The second storage unit connected to the first group of first-line bits enters a data write-back stage without exchanging data with LIO for 1 time, and the second storage unit connected to the first group of first-line bits does not enter a data write-back stage without exchanging data with LIO.

[0110] The more data write-back stages that do not exchange data with LIO, the greater the probability of sensing failure and data overwriting in the second storage unit, resulting in more accurate testing. Therefore, to balance the testing accuracy of the second storage units connected to each first bit line, before reading the second storage unit, multiple sets of first and second storage units connected to the first bit line can be reversed in a second order, which is the reverse of the first order. This ensures that each set of second storage units connected to the first bit line enters x-1 data write-back stages without exchanging data with LIO.

[0111] In one embodiment of this disclosure, a first sensing amplifier connected to a first bit line can be configured to be connected to a test voltage. When the first data is 1, the power supply voltage in the test voltage is lower than the power supply voltage when the memory array under test is operating normally; when the first data is 0, the ground voltage in the test voltage is higher than the ground voltage of the memory array under test. This further creates a first data write insufficiency in the second memory cell, accelerating the speed at which the sensing boundary of the first sensing amplifier is reached. Corresponding to the foregoing, the (tRP, tWR) boundary value combination that causes sensing failure for each set of test voltages can also be measured, providing a data basis for the analysis and design of the sensing amplifier.

[0112] In step S4, the second storage unit is read. If the first data is not read correctly, the preset row precharge time is determined to be the row precharge time boundary value of the first inductive amplifier.

[0113] When reading the second memory cell, the Y-Page read method can be used, which means opening a word line, reading all the memory cells connected by that word line, closing the word line, and opening the next word line.

[0114] When testing the entire storage array, each word line can be turned on sequentially, each storage cell can be read, and only the data in the second storage cell can be evaluated. In some embodiments, only the word line connected to the second storage cell can be turned on.

[0115] If the sensing amplifier fails to sense the data after the above steps are completed, it will rewrite the first data in the second storage unit, making it impossible to read the first data correctly in the second storage unit.

[0116] Furthermore, when the first data is correctly read from each second memory cell, the preset row precharge time tRP is reduced, and the detection is repeated according to steps S1 to S4 above. Adjusting the preset row precharge time tRP can be referred to as "carding tRP," and adjusting the write time tWR can be referred to as "carding tWR." By using the methods of carding tRP and carding tWR to control the sensing amplifier's sensing failure, the amplification performance of the sensing amplifier can be evaluated from multiple perspectives.

[0117] The following example of testing the entire storage array illustrates the embodiments of this disclosure.

[0118] Figure 10 This is a schematic diagram of the test process for testing the entire storage array according to an embodiment of this disclosure. Figure 10 The illustrated embodiment uses a first data value of 1 and a second data value of 0 as an example.

[0119] refer to Figure 10 In part (a), in step 1, the first Burst data “1” is written to the memory unit (i.e., the first memory unit) connected by the even-numbered word lines WL0, WL2, WL4, WL6… using the Y-Page method; the first Burst data “0” is written to the memory unit (i.e., the second memory unit) connected by the odd-numbered word lines WL1, WL3, WL5, WL7… using the Y-Page method.

[0120] refer to Figure 10 In part (b), in step 2, the first Burst data “0” is written back to the memory unit (i.e., the first memory unit) connected by the even-numbered word lines WL0, WL2, WL4, WL6… using the X-Fast writing method, and tWR and tRP are checked; the first Burst data “1” is written to the memory unit (i.e., the second memory unit) connected by the odd-numbered word lines WL1, WL3, WL5, WL7… using the X-Fast writing method, and tWR and tRP are checked.

[0121] refer to Figure 10In part (c), in step 3, the second Burst data "0" is written backwards using the X-Fast writing method to the memory units (i.e., the first memory units) connected by even-numbered word lines WL0, WL2, WL4, WL6…, and tWR and tRP are stopped; the second Burst data "1" is written using the X-Fast writing method to the memory units (i.e., the second memory units) connected by odd-numbered word lines WL1, WL3, WL5, WL7…, and tWR and tRP are stopped. When the second Burst data is written to each WL, the first Burst data starts to stop at tRP.

[0122] For specific instructions on writing the first and second Burst data, please refer to [link / reference needed]. Figure 7A and Figure 7B The same applies to writing subsequent Burst data.

[0123] refer to Figure 10 In part (d), in step 4, the third Burst data "0" is written backwards using the X-Fast writing method to the memory units (i.e., the first memory units) connected by even-numbered word lines WL0, WL2, WL4, WL6…, and tWR and tRP are stopped; the third Burst data "1" is written using the X-Fast writing method to the memory units (i.e., the second memory units) connected by odd-numbered word lines WL1, WL3, WL5, WL7…, and tWR and tRP are stopped. When the third Burst data is written to each WL, the first and second Burst data are stopped at tRP.

[0124] refer to Figure 10 In part (e), in step 5, the fourth Burst data "0" is written backwards using the X-Fast writing method to the storage units (i.e., the first storage units) connected by even-numbered word lines WL0, WL2, WL4, WL6…, and tWR and tRP are blocked; the fourth Burst data "1" is written using the X-Fast writing method to the storage units (i.e., the second storage units) connected by odd-numbered word lines WL1, WL3, WL5, WL7…, and tWR and tRP are blocked. When each WL starts writing the third Burst data, the first, second, and third Burst data are blocked at tRP.

[0125] refer to Figure 10 In part (f), in step 6, the Y-Page method is used to read the memory cells (i.e., the second memory cells) connected by the odd-numbered word lines WL1, WL3, WL5, WL7... to determine whether they are all 1. If they are all 1, the tRP is shortened and the test is repeated. Otherwise, the current tRP is determined to be the row precharge time boundary value.

[0126] Applying the detection method provided in this disclosure to mass production processes can improve the detection accuracy of the sensing boundary of the induction amplifier, which helps to improve product reliability and yield.

[0127] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0128] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0129] The following reference Figure 11 To describe an electronic device 1100 according to this embodiment of the present invention. Figure 11 The electronic device 1100 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0130] like Figure 11 As shown, the electronic device 1100 is manifested in the form of a general-purpose computing device. The components of the electronic device 1100 may include, but are not limited to: at least one processing unit 1110, at least one storage unit 1120, and a bus 1130 connecting different system components (including storage unit 1120 and processing unit 1110).

[0131] The storage unit stores program code, which can be executed by the processing unit 1110 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 1110 can perform the method shown in the embodiments of this disclosure.

[0132] Storage unit 1120 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 11201 and / or cache memory 11202, and may further include a read-only memory (ROM) 11203.

[0133] Storage unit 1120 may also include a program / utility 11204 having a set (at least one) of program modules 11205, such program modules 11205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0134] Bus 1130 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0135] Electronic device 1100 can also communicate with one or more external devices 1200 (e.g., keyboard, pointing device, Bluetooth device, etc.), one or more devices that enable a user to interact with electronic device 1100, and / or any device that enables electronic device 1100 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1150. Furthermore, electronic device 1100 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1160. As shown, network adapter 1160 communicates with other modules of electronic device 1100 via bus 1130. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1100, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0136] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the invention.

[0137] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may, for example, be performed synchronously or asynchronously in multiple modules.

[0138] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A method for detecting the sensing boundary of an inductive amplifier, characterized in that, include: First data and second data are written to the first storage cell and the second storage cell connected to the first bit line, respectively. The first storage cell and the second storage cell are respectively connected to the adjacent first word line and the second word line. The first bit line is connected to the first sensing amplifier. Perform a reverse write operation on the first storage unit and the second storage unit. The reverse write operation includes writing the second data into the first storage unit and writing the first data into the second storage unit. A write operation is performed on the memory cell connected by the second bit line, the first word line, and the second word line. There is a preset row precharge time between two adjacent write operations. The second bit line is connected to the second sensing amplifier. The second sensing amplifier and the first sensing amplifier are located in the same sensing amplifier array. Read the second storage cell. When the first data is correctly read in each of the second storage cells, reduce the preset row precharge time. Repeat the above steps to re-detect until the first data is not correctly read. Then determine that the preset row precharge time is the row precharge time boundary value of the first induction amplifier.

2. The detection method as described in claim 1, characterized in that, The number of the first bit lines is multiple, and the second bit line is the next first bit line after the currently operated first bit line. The reverse write operation on the first memory cell and the second memory cell includes: The reverse write operation is performed on the first memory cell and the second memory cell connected by multiple sets of first bit lines in a first order. Each set of first bit lines includes a first number of adjacent first bit lines. The first order is determined according to the bit line number in the multiple sets of first bit lines from small to large. The write operation to the memory cell connected by the second bit line, the first word line, and the second word line includes: The reverse write operation is performed on the first memory cell and the second memory cell connected by the second bit line, wherein the second bit line is one of the multiple first bit lines.

3. The detection method as described in claim 2, characterized in that, Before reading the second storage unit, the process also includes: The reverse write operation is performed on the first and second memory cells connected by the first bit line of the plurality of groups in a second order, which is the opposite of the first order.

4. The detection method according to any one of claims 1 to 3, characterized in that, In the reverse write operation, the write time of the first data is controlled to a preset write delay so that the second storage unit experiences insufficient first data write.

5. The detection method as described in claim 1, characterized in that, The first data is 1, and the second data is 0; or, the first data is 0 and the second data is 1.

6. The detection method as described in claim 2, characterized in that, The first quantity is equal to the burst length of the storage array under test, which is the storage array containing the first storage unit and the second storage unit.

7. The detection method as described in claim 1, characterized in that, The first storage unit and the second storage unit include all storage units connected to the bit lines corresponding to all the sensor amplifiers under test.

8. The detection method as described in claim 1 or 7, characterized in that, All memory cells adjacent to the first memory cell on the same first bit line are the second memory cells.

9. The detection method as described in claim 8, characterized in that, The first storage unit and the second storage unit are arranged on the same word line.

10. The detection method as described in claim 1 or 7, characterized in that, On the same first line, one or more first storage cells are adjacent to each other, one or more second storage cells are adjacent to each other, and at least one second storage cell is adjacent to the first storage cell.

11. The detection method as described in claim 1, characterized in that, The first inductive amplifier is connected to the test voltage.

12. The detection method as described in claim 11, characterized in that, When the first data is 1, the power supply voltage in the test voltage is lower than the power supply voltage when the memory array under test is operating normally; when the first data is 0, the ground voltage in the test voltage is higher than the ground voltage of the memory array under test.

13. An electronic device, characterized in that, include: Memory; as well as A processor coupled to the memory, the processor being configured to perform the memory array fault detection method as described in any one of claims 1-12 based on instructions stored in the memory.

14. A computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the storage array fault detection method as claimed in any one of claims 1-12.

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