Multi-core processing circuit with power supply stabilization test mechanism and test method thereof

Abstract

A multi-core processing circuit with power stability test mechanism and a test method thereof, the multi-core processing circuit includes a plurality of sequentially arranged core processing circuits and a self-test scheduling circuit. The core processing circuits are respectively provided with memory built-in self-test circuits. The self-test scheduling circuit is configured to receive a main driving signal, and to sequentially drive the memory built-in self-test circuit of one of the core processing circuits to perform self-test in a signal handshake manner every delay time. The one of the core processing circuits driven has a maximum average power draw within a preset range at the delay time.

Description

Technical Field

[0001] This invention relates to circuit testing technology, and more particularly to a multi-core processing circuit with a power supply stability testing mechanism and its testing method. Background Technology

[0002] Multi-core processing circuits incorporate two or more independent central processing units into a single computing element to execute program instructions independently, thereby accelerating program execution by leveraging parallel computing capabilities.

[0003] Corresponding to processing circuits, the built-in self-test circuitry of the memory is an important testing component, enabling self-testing with reduced reliance on external testing equipment. However, for multi-core processing circuits, each core processing circuit needs to perform self-testing based on its internal memory-built-in self-test circuitry. If the power supply of a multi-core processing circuit experiences a voltage drop due to excessive circuit testing, the test signal level may also drop, leading to erroneous results. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a multi-core processing circuit with a power stability testing mechanism and a testing method thereof, so as to improve the prior art.

[0005] This invention includes a multi-core processing circuit with a power stability testing mechanism, comprising: multiple sequentially arranged core processing circuits and a self-test scheduling circuit. Each core processing circuit has a built-in self-test circuit. The self-test scheduling circuit is configured to receive a main drive signal and, accordingly, sequentially drive the built-in self-test circuit of one of the core processing circuits to perform self-tests at intervals of delay using a signal handshake method. The driven core processing circuit has an average power draw within a preset range during the delay time.

[0006] This invention also includes a testing method for a multi-core processing circuit with a power stability testing mechanism, applied to a multi-core processing circuit. The multi-core processing circuit includes multiple core processing circuits arranged sequentially and each equipped with a built-in self-test circuit in memory, as well as a self-test scheduling circuit. The multi-core processing circuit testing method includes the following steps: receiving a main drive signal from the self-test scheduling circuit; and the self-test scheduling circuit sequentially driving the built-in self-test circuit of one of the core processing circuits at intervals of delay time in a signal-handling manner to perform self-testing, wherein the driven core processing circuit has an average power draw within a preset range during the delay time.

[0007] The features, implementation, and technical effects of this disclosure are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1 This diagram shows a block diagram of a multi-core processing circuit with a power stability testing mechanism in one embodiment of the present invention.

[0009] Figure 2A This diagram shows the power supply waveforms of N core processing circuits when they are driven without any delay time, according to one embodiment of the present invention.

[0010] Figure 2B This diagram shows the power supply waveform of the entire multi-core processing circuit when N core processing circuits are driven without any delay time, according to one embodiment of the present invention.

[0011] Figure 3A This diagram shows the power supply waveforms of each of the N core processing circuits when they are driven at intervals of one delay time, according to one embodiment of the present invention.

[0012] Figure 3B This diagram shows the power supply waveforms of the entire multi-core processing circuit when N core processing circuits are driven at intervals of one delay time, according to one embodiment of the present invention; and

[0013] Figure 4 This diagram shows a flowchart of a multi-core processing circuit testing method with a power supply stability testing mechanism, according to one embodiment of the present invention.

[0014] Symbol Explanation

[0015] 100: Multi-core processing circuit

[0016] 110: Core Processing Circuit

[0017] 120: Self-test scheduling circuit

[0018] MB: Memory has built-in self-test circuitry

[0019] 400: Multi-core Processing Circuit Test Method

[0020] S410~S420: Steps

[0021] ID: Individual drive signal

[0022] LT: Minimum threshold

[0023] MD: Main drive signal

[0024] RS: Return signal

[0025] TI, TI1~TIN: Time Period

[0026] DI2~DIN: Delay time

[0027] ΔV: Maximum power supply voltage drop

[0028] NΔV: Total power supply voltage drop at maximum value Detailed Implementation

[0029] One objective of this invention is to provide a multi-core processing circuit and its testing method with a power stability testing mechanism. By using a signal handshake method, the self-test circuits built into the memory of each core processing circuit are driven in a distributed manner without the need to set any delay units, thereby avoiding excessive power voltage drop caused by simultaneous driving and improving the stability of the self-test process.

[0030] Please refer to Figure 1 . Figure 1 This diagram shows a block diagram of a multi-core processing circuit 100 with a power stability testing mechanism according to an embodiment of the present invention. The multi-core processing circuit 100 includes: a plurality of sequentially arranged core processing circuits 110 and a self-test scheduling circuit 120.

[0031] The core processing circuit 110 is equipped with a built-in self-test circuit MB. Figure 1 The memory is designated as MB. It should be noted that the core processing circuit 110 may also include, for example (but not limited to) a processor, a memory that serves as the test object for the built-in self-test circuit MB, and other components, which are not shown here for the sake of simplicity.

[0032] The built-in self-test circuit MB can generate a test pattern based on its built-in logic circuit after being driven, and then test and compare the test results to determine whether the test results are correct.

[0033] The self-test scheduling circuit 120 is configured to receive the main drive signal MD. The main drive signal MD may be generated by, for example (but not limited to), a test instrument (not shown) electrically coupled to the multi-core processing circuit 100.

[0034] Upon receiving the main drive signal MD, the self-test scheduling circuit 120 sequentially drives the memory-built-in self-test circuit MB of one of the core processing circuits 110 in a handshake manner at intervals of delay time to perform self-tests. The driven core processing circuit 110 has an average power draw within a preset range during the delay time.

[0035] The above-described signal handshake configuration is such that the self-test scheduling circuit 120 transmits individual drive signal IDs to the memory-built-in self-test circuit MB of one of the core processing circuits 110 for driving.

[0036] After receiving the feedback signal RS generated by the memory-built-in self-test circuit MB, the self-test scheduling circuit 120 transmits an individual drive signal ID to the memory-built-in self-test circuit MB of the next core processing circuit 110 for driving, until all the memory-built-in self-test circuits MB of the core processing circuits 110 are driven. The time difference between the transmission of the individual drive signal ID by the self-test scheduling circuit 120 and the receipt of the feedback signal RS generated by the memory-built-in self-test circuit MB is the aforementioned delay time.

[0037] For example, when the number of core processing circuits 110 is N, after receiving the main drive signal MD, the self-test scheduling circuit 120 will generate an individual drive signal ID and send it to the built-in self-test circuit MB in the memory of the first core processing circuit 110 for driving. When the built-in self-test circuit MB in the memory of the first core processing circuit 110 generates a feedback signal RS, the self-test scheduling circuit 120 will generate an individual drive signal ID and send it to the built-in self-test circuit MB in the memory of the second core processing circuit 110 for driving. When the built-in self-test circuit MB in the memory of the second core processing circuit 110 generates a feedback signal RS, the self-test scheduling circuit 120 will generate an individual drive signal ID and send it to the built-in self-test circuit MB in the memory of the third core processing circuit 110 for driving.

[0038] Similarly, after the self-test scheduling circuit 120 generates an individual drive signal ID and drives the self-test circuit MB built into the memory of the Nth core processing circuit 110, it will no longer transmit the individual drive signal ID.

[0039] In one embodiment, the built-in self-test circuit MB, after being driven, will begin performing a self-test and generate a feedback signal RS after the self-test completes a preset test phase. Therefore, the aforementioned delay time corresponds to the time consumed from the start of the self-test to the end of the preset test phase, and the self-test has an average power draw within a preset range during this delay time. In one embodiment, the average power draw is determined by the average power supply voltage drop.

[0040] Please refer to the following at the same time Figure 2A as well as Figure 2B . Figure 2A This diagram shows the power supply waveforms of each of the N core processing circuits 110 when they are driven without any delay time, according to one embodiment of the present invention. Figure 2BThis diagram shows the power supply waveforms of the entire multi-core processing circuit 100 when N core processing circuits 110 are driven without any delay time, according to one embodiment of the present invention.

[0041] Figure 2A as well as Figure 2B The horizontal axis represents time, and the vertical axis represents voltage. It should be noted that, for easier comparison on the horizontal axis (time), ... Figure 2A The waveforms of the power supplies of multiple core processing circuits 110 are arranged side by side on the same vertical axis, and the magnitudes of each power supply are essentially equal.

[0042] like Figure 2A As shown, since each core processing circuit 110 is driven without any delay, all core processing circuits 110 will be driven simultaneously to draw power. Because the core processing circuits 110 draw a large amount of power at the beginning of the self-test, a power voltage drop with a maximum value of ΔV is generated during the time period TI, which only returns to stability after the preset test phase ends.

[0043] Therefore, as Figure 2B As shown, the power supply of the entire multi-core processing circuit 100 will be in the time period TI, because the N core processing circuits 110 draw power at the same time, resulting in a total power supply voltage drop of a maximum value of NΔV.

[0044] In this situation, due to the excessively large maximum instantaneous total power supply voltage drop NΔV, the signal level will be easily affected and reduced, even exceeding the allowable minimum threshold LT, causing the originally correct test results to become incorrect and resulting in test failure. However, if the solution is to increase the power supply of the entire system, the voltage margin will be reduced, making it easier to affect product yield.

[0045] Please refer to the following at the same time Figure 3A as well as Figure 3B . Figure 3A This diagram shows the power supply waveforms of each of the N core processing circuits 110 when they are driven at intervals of one delay time, according to one embodiment of the present invention. Figure 3B This diagram shows the power supply waveforms of the entire multi-core processing circuit 100 when N core processing circuits 110 are driven at intervals of one delay time, according to one embodiment of the present invention.

[0046] Figure 3A as well as Figure 3B The horizontal axis represents time, and the vertical axis represents voltage. It should be noted that, for easier comparison on the horizontal axis (time), ... Figure 3A The waveforms of the power supplies of multiple core processing circuits 110 are arranged side by side on the same vertical axis, and the magnitudes of each power supply are essentially equal.

[0047] like Figure 3A As shown, each core processing circuit 110 is driven at intervals of delay time DI2 to DIN. The time when each core processing circuit 110 draws power is staggered by delay time DI2 to DIN, and a power voltage drop with a maximum value of ΔV is generated in the time period TI1 to the time period TIN, and the voltage drops return to stability after the preset test phase ends.

[0048] Therefore, as Figure 3B As shown, under the optimal delay time setting, the total power supply voltage drop of the entire multi-core processing circuit 100 will be maintained at around the maximum power supply voltage drop corresponding to the core processing circuit 110, which is ΔV, due to the distributed drive, and above the minimum threshold LT, so that the test results remain correct and the test is successful.

[0049] As described above, the length of the delay time corresponds to the end of a preset test phase. In one embodiment, the self-test scheduling circuit 120 enables the built-in self-test circuit MB of each core processing circuit 110 to start testing from a delay time of zero, gradually increasing the delay time when a test fails, and setting the test phase corresponding to the delay time as a preset test phase when a test succeeds. In this way, the self-test scheduling circuit 120 can determine, for example, the end of a preset test phase. Figure 3B The optimal setting length for the delay time is shown.

[0050] In this way, multi-core processing circuits can use signal handshaking to drive the built-in self-test circuits of each core processing circuit in a distributed manner without setting any delay units, avoiding excessive power supply voltage drop caused by simultaneous driving and improving the stability of the self-test process.

[0051] Figure 4 This diagram shows a flowchart of a multi-core processing circuit testing method 400 with a power supply stability testing mechanism, according to an embodiment of the present invention.

[0052] In addition to the aforementioned apparatus, the present invention also discloses a multi-core processing circuit testing method 400, applicable to, for example, but not limited to, [other applications]. Figure 1 In the multi-core processing circuit 100. An embodiment of the multi-core processing circuit test method 400 is shown below. Figure 4 As shown, it includes the following steps.

[0053] In step S410, the self-test scheduling circuit 120 receives the main drive signal.

[0054] In step S420, the self-test scheduling circuit 120 drives the memory-built-in self-test circuit MB of one of the core processing circuits 110 to perform self-tests in a signal-handling manner at intervals of delay time, wherein one of the driven core processing circuits 110 has an average power draw within a preset range during the delay time.

[0055] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention.

[0056] In summary, the multi-core processing circuit and its testing method with a power stability testing mechanism in this invention can drive the self-test circuits built into the memory of each core processing circuit in a distributed manner through signal handshaking without setting any delay units, thereby avoiding excessive power voltage drop caused by simultaneous driving and improving the stability of the self-test process.

[0057] Although the embodiments of this disclosure are described above, they are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on its express or implied content. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the claims of this specification.

Claims

1. A multi-core processing circuit with a power supply stability testing mechanism, comprising: Multiple core processing circuits arranged in sequence, each equipped with a built-in self-test circuit in its memory; and A self-test scheduling circuit is configured to receive a main drive signal, and accordingly drive the memory-built-in self-test circuit of one of the plurality of core processing circuits to perform a self-test in a signal-handling manner at intervals of a delay time, wherein one of the driven plurality of core processing circuits has an average power draw within a preset range at that delay time. The signal handshake method is configured such that the self-test scheduling circuit transmits an individual drive signal to the built-in self-test circuit of one of the plurality of core processing circuits for driving, and after receiving a feedback signal generated by the built-in self-test circuit, the self-test scheduling circuit transmits the individual drive signal to the built-in self-test circuit of the next core processing circuit in the plurality of core processing circuits for driving, until the built-in self-test circuits of all the plurality of core processing circuits are driven; The time difference between the transmission of the individual drive signal and the receipt of the feedback signal by the built-in self-test circuit of the corresponding memory is the delay time. The built-in self-test circuit of the memory generates the feedback signal after a preset test phase ends. The self-test scheduling circuit enables the built-in self-test circuit of the memory of the multiple core processing circuits to start testing from the length of the delay time being zero. When the test fails, the length of the delay time is gradually increased. When the test succeeds, the test phase corresponding to the delay time is set as the preset test phase.

2. The multi-core processing circuit of claim 1, wherein the average power draw is determined by an average power supply voltage drop.

3. A testing method for a multi-core processing circuit with a power stability testing mechanism, applied to a multi-core processing circuit, the multi-core processing circuit comprising multiple core processing circuits arranged sequentially and each having a self-test circuit built into its memory, and a self-test scheduling circuit, the testing method comprising: A main drive signal is received by a self-test scheduling circuit; and The self-test scheduling circuit sequentially drives the built-in self-test circuit of one of the multiple core processing circuits at intervals of time delay in a signal-handling manner to perform a self-test, wherein one of the driven multiple core processing circuits has an average power draw within a preset range during the time delay. This signal handshake method also includes: The self-test scheduling circuit transmits a drive signal to the memory-built-in self-test circuit of one of the multiple core processing circuits for driving; and After receiving a feedback signal generated by the memory-built-in self-test circuit, the self-test scheduling circuit transmits the individual drive signal to the memory-built-in self-test circuit of the next core processing circuit in the plurality of core processing circuits to drive it, until the memory-built-in self-test circuits of all the plurality of core processing circuits are driven. The time difference between the transmission of the individual drive signal and the receipt of the feedback signal by the built-in self-test circuit of the corresponding memory is the delay time. in, The multi-core processing circuit testing method further includes: The feedback signal is generated by the built-in self-test circuit of the memory after a preset test phase is completed. The self-test scheduling circuit enables the built-in self-test circuits of the memory of the multiple core processing circuits to perform tests starting from the length of the delay time being zero. The self-test scheduling circuit gradually increases the length of the delay time when a test fails. as well as When the self-test scheduling circuit determines that the test is successful, it sets the test stage corresponding to the delay time as the preset test stage.

4. The multi-core processing circuit testing method as described in claim 3, wherein the average power supply draw is determined by an average power supply voltage drop.

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