Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a plurality of first transistor regions and at least one second transistor region; forming an etching stop layer on each of the first transistor regions and the second transistor regions, the etching stop layer on the second transistor region having a thickness greater than the etching stop layer on the first transistor regions; performing a plurality of cycles of deposition and etching on the first transistor regions and the second transistor region until a function structure is formed on each of the first transistor regions and the second transistor region, respectively, and each of the function structures has a different thickness, the function structure including a plurality of function layers, each of the cycles of deposition and etching including a deposition step and a patterning step after the deposition step, the second transistor region having a greater number of the patterning steps than the first transistor regions. The method for forming a semiconductor structure makes the threshold voltage of the transistor more stable, thereby improving the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for forming a semiconductor structure. Background Technology

[0002] As the size of semiconductor devices continues to shrink, fin field-effect transistors are widely used in integrated circuit components.

[0003] In the manufacturing process of fin field-effect transistors, a work function metal (WFM) is typically formed on a high-k dielectric layer. By adjusting the thickness of the work function metal layer, the threshold voltage of the field-effect transistor can be adjusted.

[0004] Currently, multiple etching processes are typically used to adjust the thickness of the work function metal layer on different transistors. However, in the existing technology, the number of etching cycles for adjusting the work function metal layer thickness varies on each transistor, making the work function metal layer on some transistors susceptible to excessive damage. This affects the stability of the threshold voltage of the field-effect transistor and consequently impacts device performance. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure that reduces the additional damage to the work function metal layer during the etching process, thereby making the threshold voltage of the field-effect transistor more stable and thus improving the device performance.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a plurality of first transistor regions and at least one second transistor region; forming an etch stop layer on each of the first transistor regions and each of the second transistor regions, wherein the thickness of the etch stop layer on each of the second transistor regions is greater than the thickness of the etch stop layer on each of the first transistor regions; after forming the etch stop layer, performing a plurality of cyclic deposition etching processes on the first transistor regions and the second transistor regions until function structures are formed on the plurality of first transistor regions and the plurality of second transistor regions respectively, and each function... The structure has different thicknesses, and the work function structure includes several work function layers. Each cycle of deposition and etching process includes a deposition step and a patterning step after the deposition step. The number of patterning steps performed on the second transistor region is more than the number of patterning steps performed on the first transistor region. Each cycle of deposition and etching process includes: depositing an initial work function layer on each first transistor region and each second transistor region; and patterning the initial work function layer to expose the etch stop layer surface of any first transistor region, any second transistor region, or any first transistor region and at least one second transistor region, so as to form a work function layer.

[0007] Optionally, the sum of the number of the first transistor region and the number of the second transistor region is N+1, the number of cycles of deposition and etching is N, where N is a natural number greater than or equal to 2; the work function structure includes several work function layers, and the maximum number of work function layers is N.

[0008] Optionally, a first work function layer is formed in the first cycle of deposition etching process, exposing part of the etching stop layer.

[0009] Optionally, in the deposition step of the i-th cyclic deposition etching process, an i-th initial work function layer is deposited, the i-th initial work function layer being located on the exposed etch stop layer surface and the (i-1)-th work function layer surface; in the patterning step of the i-th cyclic deposition etching process, the i-th initial work function layer is patterned to form the i-th work function layer; the (i-1)-th work function layer is the work function layer formed in the (i-1)-th cyclic deposition etching process, and the value of i is in the range of 1 < i ≤ N.

[0010] Optionally, in the i-th cycle deposition and etching process, the method for patterning the i-th initial work function layer includes: forming a patterned layer on the i-th initial work function layer, wherein the patterned layer has a patterned opening that exposes the i-th initial work function layer on any first transistor region or any second transistor region; using the patterned layer as a mask, etching the first work function layer to the i-th initial work function layer until the surface of the etching stop layer is exposed, wherein the i-th initial work function layer becomes the i-th work function layer.

[0011] Optionally, in the i-th cycle deposition and etching process, the method for patterning the i-th initial work function layer includes: forming a patterned layer on the i-th initial work function layer, the patterned layer having patterned openings exposing the i-th initial work function layer on any first transistor region and at least one second transistor region; using the patterned layer as a mask, etching the first work function layer to the i-th initial work function layer until the surface of the etching stop layer is exposed, the i-th initial work function layer becoming the i-th work function layer.

[0012] Optionally, the value of N can range from 2 to 10.

[0013] Optionally, the process of etching the first work function layer to the i-th initial work function layer includes a wet etching process.

[0014] Optionally, the etch stop layer includes: a first etch stop layer located on the second transistor region, and a second etch stop layer located on the first transistor region and the second transistor region.

[0015] Optionally, the method for forming the etch stop layer includes: forming an initial first etch stop layer on the first transistor region and the second transistor region; removing the initial first etch stop layer on the first transistor region to form a first etch stop layer on the second transistor region; and forming a second etch stop layer on the first transistor region and the first etch stop layer on the second transistor region.

[0016] Optionally, the process for removing the initial first etch stop layer on the first transistor region includes a dry etching process.

[0017] Optionally, the difference between the etch stop layer thickness on the second transistor region and the etch stop layer thickness on the first transistor region is a first difference, and the difference between the number of patterning steps performed on the second transistor region and the number of patterning steps performed on the first transistor region is a second difference, wherein the first difference and the second difference are positively correlated.

[0018] Optionally, the second difference is equal to 1; the first difference ranges from 5 angstroms to 20 angstroms.

[0019] Optionally, the material of the etch stop layer includes tantalum nitride; the material of the work function structure includes titanium nitride.

[0020] Optionally, before forming the etch stop layer, the method for forming the semiconductor structure further includes: forming a gate dielectric layer on the substrate and a bottom work function layer on the gate dielectric layer.

[0021] Optionally, the material of the bottom work function layer includes titanium nitride.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0023] In the semiconductor structure formation method provided by the present invention, the number of patterning steps performed on each of the second transistor regions is greater than the number of patterning steps performed on each of the first transistor regions. Therefore, the thickness damage to the etch stop layer on the second transistor region is greater than the thickness damage to the etch stop layer on the first transistor region. Since the thickness of the formed etch stop layer on the second transistor region is greater than that on the first transistor region, the thickness difference between the etch stop layers on the second and first transistor regions can compensate for the additional thickness damage to the etch stop layer on the second transistor region. This compensates for the thickness loss of the etch stop layer on the second transistor region, making the thickness of the etch stop layer more uniform, improving the stability of the device's threshold voltage, and improving device performance. Attached Figure Description

[0024] Figures 1 to 12This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0025] As described in the background section, in the prior art, multiple etching processes are typically used to adjust the thickness of the work function metal layer on different transistors. However, in the etching process for adjusting the thickness of the work function metal layer, because the number of etching cycles for the work function metal layer on each transistor is different, the work function metal layer on some transistors is easily over-damaged, thereby affecting the stability of the threshold voltage of the field-effect transistor and thus affecting the device performance.

[0026] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, wherein the thickness of the etch stop layer formed on the second transistor region is greater than the thickness on the first transistor region. The thickness difference between the etch stop layers on the second transistor region and the first transistor region can compensate for the additional thickness damage suffered by the etch stop layer on the second transistor region, thereby compensating for the thickness loss of the etch stop layer on the second transistor region, making the thickness of the etch stop layer more uniform, improving the stability of the threshold voltage of the device, and improving the device performance.

[0027] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] Figures 1 to 12 This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.

[0029] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1 A partially enlarged cross-sectional view of regions a, b, c, d, e, and f is provided, and a substrate 201 is provided, the substrate 201 including a plurality of first transistor regions A and at least one second transistor region B.

[0030] In this embodiment, the substrate 201 includes several discrete fin structures (not shown). The material of the substrate 201 includes silicon, silicon-germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. Specifically, in this embodiment, the material of the substrate 201 is silicon.

[0031] In the subsequent formation of the functional structure, several cycles of deposition and etching processes are performed on the first transistor region A and the second transistor region B. Each cycle of deposition and etching processes includes a deposition step and a patterning step after the deposition step. The number of patterning steps performed on the second transistor region B is more than the number of patterning steps performed on the first transistor region A.

[0032] In this embodiment, each first transistor region A and each second transistor region B contains a transistor device, and the transistor devices in each transistor region require different operating voltages. Subsequently, work function structures of different thicknesses are formed on each first transistor region A and each second transistor region B to respectively meet the operating voltage requirements of the transistor devices in each transistor region.

[0033] Specifically, the first transistor region A comprises four sub-transistor regions, denoted as: the first sub-transistor region I, containing a PFET ultra-low voltage threshold device (PULVT); the second sub-transistor region II, containing a PFET low voltage threshold device (PLVT); the third sub-transistor region III, containing a PFET standard voltage threshold device (PSVT); and the fourth sub-transistor region IV, containing an NFET standard voltage threshold device (NSVT). The second transistor region B comprises two sub-transistor regions, denoted as: the fifth sub-transistor region V, containing an NFET low voltage threshold device (NLVT); and the sixth sub-transistor region VI, containing an NFET ultra-low voltage threshold device (NULVT). The thickness of the work function structure required on the first sub-transistor region I to the sixth sub-transistor region VI decreases sequentially to meet the different operating voltage requirements of the transistor devices on each sub-transistor region.

[0034] Please continue to refer to this. Figure 1 and Figure 2 A gate dielectric layer (not shown) is formed on the substrate 201, and a bottom work function layer 202 is formed on the gate dielectric layer.

[0035] In this embodiment, the material of the bottom work function layer 202 includes titanium nitride.

[0036] Next, an etch stop layer is formed on each of the first transistor regions A and each of the second transistor regions B, wherein the thickness of the etch stop layer on each of the second transistor regions B is greater than the thickness of the etch stop layer on each of the first transistor regions A.

[0037] In this embodiment, the etch stop layer includes: a first etch stop layer located on the second transistor region B, and a second etch stop layer located on the first transistor region A and the second transistor region B.

[0038] In this embodiment, the detailed steps for forming the etch stop layer are as follows: Figures 2 to 3 As shown.

[0039] Please refer to Figure 3A first etch stop layer 203 is formed on the second transistor region B.

[0040] The first etch stop layer 203 is located only on the second transistor region B. Therefore, after the second etch stop layer is subsequently formed, the overall thickness of the etch stop layer on the second transistor region B is greater than the overall thickness of the etch stop layer on the first transistor region A.

[0041] Specifically, the method for forming the first etch stop layer 203 includes: forming an initial first etch stop layer (not shown) on the first transistor region A and the second transistor region B; removing the initial first etch stop layer on the first transistor region A to form the first etch stop layer 203 located on the second transistor region B.

[0042] In this embodiment, the process of removing the initial first etch stop layer on the first transistor region A includes a dry etching process.

[0043] Please refer to Figure 4 A second etch stop layer 204 is formed on the first transistor region A and the first etch stop layer 203 of the second transistor region B.

[0044] Since each of the second transistor regions B has a first etch stop layer 203 and a second etch stop layer 204, while each of the first transistor regions A only has a second etch stop layer 204, the overall thickness of the etch stop layer 205 on the second transistor region B is greater than the overall thickness of the etch stop layer 205 on the first transistor region A.

[0045] During the subsequent cyclic deposition etching process, the number of patterning steps performed on each of the second transistor regions B is greater than the number of patterning steps performed on the first transistor region A. There is a thickness difference between the etch stop layer 205 on each of the second transistor regions B and each of the first transistor regions A. This thickness difference can compensate for the additional thickness damage suffered by the etch stop layer 205 on the second transistor region B during the patterning steps, thereby making up for the thickness loss of the etch stop layer 205 on the second transistor region B, improving the stability of the threshold voltage of the transistor device, and improving the device performance.

[0046] In this embodiment, the thickness of the first etch stop layer 203 is 5 angstroms to 20 angstroms; the thickness of the second etch stop layer 204 is 5 angstroms to 20 angstroms.

[0047] In this embodiment, the material of the etch stop layer 205 includes tantalum nitride.

[0048] After forming the etch stop layer 205, several cycles of deposition and etching processes are performed on the first transistor region A and the second transistor region B until power function structures are formed on the first transistor region A and the second transistor region B respectively, and the thickness of each power function structure is different. The power function structure includes several power function layers. Each cycle of deposition and etching process includes a deposition step and a patterning step after the deposition step. The number of patterning steps performed on the second transistor region B is more than the number of patterning steps performed on the first transistor region A. Each cycle of deposition and etching process includes: depositing an initial power function layer on each first transistor region A and each second transistor region B; and patterning the initial power function layer to expose the surface of the etch stop layer 205 of any first transistor region A, any second transistor region B, or any first transistor region A and at least one second transistor region B, so as to form a power function layer.

[0049] Specifically, the sum of the number of the first transistor region A and the number of the second transistor region B is N+1, the number of cycles of deposition and etching is N, where N is a natural number greater than or equal to 2; the work function structure includes several work function layers, and the maximum number of work function layers is N.

[0050] In the first cycle of deposition etching process, a first work function layer is formed that exposes part of the etching stop layer 205.

[0051] Subsequently, in the deposition step of the i-th cycle deposition etching process, an i-th initial work function layer is deposited, which is located on the exposed surface of the etch stop layer 205 and the surface of the (i-1)-th work function layer; in the patterning step of the i-th cycle deposition etching process, the i-th initial work function layer is patterned to form the i-th work function layer; the (i-1)-th work function layer is the work function layer formed in the (i-1)-th cycle deposition etching process, and the value of i is in the range of 1 < i ≤ N.

[0052] In this embodiment, the cyclic deposition etching process is repeated 5 times. The maximum number of work function layers in the formed work function structure is 5.

[0053] Specifically, the process of forming the work function structure is as follows: Figures 4 to 11 As shown.

[0054] First, a first cycle of deposition and etching is performed to form the first work function layer, exposing part of the etch stop layer 205. Specifically, the process of performing the first cycle of deposition and etching is as follows: Figure 4 and Figure 5 As shown.

[0055] Please refer to Figure 5An initial work function layer 221 is formed by depositing an etch stop layer 205 on the surface of each first transistor region A and each second transistor region B.

[0056] In this embodiment, the material of the first initial work function layer 221 includes titanium nitride.

[0057] The thickness of the first initial work function layer 221 ranges from 5 angstroms to 30 angstroms. The formation process of the first initial work function layer 221 includes atomic layer deposition.

[0058] Please refer to Figure 6 The first initial work function layer 221 is patterned to expose the surface of the etch stop layer 205 on the second sub-transistor region II, thereby forming the first work function layer 211.

[0059] The purpose of graphically representing the first initial work function layer 221 is to remove the first initial work function layer 221 on the second sub-transistor region II while retaining the first initial work function layer 221 on the first sub-transistor region I, thereby creating a difference in the thickness of the first work function layer 211 on the first sub-transistor region I and the second sub-transistor region II.

[0060] In this embodiment, the method for patterning the first initial work function layer 221 includes: forming a patterned layer (not shown) on the first initial work function layer 221, wherein the patterned layer has a patterned opening that exposes the first initial work function layer 221 on the second sub-transistor region II; using the patterned layer as a mask, etching the first initial work function layer 221 until the surface of the etch stop layer 205 is exposed.

[0061] Specifically, the etching process for the first initial work function layer 221 includes a wet etching process. The parameters of the wet etching process include: the etching solution used includes ammonia.

[0062] Specifically, the method for forming the patterned layer includes: forming an initial patterned layer (not shown) on the first initial work function layer 221, and a photolithographic patterned layer (not shown) on the initial patterned layer, the photolithographic patterned layer having a photolithographic patterned opening that exposes the second sub-transistor region II; using the photolithographic patterned layer as a mask, etching the initial patterned layer until the surface of the first initial work function layer 221 is exposed, so as to form the patterned layer.

[0063] In this embodiment, the initial patterning layer includes an anti-reflection layer (not shown) and a low-temperature oxide layer (not shown) located on the anti-reflection layer.

[0064] Figure 7and Figure 8 This is a cross-sectional structural diagram of the second cycle of deposition and etching process.

[0065] Please refer to Figure 7 A second initial work function layer 222 is formed on the surface of the first work function layer 211, and the second initial work function layer 222 is also located on the surface of the exposed etch stop layer 205.

[0066] In this embodiment, the second initial work function layer 222 is also located on the surface of the first work function layer 211 of the third sub-transistor region III, the fourth sub-transistor region IV, the fifth sub-transistor region V, and the sixth sub-transistor region VI.

[0067] In this embodiment, the material of the second initial work function layer 222 includes titanium nitride.

[0068] Please refer to Figure 8 The first work function layer 211 and the second initial work function layer 222 are patterned to expose the surface of the etch stop layer 205 of the third sub-transistor region III, and the second initial work function layer 222 becomes the second work function layer 212.

[0069] Since the second work function layer 212 is located on the surface of the first work function layer 211 on the first sub-transistor region I and the surface of the etch stop layer 205 on the second sub-transistor region II, the first sub-transistor region I has a first work function layer 211 and a second work function layer 212, while the second sub-transistor region II only has a second work function layer 212. This results in the overall thickness of the work function layer on the first sub-transistor region I being greater than the overall thickness of the work function layer on the second sub-transistor region II.

[0070] In this embodiment, the method for patterning the first work function layer 211 and the second initial work function layer 222 includes: forming a patterned layer (not shown) on the second initial work function layer 222, wherein the patterned layer has a patterned opening (not shown) that exposes the third sub-transistor region III; using the patterned layer as a mask, etching the first work function layer 211 and the second initial work function layer 222 until the surface of the etching stop layer 205 is exposed.

[0071] Specifically, the etching process for the first work function layer 211 and the second initial work function layer 222 includes a wet etching process.

[0072] Figure 9 and Figure 10 This is a cross-sectional structural diagram of the third cycle deposition and etching process.

[0073] Please refer to Figure 9 A third initial work function layer 223 is formed on the surface of the second work function layer 212, and the third initial work function layer 223 is also located on the surface of the exposed etch stop layer 205.

[0074] Please refer to Figure 10 The first work function layer 211, the second work function layer 212, and the third initial work function layer 223 are patterned to expose the etch stop layer 205 surfaces of the fourth sub-transistor region IV, the fifth sub-transistor region V, and the sixth sub-transistor region VI. The third initial work function layer 223 becomes the third work function layer 213.

[0075] The method for patterning the first work function layer 211, the second work function layer 212, and the third initial work function layer 223 includes: forming a patterned layer on the third initial work function layer 223, wherein the patterned layer has patterned openings that expose the fourth sub-transistor region IV, the fifth sub-transistor region V, and the sixth sub-transistor region VI of the third initial work function layer 223; using the patterned layer as a mask, etching from the first work function layer 211 to the third initial work function layer 223 until the surface of the etch stop layer 205 is exposed.

[0076] Because of the diffusion effect between the etch stop layer 205 and each work function layer, the etch stop layer 205 is damaged to some extent during the patterning process, which reduces the thickness of the etch stop layer 205.

[0077] In this cyclic deposition etching process, a first patterning step was performed on each second transistor region B. In subsequent cyclic deposition etching processes, a second patterning step will be performed on each second transistor region B, resulting in greater damage to the etch stop layer 205 on each second transistor region B.

[0078] Figure 11 This is a cross-sectional structural diagram of the fourth cycle of deposition and etching process.

[0079] Please refer to Figure 11 A fourth initial work function layer (not shown) is formed on the surface of the third work function layer 213. The fourth initial work function layer is also located on the surface of the exposed etch stop layer 205. The fourth initial work function layer is patterned to expose the surface of the etch stop layer 205 of the fifth sub-transistor region V. The fourth initial work function layer becomes the fourth work function layer 214.

[0080] In this cyclic deposition etching process, a second patterning step was performed on the fifth sub-transistor region V, which caused secondary damage to the etch stop layer 205 on the fifth sub-transistor region V. However, only one patterning step was performed on each first transistor region A, so the etch stop layer 205 on each first transistor region A was only damaged once. As a result, the thickness damage of the etch stop layer 205 on the fifth sub-transistor region V is greater than that on the etch stop layer 205 of each first transistor region A.

[0081] Since the thickness of the etch stop layer 205 on the fifth sub-transistor region V is greater than the thickness of the etch stop layer 205 on each of the first transistor regions A, the additional second damage to the etch stop layer 205 on the fifth sub-transistor region V is compensated, thereby making up for the thickness loss of the etch stop layer 205 on the fifth sub-transistor region V.

[0082] In this embodiment, the method for graphically representing the fourth initial work function layer and Figure 5 The method for graphically representing the first initial work function layer 221 is the same as that used in the previous section, and will not be elaborated here.

[0083] Figure 12 This is a cross-sectional structural diagram of the fifth cycle of deposition and etching process.

[0084] Please refer to Figure 12 A fifth initial work function layer (not shown) is formed on the surface of the fourth work function layer 214. The fifth initial work function layer is also located on the surface of the exposed etch stop layer 205. The fourth work function layer 214 and the fifth initial work function layer are patterned to expose the surface of the etch stop layer 205 of the sixth sub-transistor region VI. The fifth initial work function layer becomes the fifth work function layer 215.

[0085] In this cyclic deposition etching process, a second patterning step was also performed on the sixth sub-transistor region VI, which caused secondary damage to the etching stop layer 205 on the sixth sub-transistor region VI.

[0086] The first work function layer 211 to the fifth work function layer 215 together constitute the work function structure (not shown) located on the etch stop layer 205, and the thickness of the work function structure on each first transistor region A and each second transistor region B is different.

[0087] By performing a five-cycle deposition and etching process, work function structures of different thicknesses were formed on the first sub-transistor region I to the sixth sub-transistor region VI, in order to meet the different operating voltages required by the transistor devices on the first sub-transistor region I to the sixth sub-transistor region VI.

[0088] Specifically, the number of work function layers on the first sub-transistor region I to the sixth sub-transistor region VI gradually decreases. The first sub-transistor region I has the first work function layer 211 to the fifth work function layer 215, so it has the largest work function structure thickness. The sixth sub-transistor region VI does not have any work function layer, thereby exposing the surface of the etch stop layer 205.

[0089] Because each second transistor region B (i.e., the fifth sub-transistor region V and the sixth sub-transistor region VI) undergoes two patterning steps in each deposition and etching cycle, while each first transistor region A undergoes only one patterning step, the thickness damage to the etch stop layer 205 on each second transistor region B is greater than that on each first transistor region A. Since the thickness of the formed etch stop layer 205 on each second transistor region B is greater than its thickness on each first transistor region A, the thickness difference between the etch stop layers 205 on the second transistor region B and the first transistor region A can compensate for the additional thickness damage to the etch stop layer 205 on the second transistor region B. This compensates for the thickness loss of the etch stop layer 205 on the second transistor region B, making the thickness of the etch stop layer 205 more uniform, thereby improving the stability of the device's threshold voltage and enhancing device performance.

[0090] The difference between the thickness of the etch stop layer 205 on the second transistor region B and the thickness of the etch stop layer 205 on the first transistor region A is the first difference, and the difference between the number of patterning steps performed on the second transistor region B and the number of patterning steps performed on the first transistor region A is the second difference. The first difference and the second difference are positively correlated.

[0091] Specifically, in this embodiment, the second difference is equal to 1; the range of the first difference is 5 angstroms to 20 angstroms.

[0092] In other embodiments, the second difference is greater than 1. Whenever the second difference increases by 1, the first difference increases by 5 to 20 angstroms, thereby effectively compensating for the additional thickness loss of the etch stop layer 205 on the second transistor region B.

[0093] In this embodiment, the method for graphically representing the fourth work function layer 214 and the fifth initial work function layer is as follows: Figure 7 The method for graphically representing the first work function layer 211 and the second initial work function layer 222 is the same, and will not be elaborated here.

[0094] In this embodiment, the thickness of each work function layer ranges from 5 angstroms to 30 angstroms.

[0095] In this embodiment, the material of each work function layer includes titanium nitride, that is, the material of the work function structure includes titanium nitride.

[0096] In other embodiments, the number of cycles of the deposition etching process is 2 to 10.

[0097] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a plurality of first transistor regions and at least one second transistor region; An etch stop layer is formed on each of the first transistor regions and each of the second transistor regions, wherein the thickness of the etch stop layer on each of the second transistor regions is greater than the thickness of the etch stop layer on each of the first transistor regions; After forming the etch stop layer, several cycles of deposition and etching processes are performed on the first transistor region and the second transistor region until power function structures are formed on the first transistor region and the second transistor region respectively, and the thickness of each power function structure is different. The power function structure includes several power function layers. Each cycle of deposition and etching process includes a deposition step and a patterning step after the deposition step. The number of patterning steps performed on the second transistor region is more than the number of patterning steps performed on the first transistor region. Each cycle of deposition and etching process includes: depositing to form an initial power function layer on each first transistor region and each second transistor region. The initial work function layer is patterned to expose the etch stop layer surfaces of any first transistor region, any second transistor region, or any first transistor region and at least one second transistor region, to form the work function layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sum of the number of the first transistor region and the number of the second transistor region is N+1, and the number of cycles of deposition and etching is N, where N is a natural number greater than or equal to 2. The work function structure includes several work function layers, and the maximum number of work function layers is N.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the first cycle of deposition etching process, a first work function layer is formed that exposes part of the etching stop layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the deposition step of the i-th cycle deposition etching process, the i-th initial work function layer is deposited and formed, the i-th initial work function layer is located on the surface of the exposed etching stop layer and the surface of the (i-1)-th work function layer; In the patterning step of the i-th cycle deposition and etching process, the i-th initial work function layer is patterned to form the i-th work function layer; the (i-1)-th work function layer is the work function layer formed in the (i-1)-th cycle deposition and etching process, and the value of i is in the range of 1 < i ≤ N.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, In the i-th cycle deposition and etching process, the method for patterning the i-th initial work function layer includes: forming a patterned layer on the i-th initial work function layer, wherein the patterned layer has a patterned opening that exposes the i-th initial work function layer on any first transistor region or any second transistor region; using the patterned layer as a mask, etching the first work function layer to the i-th initial work function layer until the surface of the etching stop layer is exposed, wherein the i-th initial work function layer becomes the i-th work function layer.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, In the i-th cycle deposition and etching process, the method for patterning the i-th initial work function layer includes: forming a patterned layer on the i-th initial work function layer, the patterned layer having patterned openings exposing the i-th initial work function layer on any first transistor region and at least one second transistor region; using the patterned layer as a mask, etching the first work function layer to the i-th initial work function layer until the surface of the etching stop layer is exposed, and the i-th initial work function layer becomes the i-th work function layer.

7. The method for forming a semiconductor structure as described in claim 2, characterized in that, The value of N ranges from 2 to 10.

8. The method for forming a semiconductor structure as described in claim 5, characterized in that, The etching process from the first work function layer to the i-th initial work function layer includes a wet etching process.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etch stop layer includes: a first etch stop layer located on the second transistor region, and a second etch stop layer located on the first transistor region and the second transistor region.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the etch stop layer includes: forming an initial first etch stop layer on the first transistor region and the second transistor region; removing the initial first etch stop layer on the first transistor region to form a first etch stop layer on the second transistor region; and forming a second etch stop layer on the first transistor region and the first etch stop layer on the second transistor region.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process for removing the initial first etch stop layer on the first transistor region includes a dry etching process.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The difference between the etch stop layer thickness on the second transistor region and the etch stop layer thickness on the first transistor region is the first difference, and the difference between the number of patterning steps performed on the second transistor region and the number of patterning steps performed on the first transistor region is the second difference. The first difference and the second difference are positively correlated.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The second difference is equal to 1; the first difference ranges from 5 angstroms to 20 angstroms.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the etching stop layer includes tantalum nitride; the material of the work function structure includes titanium nitride.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the etching stop layer, the method further includes forming a gate dielectric layer on the substrate and a bottom work function layer on the gate dielectric layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The material of the bottom work function layer includes titanium nitride.

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