Package substrate, power supply noise testing device, and power supply noise testing method

Abstract

The embodiment of the present disclosure provides a packaging substrate, a power supply noise testing device and a power supply noise testing method. The packaging substrate comprises a plurality of pad arrays, and each pad array comprises at least a power supply pad. The power supply pads belonging to the same power supply type in the plurality of pad arrays are divided into a test pad and a power supply pad set. The power supply pad set comprises other power supply pads belonging to the same power supply type and excluding the test pad, and the power supply pads in the power supply pad set are all electrically connected together. The test pad is used for noise testing on the internal power supply corresponding to the same power supply type in the chip to be tested. In this way, the power supply noise inside the chip can be tested, and the accuracy of the test can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a packaging substrate, a power supply noise testing device, and a power supply noise testing method. Background Technology

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speed when manufacturing and using devices such as computers. In order to obtain faster data transmission speeds, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.

[0003] Taking Synchronous Dynamic Random Access Memory (SDRAM) as an example, to verify power integrity, SDRAM chips typically require power signal testing during operation. This can be achieved by using a signal test board to bring out the power signals for testing, or by adding power test points to the system motherboard. However, in the SDRAM chip packaging design, pins with the same power signals are often connected together, making it impossible to accurately measure the internal power noise of the chip during power signal testing. Summary of the Invention

[0004] This disclosure provides a packaging substrate, a power supply noise testing device, and a power supply noise testing method, which can not only realize the testing of power supply noise inside the chip, but also improve the accuracy of the test.

[0005] In a first aspect, embodiments of this disclosure provide a packaging substrate, the packaging substrate including a plurality of pad arrays, and each pad array including at least a power pad; wherein:

[0006] Power pads belonging to the same power type in multiple pad arrays are divided into test pads and power pad sets. The power pad set includes other power pads of the same power type except for the test pads, and all power pads in the power pad set are electrically connected together. The test pads are used to perform noise testing on the internal power supply of the same power type in the chip under test.

[0007] In some embodiments, the packaging substrate includes four pad arrays; wherein the four pad arrays are arranged in a vertically symmetrical and horizontally symmetrical structure.

[0008] In some embodiments, the packaging substrate further includes a conductive layer; wherein, in the conductive layer, the power pads in the power pad set are electrically connected by copper pouring to form a first power network, and the test pads are independent of the first power network.

[0009] In some embodiments, the surface of the packaging substrate is provided with gold fingers; wherein, in the same power type, the distance between the test pad and the gold fingers is smaller than the distance between the power pad and the gold fingers in the power pad set.

[0010] In some embodiments, a chip under test (DUT) is further placed on the surface of the packaging substrate, and the DUT includes multiple pin arrays, each pin array including at least a power supply pin; wherein, the power supply pins belonging to the same power type in the multiple pin arrays are divided into test pins and a set of power supply pins; wherein, the power supply pins in the set of power supply pins are electrically connected to the power pads in the set of power pads, and the test pins are electrically connected to the test pads, so that the test pads can perform noise testing on the internal power supply of the same power type in the DUT through the test pins.

[0011] In some embodiments, the packaging substrate is further provided with metal vias and metal traces; wherein, the test pads are electrically connected to the gold fingers through the metal traces and metal vias, and the gold fingers and test pins are electrically connected by wire bonding, so as to realize that the test pads and test pins are electrically connected together.

[0012] In some embodiments, each pad array includes at least a VDD1 power pad, a VDD2 power pad, and a VDDQ power pad; wherein the same power type is any one of the VDD1 power type, the VDD2 power type, and the VDDQ power type.

[0013] In some embodiments, power pads belonging to the VDD1 power type in the multiple pad arrays are divided into VDD1 power test pads and a VDD1 power pad set; wherein, all power pads in the VDD1 power pad set are electrically connected to form a VDD1 power network, and the VDD1 power test pads are independent of the VDD1 power network, and the VDD1 power test pads are used to perform noise testing on the VDD1 power supply inside the chip under test; power pads belonging to the VDD2 power type in the multiple pad arrays are divided into VDD2 power test pads and a VDD2 power pad set; wherein, the power pads in the VDD2 power pad set are... All pads are electrically connected to form a VDD2 power network, and the VDD2 power test pad is independent of the VDD2 power network. The VDD2 power test pad is used to perform noise testing on the VDD2 power supply inside the chip under test. The power pads of the VDDQ power type in the multiple pad array are divided into VDDQ power test pads and VDDQ power pad sets. Among them, all power pads in the VDDQ power pad set are electrically connected to form a VDDQ power network, and the VDDQ power test pad is independent of the VDDQ power network. The VDDQ power test pad is used to perform noise testing on the VDDQ power supply inside the chip under test.

[0014] In a second aspect, embodiments of this disclosure provide a power supply noise testing apparatus, which includes a packaging substrate, a chip under test, and a test board as described in the first aspect; wherein:

[0015] The test board is equipped with a first test point corresponding to the first power type;

[0016] The chip under test includes at least a power supply pin corresponding to a first power supply type, and the power supply pins are divided into a first test pin and a first power supply pin set other than the first test pin.

[0017] The packaging substrate includes at least a power pad corresponding to a first power type, and the power pad is divided into a first test pad and a set of first power pads excluding the first test pad.

[0018] In this configuration, the power pins in the first power pin set are electrically connected to the power pads in the first power pad set, the first test pin is electrically connected to the first test pad, and the first test pad is also electrically connected to the first test point, so that the first test point can perform noise testing on the internal power supply corresponding to the first power type in the chip under test through the first test pad and the first test pin.

[0019] In some embodiments, the chip under test, the packaging substrate, and the test board are stacked sequentially.

[0020] In some embodiments, the test board is further provided with multiple solder joint arrays corresponding to multiple pad arrays in the packaging substrate, and each solder joint array includes at least a power solder joint; wherein, the power solder joints belonging to the first power type in the multiple solder joint arrays are divided into a first test solder joint and a first power solder joint set, the power solder joints in the first power solder joint set are electrically connected to the power pads in the first power pad set, and all the power solder joints in the first power solder joint set are electrically connected together to form a first power network; wherein, the first test solder joint is independent of the first power network.

[0021] In some embodiments, the test board is further provided with a first metal trace; wherein, the first test pad is connected to the first test solder joint, and the first test solder joint is electrically connected to the first test point through the first metal trace, so as to realize the electrical connection between the first test pad and the first test point.

[0022] In some embodiments, the test board is further provided with a first resistor identifier, and the first resistor identifier includes a first solder joint and a second solder joint; wherein the first solder joint is connected to a first test solder joint, and the second solder joint is connected to a first power network.

[0023] In some embodiments, in test mode, the first resistor is not soldered at the first resistor mark so that the first test solder joint is disconnected from the first power network; in operating mode, the first resistor is soldered at the first resistor mark so that the first test solder joint is electrically connected to the first power network.

[0024] In some embodiments, the resistance of the first resistor is 0 ohms.

[0025] In some embodiments, the first power supply type is any one of VDD1, VDD2, and VDDQ power supply types; wherein, on the test board, different first power supply types are provided with different first test points and different first resistor labels.

[0026] Thirdly, embodiments of this disclosure provide a power supply noise testing method, applied to the power supply noise testing apparatus described in the second aspect, the method comprising:

[0027] In test mode, noise test is performed on the internal power supply corresponding to the first power type in the chip under test through the first test point on the test board; wherein, the first test point has a corresponding relationship with the first power type, and the first power type is any one of VDD1 power type, VDD2 power type and VDDQ power type.

[0028] In some embodiments, the test board is further provided with multiple solder joint arrays corresponding to multiple pad arrays in the packaging substrate, and each solder joint array includes at least a power solder joint; wherein, the power solder joints belonging to the first power type in the multiple solder joint arrays are divided into a first test solder joint and a first power solder joint set, the power solder joints in the first power solder joint set are electrically connected to the power pads in the first power pad set, and all the power solder joints in the first power solder joint set are electrically connected together to form a first power network; wherein, the first test solder joint is independent of the first power network.

[0029] In some embodiments, the test board is further provided with a first resistor mark, and the method further includes: in the working mode, determining that a first resistor is soldered at the first resistor mark, and controlling the first test solder joint to be electrically connected to the first power network through the first resistor.

[0030] In some embodiments, the method further includes: in test mode, determining that a first resistor is not soldered at a first resistor marker, such that the first test solder joint is disconnected from the first power network.

[0031] This disclosure provides a packaging substrate, a power supply noise testing device, and a power supply noise testing method. The packaging substrate includes multiple pad arrays, each of which includes at least a power pad. Power pads belonging to the same power type within the multiple pad arrays are divided into test pads and a power pad set. The power pad set includes other power pads of the same power type besides the test pads, and all power pads in the power pad set are electrically connected together. The test pads are used to perform noise testing on the internal power supply of the same power type in the chip under test. The power supply noise testing device includes a packaging substrate, a chip under test (DUT), and a test board. The test board has a first test point corresponding to a first power type. The DUT includes at least power pins corresponding to the first power type, and these power pins are divided into a first test pin and a set of first power pins excluding the first test pins. The packaging substrate includes at least power pads corresponding to the first power type, and these power pads are divided into a first test pad and a set of first power pads excluding the first test pads. The power pins in the first power pin set are electrically connected to the corresponding power pads in the first power pad set, the first test pins are electrically connected to the first test pads, and the first test pads are also electrically connected to the first test point, so that the first test point can perform noise testing on the internal power supply corresponding to the first power type in the DUT through the first test pads and the first test pins. In this way, based on the power supply noise testing device, by dedicating a separate pin on the packaging substrate as a first test pin and setting a first test point on the test board, and then connecting the first test pin to the first test point, not only can the signal used to test power supply noise be led out through the first test point, but the test signal is also made independent of the first power network corresponding to the first power type. Thus, by performing noise testing on the internal power supply of the chip under test through the first test point on the test board, the accuracy of power supply noise testing can be improved. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the layout of a packaging substrate;

[0033] Figure 2 This is a schematic diagram of the test results for chip power supply noise.

[0034] Figure 3 This is a schematic diagram of the composition structure of a packaging substrate provided in an embodiment of the present disclosure;

[0035] Figure 4 This provides a schematic diagram of the composition structure of another packaging substrate for embodiments of this disclosure;

[0036] Figure 5 This is a partially enlarged schematic diagram of a packaging substrate provided in an embodiment of the present disclosure;

[0037] Figure 6 This is a schematic diagram of a specific structure of a packaging substrate provided in an embodiment of the present disclosure;

[0038] Figure 7 This is a schematic diagram of the composition structure of a power supply noise testing device provided in an embodiment of the present disclosure;

[0039] Figure 8 This disclosure provides a schematic diagram of the composition of another power supply noise testing device according to an embodiment.

[0040] Figure 9 A schematic diagram illustrating the test results of an internal power supply noise provided in an embodiment of this disclosure;

[0041] Figure 10 This is a flowchart illustrating a power supply noise testing method provided in an embodiment of the present disclosure. Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0044] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0045] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0046] It is understandable that, taking Synchronous Dynamic Random Access Memory (SDRAM) as an example, SDRAM chips generally need to test the power supply signal during operation to verify power integrity.

[0047] In related technologies, power signals can be extracted and tested using an SDRAM signal test board; alternatively, power test points can be added to the system motherboard. However, in the SDRAM chip packaging substrate design, pins with the same power signals are connected together, making it impossible to accurately measure the internal power noise of the chip when testing the power supply.

[0048] For an SDRAM chip, at least three types of power signals can be included, such as VDD1 power type, VDD2 power type, and VDDQ power type, and each power type can have multiple power pins. Specifically, the chip can be provided with multiple VDD1 power pins, multiple VDD2 power pins, and multiple VDDQ power pins, which can be electrically connected to the corresponding VDD1 power pads, VDD2 power pads, and VDDQ power pads on the package substrate, respectively.

[0049] For example, see Figure 1 This illustrates a layout diagram of a packaging substrate. For example... Figure 1 As shown, the system can include two types of power pads: VDD2 power pads and VDDQ power pads. All VDD2 power pads are connected together to form a VDD2 power network, and all VDDQ power pads are connected together to form a VDDQ power network. This connection effectively links all power pins corresponding to the VDD2 power type in the chip together; similarly, the connection of all VDDQ power pads links all power pins corresponding to the VDDQ power type in the chip together. Similarly, for VDD1 power pads (not shown in the figure) belonging to the VDD1 power type, all of these pads will be connected together on the package substrate, thus linking all power pins of the VDD1 power type in the chip together.

[0050] based on Figure 1 The packaging substrate, Figure 2 A schematic diagram of the test results for chip power supply noise is shown. For example... Figure 2 As shown, (a) presents the test results for power supply noise inside the chip, and (b) presents the test results for power supply noise outside the chip. Internal power supply noise refers to the power supply noise actually measured inside the chip, while external power supply noise refers to the power supply noise measured outside the chip using conventional methods. Figure 2In (a), the bold solid box reflects that the power supply noise inside the chip is very serious; however, in the corresponding period in (b), the power supply noise measured outside the chip is almost non-existent, as shown in the bold dashed box.

[0051] In other words, in related technologies, the VDD1, VDD2, and VDDQ power pads are all individually connected together on the package substrate; that is, power pins corresponding to the same power signal are connected together. Therefore, power noise testing in these technologies cannot differentiate between them. The external test measures the overall noise of a single type of power signal, making it impossible to accurately reflect the actual internal noise of the chip when using conventional methods. Consequently, it is impossible to directly measure the accurate internal power noise of the chip during power supply testing.

[0052] Based on this, the present disclosure provides a packaging substrate, which includes multiple pad arrays, and each pad array includes at least a power pad. The power pads belonging to the same power type in the multiple pad arrays are divided into test pads and a power pad set. The power pad set includes other power pads belonging to the same power type except for the test pads, and all power pads in the power pad set are electrically connected together. The test pads are used to perform noise testing on the internal power supply corresponding to the same power type in the chip under test. This disclosure also provides a power supply noise testing device and a power supply noise testing method. The method is applied to the power supply noise testing device, which includes a packaging substrate, a chip under test (DUT), and a test board. The test board has a first test point corresponding to a first power type. The DUT includes at least power pins corresponding to the first power type, and these power pins are divided into a first test pin and a set of first power pins excluding the first test pins. The packaging substrate includes at least power pads corresponding to the first power type, and these power pads are divided into a first test pad and a set of first power pads excluding the first test pads. The power pins in the first power pin set are electrically connected to the corresponding power pads in the first power pad set. The first test pins are electrically connected to the first test pads, and the first test pads are also electrically connected to the first test point, so that the first test point can perform noise testing on the internal power supply corresponding to the first power type in the DUT through the first test pads and the first test pins.

[0053] In this way, based on the power supply noise testing device, by dedicating a separate pin on the packaging substrate as a first test pin and setting a first test point on the test board, and then connecting the first test pin to the first test point, not only can the signal used to test power supply noise be led out through the first test point, but the test signal is also made independent of the first power network corresponding to the first power type. Thus, by performing noise testing on the internal power supply of the chip under test through the first test point on the test board, the accuracy of power supply noise testing can be improved.

[0054] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0055] In one embodiment of this disclosure, see Figure 3 This illustrates a schematic diagram of the composition structure of a packaging substrate provided in an embodiment of this disclosure. For example... Figure 3 As shown, the package substrate 40 may include multiple pad arrays (such as pad array 401, pad array 402, pad array 403, and pad array 404), and each pad array includes at least a power pad; wherein:

[0056] Power pads belonging to the same power type in multiple pad arrays are divided into test pads 411 and power pad sets. The power pad set may include other power pads 412 belonging to the same power type besides test pads 411, and all power pads in the power pad set are electrically connected together.

[0057] Test pad 411 can be used to perform noise testing on the internal power supply of the same power type in the chip under test.

[0058] It should be noted that, in the embodiments disclosed herein, the package substrate (SUB) provides electrical connection, protection, support, heat dissipation, and assembly functions for the chip under test, thereby achieving multi-pin configuration, reducing the size of the packaged product, improving electrical performance and heat dissipation, and enabling ultra-high density or multi-chip modularization. Here, the package substrate is the carrier for semiconductor chip packaging. Its main function is to fix the diced wafer (Die) onto the package substrate, and to achieve electrical connection between the Die and the pads on the package substrate using ultra-fine metal wires or conductive resin.

[0059] It should also be noted that, in this embodiment, the chip under test (DUT) can refer to a wafer or die. The internal power supply within the die can include various power supply types, such as VDD1, VDD2, and VDDQ. Here, VDDQ can be considered as the power supply for the input / output buffer (IO buffer); VDD1 and VDD2 can be considered as the power supplies for the chip core, but VDD1 and VDD2 have different voltage levels. Therefore, noise testing of the internal power supply of the DUT can be performed on the internal power supply corresponding to the VDD1 power supply type, or on the internal power supply corresponding to the VDD2 power supply type, or on the internal power supply corresponding to the VDDQ power supply type; no limitation is made in this regard.

[0060] For example, such as Figure 3 As shown, taking the VDDQ power type as an example, there are 20 power pads belonging to the VDDQ power type (marked with black fill). For these 20 power pads, one can be selected as test pad 411, and the remaining 19 power pads (such as 412) form the power pad set corresponding to the VDDQ power type. All power pads in this power pad set are electrically connected together.

[0061] In other words, in this embodiment of the disclosure, there can be multiple power pads of the same power type, and these multiple power pads are not all electrically connected together. Specifically, for multiple power pads of the same power type, one can be set aside as a test pad, and then all the remaining power pads are electrically connected together. In this way, by using the set aside test pad to perform noise testing on the internal power supply of the chip under test, the internal power supply noise of the chip can be accurately measured.

[0062] In some embodiments, the packaging substrate 40 may include four pad arrays; wherein the four pad arrays are arranged in a vertically symmetrical and horizontally symmetrical structure.

[0063] It should also be noted that, in the embodiments disclosed herein, please refer to the specific details. Figure 3 The packaging substrate 40 may include pad arrays 401, 402, 403, and 404. These four pad arrays can be arranged in a horizontally symmetrical structure or a vertically symmetrical structure. In this way, the distribution of these pad arrays in the design of the packaging substrate 40 is symmetrical and the overall appearance is aesthetically pleasing.

[0064] In some embodiments, Figure 3 Based on the package substrate 40 shown, see... Figure 4 The packaging substrate 40 may also include a conductive layer 413; wherein, in the conductive layer 413, the power pads in the power pad set are electrically connected by copper pouring to form a first power network, and the test pad 411 is independent of the first power network.

[0065] It should be noted that in this embodiment, the packaging substrate 40 can be a multilayer board, wherein each layer can serve as a conductive layer. For example, for three power types—VDD1, VDD2, and VDDQ—different layers can electrically connect the power pads corresponding to different power types, and also allow for large-area copper pouring of the same power type. This improves current carrying capacity, reduces power impedance, effectively suppresses crosstalk between signals, and facilitates heat dissipation. For instance, regarding the multilayer conductive layers of the packaging substrate… Figure 1 It can be considered as a conductive layer. Figure 4 It can be considered as another conductive layer.

[0066] It should also be noted that, in the embodiments disclosed herein, such as Figure 4 As shown, taking the VDDQ power type as an example, in the VDDQ power noise test mode, except for the test pad 411, all other power pads are electrically connected together to form a VDDQ power network. However, the test pad 411 is not connected to the VDDQ power network, so as to facilitate subsequent noise testing of the VDDQ power supply using the test pad 411.

[0067] Furthermore, in some embodiments, the surface of the packaging substrate 40 is provided with gold fingers; wherein, in the same power type, the distance between the test pad and the gold fingers is smaller than the distance between the power pad and the gold fingers in the power pad set.

[0068] It should be noted that, in the embodiments disclosed herein, an independent test pad can be any power pad of the same power type. In one specific implementation, the selected test pad of the same power type should be as close as possible to the gold fingers on the package substrate 40 to minimize the trace length and loop size.

[0069] For example, see Figure 5 This illustration shows a partially enlarged schematic diagram of a packaging substrate provided in an embodiment of the present disclosure. Figure 5 The diagram illustrates the placement of the gold finger 414 on the package substrate. Therefore, for the same power type, when selecting test pads, the distance between the selected test pad and the gold finger must be less than the distance between other power pads and the gold finger.

[0070] Furthermore, in some embodiments, a chip under test (not shown) is also placed on the surface of the packaging substrate 40, and the chip under test includes multiple pin arrays, each pin array including at least a power supply pin; wherein:

[0071] In multiple pin arrays, power pins belonging to the same power type are divided into test pins and power pin sets. The power pins in the power pin set are electrically connected to the power pads in the power pad set, and the test pins are electrically connected to the test pads, so that the test pads can perform noise testing on the internal power supply of the same power type in the chip under test through the test pins.

[0072] It should be noted that, in the embodiments disclosed herein, for the same power type, not only do the power pads on the packaging substrate need to be divided to set aside one power pad as a test pad, and then all the other power pads are connected together; also, for the chip under test, the power pins of the chip under test need to be divided to set aside one power pin as a test pin, so that the test pad can perform noise testing on the internal power supply of the same power type in the chip under test through the test pin.

[0073] It should also be noted that, in this embodiment, there is a correspondence between the multiple pin arrays of the chip under test and the multiple pad arrays of the packaging substrate, with each pin connected to a corresponding pad on the packaging substrate. Here, for the chip under test, the multiple pin arrays are also symmetrically arranged horizontally and vertically.

[0074] For example, still taking the same power type as an example, after a test pin is set aside, the test pin is electrically connected to the corresponding test pad, and the remaining power pins are electrically connected to the corresponding power pads in the power pad set, so that all the remaining power pins are also electrically connected together; the set aside test pin is connected to the outside of the chip under test through the test pad, so that the noise test of the internal power supply of the same power type in the chip under test can be performed from the outside of the chip under test through the test pin, and the accuracy of power supply noise test can also be improved.

[0075] Furthermore, in some embodiments, the packaging substrate 40 is also provided with metal vias and metal traces; wherein, the test pads are electrically connected to the gold fingers through the metal traces and metal vias, and the gold fingers and test pins are electrically connected by wire bonding, so as to realize that the test pads and test pins are electrically connected together.

[0076] It should be noted that, in this embodiment, for the selected test pad 411, traces and vias are used to connect it to the gold fingers on the surface of the package substrate 40 via the back side of the package substrate 40, and then the gold wire is used to connect it to the power pin of the chip under test. Alternatively, for other power pads, traces and vias can also be used to connect them to the gold fingers on the surface of the package substrate 40 via the back side of the package substrate 40, and then the gold wire is used to connect them to other power pins of the chip under test, thus achieving electrical connection between the power pads of the package substrate 40 and the power pins of the chip under test.

[0077] For example, see Figure 6 This illustrates a schematic diagram of a specific structure of a packaging substrate 40 provided in an embodiment of this disclosure. For example... Figure 6 As shown, this may include: gold fingers 414, gold wires 415, the chip under test 416, and a pad array 417. (The rest of the text appears to be a fragment and doesn't translate directly.) Figure 6 As can be seen, a pad array 417 is provided on the back side of the packaging substrate 40. Taking the test pad in the pad array 417 as an example, it is connected from the back side of the packaging substrate 40 to the gold finger 414 provided on the surface of the packaging substrate 40 through the trace and via, and then connected to the test pin of the chip under test 416 through the gold wire 415, thereby realizing the electrical connection between the test pad and the test pin.

[0078] Furthermore, in some embodiments, each pad array includes at least a VDD1 power pad, a VDD2 power pad, and a VDDQ power pad; wherein the same power type is any one of the VDD1 power type, VDD2 power type, and VDDQ power type.

[0079] It should be noted that, in this embodiment, the power pads may include at least three types, such as VDD1 power pads, VDD2 power pads, and VDDQ power pads; correspondingly, the same power type can be any one of VDD1, VDD2, and VDDQ power types. The methods for power noise testing are similar for these three power types; each can be tested using a separate test pin to perform noise testing on the VDD1 power supply, the VDD2 power supply, or the VDDQ power supply in the chip under test.

[0080] In one specific embodiment, for a VDD1 power supply, the power pads belonging to the VDD1 power supply type in the multiple pad arrays are divided into VDD1 power supply test pads and a VDD1 power supply pad set; wherein, all the power pads in the VDD1 power supply pad set are electrically connected to form a VDD1 power supply network, and the VDD1 power supply test pads are independent of the VDD1 power supply network, and the VDD1 power supply test pads are used to perform noise testing on the VDD1 power supply inside the chip under test.

[0081] In another specific embodiment, for VDD2 power supply, the power pads belonging to the VDD2 power supply type in the multiple pad arrays are divided into VDD2 power supply test pads and VDD2 power supply pad sets; wherein, all power pads in the VDD2 power supply pad set are electrically connected to form a VDD2 power supply network, and the VDD2 power supply test pads are independent of the VDD2 power supply network, and the VDD2 power supply test pads are used to perform noise testing on the VDD2 power supply inside the chip under test;

[0082] In another specific embodiment, for VDDQ power supplies, the power pads belonging to the VDDQ power type in the multiple pad arrays are divided into VDDQ power test pads and a set of VDDQ power pads; wherein, all the power pads in the set of VDDQ power pads are electrically connected to form a VDDQ power network, and the VDDQ power test pads are independent of the VDDQ power network, and the VDDQ power test pads are used to perform noise testing on the VDDQ power supply inside the chip under test.

[0083] It should be noted that if the packaging substrate 40 has multiple power types, then for each power type, these power pads can be divided into corresponding test pads and power pad sets, and the power pins in the chip under test can also be divided into corresponding test pins and power pin sets. Then, all the power pads in the power pad set are electrically connected together by copper pouring, so that all power pins except the test pins are electrically connected together. At this time, by leading the test pins out to the outside of the chip under test, not only can the power noise of the power type in the chip under test be tested, but the accuracy of the power noise test can also be improved.

[0084] It should also be noted that, in this embodiment of the disclosure, the test pads of the VDD1 power supply are independent of the VDD1 power network, the test pads of the VDD2 power supply are independent of the VDD2 power network, and the test pads of the VDDQ power supply are independent of the VDDQ power network; moreover, the VDD1 power network, the VDD2 power network, and the VDDQ power network are also independent of each other.

[0085] It should also be noted that, in this embodiment of the disclosure, taking the VDDQ power supply as an example, if the test pad is named VDDQ1, then the corresponding test pin on the chip under test can also be named VDDQ1, so as to better realize the electrical connection between the test pin and the test pad on the package substrate.

[0086] This disclosure provides a packaging substrate comprising multiple pad arrays, each pad array including at least a power pad. Power pads belonging to the same power type within the multiple pad arrays are divided into test pads and a power pad set. The power pad set includes all power pads of the same power type except for the test pads, and all power pads in the power pad set are electrically connected together. The test pads are used to perform noise testing on the internal power supply of the same power type in the chip under test. Thus, although all power pads in the power pad set are electrically connected together, the test pads are not electrically connected to them. By using the independent test pads to perform noise testing on the internal power supply of the chip under test, the internal power supply noise of the chip can be accurately measured, thereby improving the accuracy of power supply noise testing.

[0087] In another embodiment of this disclosure, see Figure 7 This illustration shows a schematic diagram of the composition of a power supply noise testing device 80 provided in an embodiment of this disclosure. Figure 7 As shown, the power supply noise testing device 80 may include a packaging substrate 801, a chip under test 802, and a test board 803; wherein:

[0088] Test board 803 is equipped with a first test point a corresponding to the first power type;

[0089] The chip under test 802 includes at least a power supply pin corresponding to a first power supply type, and the power supply pin is divided into a first test pin and a first power supply pin set other than the first test pin.

[0090] The packaging substrate 801 may include at least a power pad corresponding to a first power type, and the power pad is divided into a first test pad and a set of first power pads excluding the first test pad.

[0091] In this configuration, the power pins in the first power pin set are electrically connected to the power pads in the first power pad set, the first test pin is electrically connected to the first test pad, and the first test pad is also electrically connected to the first test point, so that the first test point can perform noise testing on the internal power supply corresponding to the first power type in the chip under test through the first test pad and the first test pin.

[0092] It should be noted that, in this embodiment, the packaging substrate 801 can be the packaging substrate 40 provided in the foregoing embodiments. Additionally, the test board 803 can be a signal test board or a system motherboard; no limitations are imposed here.

[0093] It should also be noted that, in this embodiment of the present disclosure, in order to facilitate power supply noise testing outside the chip, test points can be set on the test board 803. Here, taking the first power type as an example, a corresponding first test point can be set on the test board 803, and then the power signal to be tested can be led out through the first test point, so that internal power supply noise testing can be performed outside the chip under test 802, and the accuracy of power supply noise testing is high.

[0094] Understandably, in this embodiment of the disclosure, since there may be multiple power types corresponding to the chip under test 802, and the first power type is only one of them; there may also be multiple test points on the test board 803, and the number of test points is related to the number of power types; in other words, different power types are provided with different test points on the test board 803.

[0095] In some embodiments, the first power type can be any one of VDD1 power type, VDD2 power type and VDDQ power type; wherein, on the test board 803, different first test points are set for different first power types.

[0096] Specifically, the test board 803 can be configured with VDD1 test points corresponding to VDD1 power type, VDD2 test points corresponding to VDD2 power type, and VDDQ test points corresponding to VDDQ power type. The VDD1 test point can be used to perform noise testing on the VDD1 power supply inside the chip under test 802, the VDD2 test point can be used to perform noise testing on the VDD2 power supply inside the chip under test 802, and the VDDQ test point can be used to perform noise testing on the VDDQ power supply inside the chip under test 802.

[0097] In some embodiments, in the power supply noise testing apparatus 80, the chip under test 802, the packaging substrate 801, and the test board 803 are stacked in sequence.

[0098] It should be noted that, for details please refer to [link / reference]. Figure 7 The chip under test 802 is placed above the packaging substrate 801, and the test board 803 is placed below the packaging substrate 801, thus forming a stacked structure. This stacked structure not only saves layout space, but also has a good overall aesthetics.

[0099] In some embodiments, see Figure 8The test board 803 may also be provided with multiple solder joint arrays (such as solder joint array 831, solder joint array 832, solder joint array 833 and solder joint array 834) corresponding to multiple solder pad arrays in the packaging substrate 801, and each solder joint array includes at least a power solder joint; wherein:

[0100] In the array of multiple solder joints, the power solder joints belonging to the first power type are divided into a first test solder joint b and a first power solder joint set. The power solder joints in the first power solder joint set are electrically connected to the power pads in the first power pad set, and all the power solder joints in the first power solder joint set are electrically connected together to form a first power network. Among them, the first test solder joint a is independent of the first power network.

[0101] It should be noted that, in the embodiments disclosed herein, please refer to the specific details. Figure 8 The test board 803 may include solder joint arrays 831, 832, 833, and 834. These four solder joint arrays can be arranged in a left-right symmetrical structure along the X-axis or a top-bottom symmetrical structure along the Y-axis.

[0102] It should also be noted that, in this embodiment of the present disclosure, there is a correspondence between the four solder point arrays in the test board 803 and the four pad arrays in the packaging substrate 801, and each solder point is electrically connected to the corresponding pad. Thus, taking the first power type as an example, not only do the power pads in the packaging substrate 801 need to be divided to create a separate power pad as the first test pad, and then all the other power pads are connected to form the first power network; correspondingly, the power pins in the chip under test 802 also need to be divided to create a separate power pin as the first test pin, and then the other power pins are electrically connected to the corresponding power pads, so that all power pins except the first test pin are also electrically connected to the first power network, but the first test pin is not connected to the first power network; correspondingly, the power solder joints in the test board 803 also need to be divided in the same way, with a separate power solder joint as the first test solder joint, and then the first test pin is electrically connected to the first test point in sequence through the first test pad, the first test solder joint, and the first test point, so that noise testing of the internal power supply corresponding to the first power type in the chip under test can be performed outside the chip under test 802 through the first test point.

[0103] Furthermore, in some embodiments, the test board 803 is also provided with a first metal trace; wherein, the first test pad is connected to the first test solder joint, and the first test solder joint is electrically connected to the first test point through the first metal trace, so as to realize the electrical connection between the first test pad and the first test point.

[0104] It should be noted that, in the embodiments disclosed herein, please refer to the specific details. Figure 7The bold solid line on test board 803 indicates the first metal trace. From Figure 7 As can be clearly seen, the first test pin is electrically connected to the first test solder joint through the first test pad in the packaging substrate 801. Then, on the test board 803, the first test solder joint is electrically connected to the first test point a through a metal trace, so as to realize the electrical connection between the first test pin and the first test point. This allows the power signal to be tested to be led out to the outside of the chip under test 802 for convenient power noise testing.

[0105] Furthermore, in some embodiments, see Figure 8 The test board 803 may also be provided with a first resistor identifier R1, and the first resistor identifier R1 includes a first solder joint and a second solder joint; wherein, the first solder joint is connected to the first test solder joint, and the second solder joint is connected to the first power network.

[0106] In one specific implementation, in test mode, the first resistor is not soldered at the first resistor mark R1 so that the first test solder joint is disconnected from the first power network; in operating mode, the first resistor is soldered at the first resistor mark R1 so that the first test solder joint is electrically connected to the first power network.

[0107] It should be noted that, in this embodiment, taking the first power type as an example, the test board 803 is provided with a first resistor identifier R1 corresponding to the first power type. This first resistor identifier R1 is used to separate the first test solder joint from the first power network. Specifically, in test mode, the first test solder joint needs to be independent of the first power network; in this case, the first resistor is not soldered at the first resistor identifier R1, so that the first test solder joint is disconnected from the first power network. In normal system operation mode, i.e., working mode, the first test solder joint also needs power; in this case, the first resistor needs to be soldered at the first resistor identifier R1, so that the first test solder joint is electrically connected to the first power network. Thus, by whether or not the first resistor is soldered at the first resistor identifier R1, the connection or disconnection between the first test solder joint and the first power network can be achieved.

[0108] It should also be noted that, in this embodiment, the resistance of the first resistor can be 0 ohms. This avoids energy loss through the first resistor when using a 0-ohm first resistor to establish the electrical connection between the first test solder joint and the first power network.

[0109] Furthermore, in some embodiments, the first power supply type is any one of VDD1, VDD2, and VDDQ power supply types; wherein, on the test board 803, different first test points and different first resistor labels are set for different first power supply types.

[0110] In this embodiment of the disclosure, since the chip under test 802 can have multiple power supply types, and the first power supply type is only one of them; therefore, there can also be multiple resistor labels that can be set on the test board 803, and the number of resistor labels is related to the number of power supply types; in other words, different power supply types can also be correspondingly set with different resistor labels on the test board 803.

[0111] For example, taking the VDDQ power type as an example, although the VDDQ test pads in the package substrate 801 and the corresponding VDDQ test pins in the chip under test 802 are isolated, and the other VDDQ power pins are connected together to form a VDDQ power network, and the VDDQ test pins are not connected to the VDDQ power network; however, when the test board 803 is powered, it is still necessary to power the isolated VDDQ test pins and the VDDQ power network together. Theoretically, there are many VDDQ power pins in the chip under test 802, and the absence of one pin does not affect normal operation; however, when no test is being performed, the VDDQ test pin is in an idle state and can be powered by the first resistor; when testing is being performed, it is no longer powered, and the VDDQ test pin is only used for noise testing of the VDDQ power supply in the chip under test 802.

[0112] In other words, in this embodiment, if a 0-ohm resistor is soldered at the first resistor mark R1, then the VDDQ test pin can be powered in the same way as the VDDQ power network. If the 0-ohm resistor is not soldered at the first resistor mark R1, then it is equivalent to no longer powering the VDDQ test pin. In this case, only the other VDDQ power pins in the chip under test 802 are connected together, and the power signal to be tested can be led out through the VDDQ test pin and the test point on the test board 803. Thus, when the power noise test device 80 is in test mode, based on the independent VDDQ test pin, accurate internal power noise test results can be directly measured outside the chip under test 802. For example, Figure 9 A schematic diagram illustrating test results for internal power supply noise provided in an embodiment of this disclosure is shown. For example... Figure 9 As shown, the test result was obtained externally to the chip under test 802, specifically at the first test point. In other words, by assembling the test platform according to the embodiments of this disclosure and then testing the internal power supply of the chip through the first test point, the power supply noise of the chip's internal die can be tested more accurately.

[0113] This disclosure provides a power supply noise testing apparatus, which relates to semiconductor memory technology, particularly to the testing and verification of SDRAM. Specifically, it utilizes a special packaging design to achieve more accurate power supply measurements of the chip under test (DUT). The packaging substrate has a first test pad independent of a first power network, and the DUT has a corresponding first test pin independent of the first power network. The packaging substrate and the DUT are then packaged to form a semiconductor structure, which is then placed on a test board. Thus, the first test pin, independent of the first power network, is electrically connected to a first test point on the test board via the first test pad. This allows for testing of the internal power supply noise of the DUT within the semiconductor structure through the external first test point, thereby improving the accuracy of power supply noise testing.

[0114] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 10 This illustration shows a flowchart of a power supply noise testing method provided by an embodiment of this disclosure. Figure 10 As shown, the method may include:

[0115] S1001: In test mode, noise test is performed on the internal power supply corresponding to the first power type in the chip under test through the first test point on the test board; wherein, the first test point corresponds to the first power type, and the first power type is any one of VDD1 power type, VDD2 power type and VDDQ power type.

[0116] It should be noted that, in this embodiment of the disclosure, the method is applied to the power supply noise testing device described in the foregoing embodiments, which can be regarded as a method for testing the noise of the internal power supply in an SDRAM chip.

[0117] It should also be noted that the power supply noise testing device here may include a test board, a packaging substrate, and a chip under test; and the chip under test, the packaging substrate, and the test board are stacked sequentially. In a specific embodiment, the test board is further provided with multiple solder joint arrays corresponding to multiple pad arrays in the packaging substrate, and each solder joint array includes at least a power solder joint; wherein, the power solder joints belonging to the first power type in the multiple solder joint arrays are divided into a first test solder joint and a first power solder joint set, the power solder joints in the first power solder joint set are electrically connected to the power pads in the first power pad set, and all the power solder joints in the first power solder joint set are electrically connected together to form a first power network; wherein, the first test solder joint is independent of the first power network.

[0118] In this embodiment, there is a correspondence between the multiple solder joint arrays in the test board and the multiple pad arrays in the packaging substrate, with each solder joint electrically connected to its corresponding pad. Thus, taking the first power type as an example, not only do the power pads in the packaging substrate need to be divided to designate one independent power pad as the first test pad, and then all other power pads are connected to form the first power network, correspondingly, the power pins in the chip under test also need to be divided, with one independent power pin as the first test pin, and then other power pins electrically connected to their corresponding power pads, so that all power pins except the first test pin are also electrically connected to the first power network, but the first test pin is not connected to the first power network. Correspondingly, the power solder joints in the test board also need to be divided in the same way, with one independent power solder joint as the first test solder joint, and then the first test pin sequentially passes through the first test pad, the first test solder joint, and is electrically connected to the first test point, so that noise testing of the internal power supply corresponding to the first power type in the chip under test can be performed externally through the first test point.

[0119] Furthermore, in some embodiments, the test board is also provided with a first resistor mark, and the method may further include: in the working mode, determining that a first resistor is soldered at the first resistor mark, and controlling the first test solder joint to be electrically connected to the first power network through the first resistor.

[0120] Furthermore, in some embodiments, the method may further include: in test mode, determining that the first resistor is not soldered at the first resistor mark, so that the first test solder joint is disconnected from the first power network.

[0121] In this embodiment of the disclosure, the resistance value of the first resistor can be 0 ohms.

[0122] In this embodiment of the disclosure, since the power supply type corresponding to the chip under test can be multiple (e.g., VDD1 power supply type, VDD2 power supply type, and VDDQ power supply type, etc.), and the first power supply type is only one of them; therefore, there can also be multiple resistor labels that can be set on the test board, and the number of resistor labels is related to the number of power supply types; in other words, different power supply types can also be set with different resistor labels on the test board.

[0123] For example, taking a first power type as an example, the test board is provided with a first resistor label corresponding to the first power type. This first resistor label is used to separate the first test solder joint from the first power network. In test mode, the first test solder joint needs to be independent of the first power network; in this case, the first resistor is not soldered at the first resistor label, thus disconnecting the first test solder joint from the first power network. In normal system operation mode, the first test solder joint also needs power; in this case, the first resistor is soldered at the first resistor label, thus electrically connecting the first test solder joint to the first power network. In this way, by whether or not the first resistor is soldered at the first resistor label, the connection or disconnection between the first test solder joint and the first power network can be achieved. This allows for accurate internal power noise test results to be directly measured externally from the chip under test when in test mode.

[0124] This disclosure provides a power supply noise testing method, specifically a method for accurately measuring the internal power supply noise of a chip by modifying the design of the packaging substrate. On one hand, the network distribution of the power supply pins is modified in the packaging substrate design; on the other hand, corresponding test points are added to the test board (e.g., a system motherboard). In test mode, the 0-ohm first resistor is disconnected, and then the internal power supply noise is measured according to the corresponding power supply test points. Thus, according to the technical solution provided in the foregoing embodiment, the accurate internal power supply noise of the chip can be directly measured using the corresponding test points in test mode, thereby improving the accuracy of power supply noise testing.

[0125] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0126] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0127] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0128] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0129] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0130] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0131] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A packaging substrate, characterized in that, The packaging substrate includes multiple pad arrays, and each pad array includes at least a power pad; wherein: The power pads belonging to the same power type in the multiple pad arrays are divided into test pads and a power pad set; wherein, the power pad set includes other power pads belonging to the same power type except for the test pads, and all power pads in the power pad set are electrically connected together; the test pads are used to perform noise testing on the internal power supply corresponding to the same power type in the chip under test.

2. The packaging substrate according to claim 1, characterized in that, The packaging substrate includes four pad arrays; wherein the four pad arrays are symmetrical vertically and horizontally.

3. The packaging substrate according to claim 1, characterized in that, The packaging substrate further includes a conductive layer; wherein, in the conductive layer, the power pads in the power pad set are electrically connected by copper pouring to form a first power network, and the test pads are independent of the first power network.

4. The packaging substrate according to claim 1, characterized in that, The surface of the packaging substrate is provided with gold fingers; wherein, in the same power type, the distance between the test pad and the gold fingers is less than the distance between the power pads and the gold fingers in the power pad set.

5. The packaging substrate according to claim 4, characterized in that, The surface of the packaging substrate is further provided with the chip under test (DUT), and the DUT includes multiple pin arrays, each pin array including at least a power supply pin; wherein: The power pins belonging to the same power type in the multiple pin arrays are divided into test pins and power pin sets; wherein, the power pins in the power pin set are electrically connected to the power pads in the power pad set, and the test pins are electrically connected to the test pads, so that the test pads can perform noise testing on the internal power supply of the same power type in the chip under test through the test pins.

6. The packaging substrate according to claim 5, characterized in that, The packaging substrate is further provided with metal vias and metal traces; wherein, the test pad is electrically connected to the gold finger through the metal traces and the metal vias, and the gold finger and the test pin are electrically connected by wire bonding, so as to realize that the test pad and the test pin are electrically connected together.

7. The packaging substrate according to claim 1, characterized in that, Each pad array includes at least VDD1 power pad, VDD2 power pad, and VDDQ power pad; The same power type can be any one of VDD1, VDD2, and VDDQ power types.

8. The packaging substrate according to claim 7, characterized in that, The power pads belonging to the VDD1 power type in the multiple pad arrays are divided into VDD1 power test pads and VDD1 power pad sets; wherein, all the power pads in the VDD1 power pad set are electrically connected to form a VDD1 power network, and the VDD1 power test pads are independent of the VDD1 power network, and the VDD1 power test pads are used to perform noise testing on the VDD1 power inside the chip under test; The power pads belonging to the VDD2 power type in the multiple pad arrays are divided into VDD2 power test pads and VDD2 power pad sets; wherein, all the power pads in the VDD2 power pad set are electrically connected to form a VDD2 power network, and the VDD2 power test pads are independent of the VDD2 power network, and the VDD2 power test pads are used to perform noise testing on the VDD2 power inside the chip under test; The power pads belonging to the VDDQ power type in the multiple pad arrays are divided into VDDQ power test pads and a set of VDDQ power pads. The power pads in the set of VDDQ power pads are all electrically connected to form a VDDQ power network, and the VDDQ power test pads are independent of the VDDQ power network. The VDDQ power test pads are used to perform noise testing on the VDDQ power supply inside the chip under test.

9. A power supply noise testing device, characterized in that, The power supply noise testing device includes a packaging substrate, a chip under test, and a test board as described in any one of claims 1 to 8; wherein: The test board is equipped with a first test point corresponding to the first power type. The chip under test includes at least a power pin corresponding to the first power type, and the power pin is divided into a first test pin and a first power pin set other than the first test pin. The packaging substrate includes at least a power pad corresponding to the first power type, and the power pad is divided into a first test pad and a first power pad set other than the first test pad. Wherein, the power pins in the first power pin set are electrically connected to the power pads in the first power pad set, the first test pin is electrically connected to the first test pad, and the first test pad is also electrically connected to the first test point, so that the first test point can perform noise testing on the internal power supply corresponding to the first power type in the chip under test through the first test pad and the first test pin.

10. The power supply noise testing device according to claim 9, characterized in that, The chip under test, the packaging substrate, and the test board are stacked in sequence.

11. The power supply noise testing device according to claim 9, characterized in that, The test board also has multiple solder joint arrays corresponding to multiple pad arrays in the packaging substrate, and each solder joint array includes at least one power solder joint; wherein: The power solder joints belonging to the first power type in the plurality of solder joint arrays are divided into a first test solder joint and a first power solder joint set. The power solder joints in the first power solder joint set are electrically connected to the power pads in the first power pad set, and all the power solder joints in the first power solder joint set are electrically connected together to form a first power network. The first test solder joint is independent of the first power network.

12. The power supply noise testing device according to claim 11, characterized in that, The test board is further provided with a first metal trace; wherein the first test pad is connected to the first test solder point, and the first test solder point is electrically connected to the first test point through the first metal trace, so as to realize the electrical connection between the first test pad and the first test point.

13. The power supply noise testing device according to claim 11, characterized in that, The test board is also provided with a first resistor mark, and the first resistor mark includes a first solder joint and a second solder joint; The first solder joint is connected to the first test solder joint, and the second solder joint is connected to the first power network.

14. The power supply noise testing device according to claim 13, characterized in that, In test mode, the first resistor is not soldered at the first resistor mark so that the first test solder joint is disconnected from the first power network. In the operating mode, a first resistor is soldered at the first resistor mark so that the first test solder joint is electrically connected to the first power network.

15. The power supply noise testing device according to claim 14, characterized in that, The resistance of the first resistor is 0 ohms.

16. The power supply noise testing device according to claim 13, characterized in that, The first power type is any one of VDD1 power type, VDD2 power type and VDDQ power type; On the test board, different first power supply types are provided with different first test points and different first resistor markings.

17. A power supply noise testing method, characterized in that, The method, applied to the power supply noise testing apparatus of claim 9, comprises: In test mode, noise test is performed on the internal power supply corresponding to the first power type in the chip under test through the first test point on the test board. The first test point corresponds to the first power type, and the first power type is any one of VDD1 power type, VDD2 power type and VDDQ power type.

18. The method according to claim 17, characterized in that, The test board also has multiple solder joint arrays corresponding to multiple pad arrays in the packaging substrate, and each solder joint array includes at least one power solder joint; wherein: The power solder joints belonging to the first power type in the plurality of solder joint arrays are divided into a first test solder joint and a first power solder joint set. The power solder joints in the first power solder joint set are electrically connected to the power pads in the first power pad set, and all the power solder joints in the first power solder joint set are electrically connected together to form a first power network. The first test solder joint is independent of the first power network.

19. The method according to claim 18, characterized in that, The test board is also equipped with a first resistance indicator, and the method further includes: In the working mode, the first resistor is soldered at the first resistor mark, and the first resistor controls the first test solder joint to be electrically connected to the first power network.

20. The method according to claim 19, characterized in that, The method further includes: In test mode, it is determined that the first resistor is not soldered at the first resistor mark, so that the first test solder joint is disconnected from the first power network.

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