Method for inspecting semiconductor element layout and layout change

Abstract

A layout of a semiconductor element and a method for checking layout change are disclosed. The layout of the semiconductor element includes at least one semiconductor layer and a dummy layer. Each semiconductor layer has a layout pattern. The dummy layer has a dummy pattern. A checking circuit calculates a Boolean operation value between the layout pattern and the dummy pattern, and compares the Boolean operation value between the layout pattern and the dummy pattern with an original preset value to determine whether the layout pattern is changed.

Description

Technical Field

[0001] This invention relates to a semiconductor device layout, and more particularly to a semiconductor device layout having a dummy pattern for determining whether the layout pattern has been changed. Background Technology

[0002] The semiconductor process for forming integrated circuits requires a set of steps, including deposition and patterning of material layers such as isolation layers, polysilicon layers, and metal layers. However, when the pattern of any semiconductor layer changes, the integrated circuit will malfunction. Summary of the Invention

[0003] An embodiment of the present invention provides a semiconductor device layout, including a semiconductor layer and a dummy layer. The semiconductor layer has a layout pattern. The dummy layer has a dummy pattern. A checking circuit calculates the layout pattern and the dummy pattern to generate a calculated value, and compares the calculated value with a preset value to determine whether the layout pattern has been changed.

[0004] In another embodiment, the present invention further includes a method for detecting changes in the layout of semiconductor components, comprising: forming a layout pattern in a semiconductor layer; forming a dummy pattern in a dummy layer; using a Boolean operation to calculate the layout pattern and the dummy pattern to generate a calculated value; and comparing the calculated value with a preset value. When the calculated value differs from the preset value, it indicates that the layout pattern has been changed.

[0005] The semiconductor element layout change inspection method of the present invention can be implemented via a layout inspection circuit, which is hardware or firmware capable of performing specific functions, or it can be implemented by incorporating code into a recording medium and combined with specific hardware. When the code is loaded and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine becomes the inspection circuit for implementing the present invention. Attached Figure Description

[0006] Figures 1A to 1D This is a schematic diagram of the semiconductor element layout of the present invention.

[0007] Figure 2A and Figure 2B This is a schematic diagram showing the overlap of the layout pattern and the dummy pattern of the present invention.

[0008] Figure 3A and Figure 3B This is a schematic diagram showing the overlap between the layout pattern of the present invention and another dummy pattern.

[0009] Figure 4A and Figure 4B This is a schematic diagram showing the overlap of the layout pattern and the dummy pattern of the present invention.

[0010] Figure 5A and Figure 5B This is a schematic diagram showing the overlap between the layout pattern of the present invention and another dummy pattern.

[0011] Figure 6A and Figure 6B This is a schematic diagram showing the overlap of the layout pattern and the dummy pattern of the present invention.

[0012] Figure 7A and Figure 7B This is a schematic diagram showing the overlap between the layout pattern of the present invention and another dummy pattern.

[0013] Figure 8A and Figure 8B This is a schematic diagram showing the overlap between the layout pattern of the present invention and two other dummy patterns.

[0014] Figure 9 This is a schematic diagram showing other overlaps between the layout pattern and the dummy pattern.

[0015] Figure 10 This is a schematic diagram of the layout change inspection method of the present invention.

[0016] Icon labels:

[0017] 100A, 100B, 100C, 100D: Semiconductor Component Layout

[0018] 105, 110, 115: Semiconductor layer

[0019] 106, 111, 116, B: Layout pattern

[0020] 120, 125: Virtual layers

[0021] 130: Check the circuit

[0022] SDI, SDI2, SDI_2, SDI2_2, 810, 820, A: Dummy Pattern

[0023] FL1, FL2: Electronic files

[0024] CT1~CT3: Contact ends

[0025] 210~230, 310~330, 410, 420, 510, 520, 710, 720: Patterns

[0026] UR, CR: Region

[0027] S101~S106: Steps Detailed Implementation

[0028] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below in conjunction with the accompanying drawings for detailed description. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The arrangement of elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the accompanying drawings is for simplification and does not imply any correlation between different embodiments.

[0029] Figure 1A This is a schematic diagram of the semiconductor device layout of the present invention. The semiconductor device layout 100A includes a semiconductor layer 110 and a dummy layer 120. The semiconductor layer 110 has a layout pattern 111. In this embodiment, the layout pattern 111 includes three contacts, but this is not intended to limit the invention. The present invention does not limit the type of semiconductor layer 110. In some embodiments, the semiconductor layer 110 is a semiconductor layer with a well, a semiconductor layer with an oxide diffusion region, a semiconductor layer with a polysilicon region, a semiconductor layer with a via, or a semiconductor layer with metal. In this example, the layout pattern 111 may be an N-type well, a P-type well, an oxide diffusion region, a polysilicon region, a via, or metal.

[0030] The dummy layer 120 has a dummy pattern SDI2. In this embodiment, the dummy pattern SDI2 is composed of multiple line segments. In this example, each line segment is arranged parallel to each other and regularly disposed within the dummy layer 120. In other embodiments, the dummy pattern SDI2 is a similar two-dimensional barcode (QR code), but this is not intended to limit the invention. The invention does not limit the shape of the dummy pattern SDI2. (Further details will follow.) Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A and Figure 7A The shape of the dummy pattern SDI2 is described. In other embodiments, the dummy layer 120 further includes a dummy pattern SDI. The dummy pattern SDI is a rectangular line segment that surrounds the dummy pattern SDI2.

[0031] In one possible embodiment, a check circuit 130 calculates the layout pattern 111 and the dummy pattern SDI2 to generate a calculated value. In one possible embodiment, this calculated value is a pattern density value. In this example, the pattern density value is related to the area of ​​the overlapping region of the layout pattern 111 and the dummy pattern SDI2. The check circuit 130 compares the calculated value with a preset value to determine whether the layout pattern 111 has been changed. This change means that the layout pattern 111 has been displaced, its shape has changed, or its area has increased or decreased. When the calculated value equals the preset value, it indicates that the layout pattern 111 has not been changed. However, when the calculated value does not equal the preset value, it indicates that the layout pattern 111 has been changed. In one possible embodiment, the check circuit 130 highlights and records the layout pattern 111.

[0032] After testing all semiconductor layers, the inspection circuit 130 provides a test report. Based on this report, the tester can determine whether the layout pattern 111 of semiconductor layer 110 has been altered. This test report may be a design rule check (DRC) report.

[0033] In this embodiment, the inspection circuit 130 receives electronic files FL1 and FL2. Electronic file FL1 describes the characteristics of the layout pattern 111, such as its position and size. Electronic file FL2 describes the characteristics of the dummy pattern SDI2, such as its position and size. In one possible embodiment, electronic files FL1 and FL2 may be two-dimensional vector graphics files.

[0034] In some embodiments, the semiconductor element 100A and the detection circuit 130 constitute a test system. The detection circuit 130 is used to check whether the layout pattern of the semiconductor element 100A has changed. When the semiconductor element 100A has multiple semiconductor layers, the detection circuit 130 compares the layout pattern corresponding to each semiconductor layer with at least one dummy pattern to generate multiple comparison results. The detection circuit 130 compares each comparison result with a corresponding preset value to determine whether the layout pattern has changed. This change refers to the occurrence of displacement, increase, or decrease in the layout pattern.

[0035] Figure 1B This is a schematic diagram of the semiconductor element layout of the present invention. Figure 1B resemblance Figure 1A The difference is that, Figure 1B The semiconductor element 100B has an additional semiconductor layer 115. The present invention does not limit the number of semiconductor layers. In other embodiments, the semiconductor element 100B has even more semiconductor layers.

[0036] Semiconductor layer 115 has a layout pattern 116. In one possible embodiment, layout pattern 116 is a pattern of an N-type well. In this example, semiconductor layers 110 and 115 are integrated in the same device layout. Electronic file FL1 describes the physical characteristics of layout patterns 111 and 116.

[0037] In this embodiment, the inspection circuit 130 calculates the layout pattern 111 and the dummy pattern SDI2 to generate a first calculated value, and compares the first calculated value with a first preset value. Based on the comparison result of the first calculated value and the first preset value, the inspection circuit 130 determines whether the layout pattern 111 has been changed. In this example, the inspection circuit 130 also calculates the layout pattern 116 and the dummy pattern SDI2 to generate a second calculated value, and compares the second calculated value with a second preset value. Based on the comparison result of the second calculated value and the second preset value, the inspection circuit 130 determines whether the layout pattern 116 has been changed.

[0038] Figure 1C This is a schematic diagram of the semiconductor element layout of the present invention. Figure 1C resemblance Figure 1A The difference is that, Figure 1C The inspection circuit 130 also calculates the layout pattern 106 and the dummy pattern SDI2 to generate a second calculated value. In one possible embodiment, the layout pattern 106 is a previous or next version of the layout pattern 111. In this example, the inspection circuit 130 determines the difference between the layout patterns 106 and 111 based on the first and second calculated values. For example, if the first calculated value is different from the second calculated value, it indicates that there is a difference between the layout patterns 106 and 111. The inspection circuit 130 records and marks this difference. In this example, semiconductor layers 105 and 110 are not integrated in the same semiconductor element layout. If the first calculated value is the same as the second calculated value, it indicates that the layout pattern 106 is completely identical to the layout pattern 111.

[0039] Figure 1D This is another schematic diagram of the semiconductor element layout of the present invention. Figure 1D resemblance Figure 1A The difference is that, Figure 1D An additional dummy layer 125 is added. The present invention does not limit the number of dummy layers. In other embodiments, the semiconductor device layout has even more dummy layers.

[0040] The dummy layer 125 has a dummy pattern SDI2_2. The dummy pattern SDI2_2 is composed of multiple line segments. In this example, each line segment is arranged parallel to each other and regularly positioned within the dummy layer 125. In this embodiment, the shape of the dummy pattern SDI2_2 of the dummy layer 125 differs from the shape of the dummy pattern SDI2 of the dummy layer 120. In some embodiments, the shape of the dummy pattern SDI2 may be similar to that of the dummy pattern SDI2_2, such as both being diagonal lines from the upper left to the lower right, but the width of the line segments in the dummy pattern SDI2 differs from the width of the dummy pattern SDI2_2.

[0041] In other embodiments, dummy layer 125 further includes a dummy pattern SDI_2. Dummy pattern SDI_2 is a rectangular line segment that surrounds dummy pattern SDI2_2. In this example, the dummy pattern SDI_2 of dummy layer 125 is similar to the dummy pattern SDI of dummy layer 120.

[0042] In one possible embodiment, the checking circuit 130 calculates the layout pattern 111 and the dummy pattern SDI2 to generate a first calculated value, and compares the first calculated value with a first preset value. When the first calculated value equals the first preset value, the checking circuit 130 then calculates the layout pattern 111 and the dummy pattern SDI2_2 to generate a second calculated value, and compares the second calculated value with a second preset value. When the second calculated value does not equal the second preset value, it indicates that the layout pattern 111 has been changed.

[0043] Figure 2A and Figure 2B This is a schematic diagram showing the overlap between layout pattern 111 and dummy pattern SDI2. Layout pattern 111 includes contact terminals CT1 to CT3. Dummy pattern SDI2 includes patterns 210 to 230. In one possible embodiment, the checking circuit 130 determines whether the contact terminals CT1 to CT3 have been altered, such as displacement of any one of the contact terminals CT1 to CT3 or a change in the size of any one of the contact terminals CT1 to CT3, based on the overlap area between the contact terminals CT1 to CT3 and the patterns 210 to 230.

[0044] For example, in Figure 2A In this example, the detection circuit 130 calculates the overlapping area (or first area) of contact end CT1 and pattern 210, the overlapping area (or second area) of contact end CT2 and pattern 220, and the overlapping area (or third area) of contact end CT3 and pattern 230. In this case, the detection circuit 130 sums the first to third areas to generate a first calculation result (or calculated value). The detection circuit 130 then determines whether the first calculation result equals a preset value. Figure 2A Since the layout pattern 111 has not been changed, the first calculation result is equal to the preset value.

[0045] However, in Figure 2B In this case, the layout pattern 111 is shifted. For example, the contact end CT2 shifts to the right. In this example, the overlap area between the contact end CT2 and the pattern 220 is less than... Figure 2A The overlap area between the middle contact terminal CT2 and pattern 220. Therefore, the calculated value generated by the inspection circuit 130 is not equal to the preset value.

[0046] In other embodiments, the detection circuit 130 may compare the overlapping area (or first area) of contact end CT1 with pattern 210, the overlapping area (or second area) of contact end CT2 with pattern 220, and the overlapping area (or third area) of contact end CT3 with pattern 230 with a first value, a second value, and a third value, respectively, to determine whether contact ends CT1 to CT3 have shifted. For example, when the second area is not equal to the second value, it indicates that contact end CT2 has shifted or that the size of contact end CT2 has changed. Therefore, the inspection circuit 130 marks contact end CT2 in the inspection report.

[0047] Figure 3A and Figure 3B This is a schematic diagram showing the overlap between layout pattern 111 and dummy pattern SDI2. Figure 3A Similar to Figure 2A The difference lies in the shape of the dummy pattern SDI2. Figure 2A In the diagram, the dummy pattern SDI2 is depicted as a diagonal line running from the upper left to the lower right. Figure 3A and Figure 3B In the middle, the dummy pattern SDI2 is a diagonal line from the lower left to the upper right.

[0048] Figure 4A and Figure 4B This is another schematic diagram showing the overlap between layout pattern 111 and dummy pattern SDI2. Figure 4A and Figure 2A The difference lies in the shape of the dummy pattern SDI2. In this embodiment, the dummy pattern SDI2 includes patterns 410 and 420. The shape of pattern 410 is different from that of pattern 420. Pattern 420 is composed of multiple triangular patterns.

[0049] Figure 5A and Figure 5B This is another schematic diagram showing the overlap between layout pattern 111 and dummy pattern SDI2. Figure 5A Similar to Figure 4A The difference is that, Figure 5A The hypotenuse of the triangle in pattern 520 faces to the left, while Figure 4A The hypotenuse of the triangle in pattern 420 faces to the right.

[0050] Figure 6A and Figure 6B This is another schematic diagram showing the overlap between layout pattern 111 and dummy pattern SDI2. In this embodiment, dummy pattern SDI2 is composed of multiple rectangles. The area of ​​one of the multiple rectangles is different from the area of ​​the others.

[0051] Figure 7A and Figure 7B This is another overlapping schematic diagram of layout pattern 111 and dummy pattern SDI2. Dummy pattern SDI2 includes patterns 710 and 720. Pattern 710 is a rectangle that surrounds pattern 720. In this embodiment, pattern 720 is composed of multiple patterns that are irregularly arranged. The multiple patterns include multiple triangles and trapezoids.

[0052] Figure 8A and Figure 8B This is a schematic diagram showing the overlap of layout pattern 111 and two dummy patterns. In this embodiment, dummy pattern 810 is similar to... Figure 6A The dummy pattern SDI2, while the dummy pattern 820 is similar to Figure 7A The dummy pattern SDI2. Dummy patterns 810 and 820 are located in different dummy layers. In this example, the dummy layer containing dummy pattern 810 is located below the dummy layer containing dummy pattern 820. In other embodiments, the semiconductor layer containing layout pattern 111 may be located between the dummy layers containing dummy pattern 810 and dummy pattern 820.

[0053] Figure 9 This is a schematic diagram illustrating other overlaps between the layout pattern and the dummy pattern. For ease of explanation, Figure 9 Only a single layout pattern B and a single dummy pattern A are displayed. The present invention does not limit the shapes of the dummy pattern A and the layout pattern B. In this embodiment, the dummy pattern A is rectangular, and the layout pattern B is circular. In this example, the layout pattern B has regions UR and CR. Region UR does not overlap with dummy pattern A. Region CR overlaps with dummy pattern A.

[0054] In one possible embodiment, the inspection circuit 130 uses a Boolean operation OP1 to calculate the dummy pattern A and the layout pattern B to generate a first calculated value. In this example, the inspection circuit 130 calculates an area difference between the dummy pattern A and the region CR, and uses the area difference as a first calculated value. In other embodiments, the inspection circuit 130 may subtract the area of ​​the region CR from the area of ​​the dummy pattern A, and then use the subtraction result as a calculated value.

[0055] In another possible embodiment, the checking circuit 130 uses a Boolean operation OP2 to calculate the dummy pattern A and the layout pattern B to generate a second calculated value. In this example, the second calculated value is the difference between the area of ​​the layout pattern B and the area of ​​the region CR. In other words, the second calculated value is the area of ​​the region UR of the layout pattern B.

[0056] In some embodiments, the checking circuit 130 uses a Boolean operation OP3 to calculate the dummy pattern A and the layout pattern B to generate a third calculated value. In this example, the third calculated value is the sum of the area of ​​the dummy pattern A and the area of ​​the region UR of the layout pattern B. In this example, the Boolean operation OP3 is an OR operation.

[0057] In another embodiment, the inspection circuit 130 uses a Boolean operation OP4 to calculate the dummy pattern A and the layout pattern B to generate a fourth calculated value. In this example, the fourth calculated value is the area CR of the layout pattern B. In this example, the Boolean operation OP4 is an AND operation.

[0058] In other embodiments, the inspection circuit 130 uses a Boolean operation OP5 to calculate the dummy pattern A and the layout pattern B to generate a fifth calculated value. In this example, the inspection circuit 130 calculates the difference between the area of ​​the dummy pattern A and the area of ​​region CR, and then adds the difference to the area of ​​region UR. In this example, the Boolean operation OP5 is a mutually exclusive OR (XOR) operation.

[0059] Figure 10 This is a schematic diagram of the method for checking changes in the layout pattern according to the present invention. First, a first layout pattern is formed in a first semiconductor layer (step S101). The present invention does not limit the type of the first layout pattern. In one possible embodiment, the first layout pattern may be a layout pattern used to form a well, an oxide diffusion region (OD), a polysilicon region, a via, or a metal.

[0060] Next, a first dummy pattern is formed in a first dummy layer (step S102). The present invention does not limit the shape of the first dummy pattern. The first dummy pattern is a pattern with a special irregular shape. In one possible embodiment, the first dummy pattern is a pattern similar to a two-dimensional barcode.

[0061] A Boolean operation is used to calculate the first layout pattern and the first dummy pattern to generate a first calculated value (step S103). In one possible embodiment, the Boolean operation is an AND operation, an OR operation, a XOR operation, or a combination of the above operations. In some embodiments, step S103 generates a first calculated value based on the overlapping area of ​​the first layout pattern and the first dummy pattern. Figure 9For example, the first calculated value might be the area of ​​the first dummy pattern (A) minus the area of ​​the overlapping region (CR) of the first layout pattern (B) and the first dummy pattern (A). In other embodiments, the first calculated value might be the area of ​​the first layout pattern (B) minus the area of ​​the overlapping region (CR) of the first layout pattern (B) and the first dummy pattern (A). In some embodiments, the first calculated value might be the sum of the areas of the first dummy pattern (A) and the first layout pattern (B), minus the area of ​​the overlapping region (CR) of the first layout pattern (B) and the first dummy pattern (A). In other embodiments, the first calculated value might be the area of ​​the overlapping region (CR) of the first layout pattern (B) and the first dummy pattern (A). In some embodiments, the first calculated value might be the area of ​​the first dummy pattern (A) minus the area of ​​the overlapping region (CR) of the first layout pattern (B) and the first dummy pattern (A), plus the area of ​​the region (UR) of the first layout pattern (B) that does not overlap with the first dummy pattern (A).

[0062] Next, it is determined whether the first calculated value is the same as the first preset value (step S104). When the first calculated value is different from the first preset value, it indicates that the first layout pattern has been changed. Therefore, the first layout pattern is marked (step S105). In some embodiments, step S105 records the first layout pattern. The user can determine the changed level based on the recording result of step S105. However, when the first calculated value is the same as the first preset value, it indicates that the first layout pattern has not been changed. Therefore, the first layout pattern is not marked (step S106).

[0063] In some embodiments, step S102 further forms a second dummy pattern in a second dummy layer. The second dummy pattern may be the same as or different from the first dummy pattern. In one possible embodiment, there are slight differences between the first dummy pattern and the second dummy pattern, such as the size of the line segments or the spacing between the line segments. Step S103 also uses the same Boolean operation to calculate the first layout pattern and the second dummy pattern to generate a second calculated value. In other embodiments, step S103 may use another Boolean operation to calculate the first layout pattern and the second dummy pattern to obtain a second calculated value. In this example, when the first calculated value is the same as the first preset value, step S106 does not mark the first layout pattern and compares the second calculated value with a second preset value. When the second calculated value is different from the second preset value, it indicates that the first layout pattern has changed. Therefore, step S105 is executed to mark the first layout pattern.

[0064] In one possible embodiment, step S101 further forms a second layout pattern in a second semiconductor layer. In this example, step S103 uses the same Boolean operation to calculate the second layout pattern and the first dummy pattern to generate a third calculated value. In another possible embodiment, step S103 uses different Boolean operations to calculate the second layout pattern and the first dummy pattern to obtain a third calculated value. In this example, step S104 further compares the third calculated value with a third preset value to determine whether the second layout pattern has been changed. When the third calculated value is different from the third preset value, it indicates that the second layout pattern has been changed. Therefore, step S105 marks and records the second layout pattern.

[0065] In other embodiments, step S103 also utilizes the same Boolean operation to calculate a second layout pattern and a first dummy pattern to generate a third calculated value. In this example, step S104 compares the first and third calculated values ​​with a first preset value. When both the first and third calculated values ​​are equal to the first preset value, it indicates that the first layout pattern and the second layout pattern are the same. When either the first or third calculated value differs from the first preset value, it indicates that there is a difference between the first layout pattern and the second layout pattern. Therefore, step S105 records the level of the difference and outputs a check result (including the level of the difference). In this example, the second layout pattern is located in a second semiconductor layer, and the second semiconductor layer is not integrated with the first semiconductor layer on the same wafer.

[0066] It is important to understand that when a component or layer is mentioned as being "coupled" to another component or layer, it can be directly coupled or connected to the other component or layer, or have other components or layers in between. Conversely, if a component or layer is "connected" to another component or layer, there will be no other components or layers in between.

[0067] The semiconductor element layout change inspection method, or a specific configuration or part thereof, of the present invention can exist in the form of code. The code can be stored on physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (e.g., computer-readable) storage media, or not limited to external computer program products. When the code is loaded and executed by a machine, such as a computer, that machine becomes part of the inspection circuitry of the present invention. The code can also be transmitted via some transmission medium, such as wires or cables, optical fibers, or any transmission method. When the code is received, loaded, and executed by a machine, such as a computer, that machine becomes part of the inspection circuitry of the present invention. When implemented in a general-purpose processing unit, the code, combined with the processing unit, provides a unique device that operates similarly to an application-specific logic circuit.

[0068] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by those skilled in the art. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their relevant technical field, and not as idealized or overly formal expressions. While terms such as "first," "second," etc., may be used to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another.

[0069] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments using hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A semiconductor device layout, characterized in that, include: A first semiconductor layer having a first layout pattern; as well as A first dummy layer, having a first dummy pattern; in: A circuit is used to calculate the first layout pattern and the first dummy pattern to generate a first calculated value, and compares the first calculated value with a first preset value to determine whether the first layout pattern has been changed. When the first calculated value is not equal to the first preset value, it indicates that the first layout pattern has been changed. Therefore, the checking circuit indicates and records the position of the first layout pattern. The inspection circuit provides a test report indicating whether the first layout pattern has been altered. This test report is a design rule check report.

2. The semiconductor device layout as described in claim 1, characterized in that, The first calculated value is the overlap area between the first layout pattern and the first dummy pattern.

3. The semiconductor device layout as described in claim 1, characterized in that, The first layout pattern includes: A first region, the portion overlapping the first dummy pattern; and A second region, which does not overlap with the first dummy pattern; The first calculated value is the sum of the areas of the first dummy pattern and the second region.

4. The semiconductor device layout as described in claim 1, characterized in that, The first layout pattern includes: A first region, the portion overlapping the first dummy pattern; and A second region, which does not overlap with the first dummy pattern; The inspection circuit calculates the sum of the areas of the first dummy pattern and the second region, and then calculates the area difference between the sum of the areas and the area of ​​the first region. The area difference is used as the first calculated value.

5. The semiconductor device layout as described in claim 1, characterized in that, The first dummy pattern is a two-dimensional barcode pattern.

6. The semiconductor device layout as described in claim 1, characterized in that, Also includes: A second dummy layer having a second dummy pattern; in: The inspection circuit calculates a second calculated value between the first layout pattern and the second dummy pattern, and compares the second calculated value with a second preset value; When the first calculated value is the same as the first preset value and the second calculated value is different from the second preset value, it indicates that the first layout pattern has been changed.

7. The semiconductor device layout as described in claim 6, characterized in that, The first dummy pattern is different from the second dummy pattern.

8. The semiconductor device layout as described in claim 1, characterized in that, Also includes: A second semiconductor layer having a second layout pattern; The inspection circuit calculates a third calculated value between the second layout pattern and the first dummy pattern, and compares the third calculated value with a third preset value to determine whether the second layout pattern has been changed.

9. The semiconductor device layout as described in claim 8, characterized in that, The second layout pattern does not overlap with the first layout pattern.

10. The semiconductor device layout as described in claim 1, characterized in that, The inspection circuit compares the first layout pattern with a second layout pattern to determine whether the first layout pattern is the same as the second layout pattern, wherein the second layout pattern is located in a second semiconductor layer, and the second semiconductor layer is different from the first semiconductor layer.

11. The semiconductor device layout as described in claim 10, characterized in that, When there is a difference between the first layout pattern and the second layout pattern, the inspection circuit records the location of the difference.

12. A method for inspecting changes in the layout of semiconductor components, characterized in that, include: A first layout pattern is formed in a first semiconductor layer; A first dummy pattern is formed in a first dummy layer; Using a Boolean operation, the first layout pattern and the first dummy pattern are calculated to generate a first calculated value; Compare the first calculated value with a first preset value; When the first calculated value is not equal to the first preset value, the position of the first layout pattern is marked and recorded; and Provide a test report indicating whether the first layout pattern has been altered. in: When the first calculated value differs from the first preset value, it indicates that the first layout pattern has been changed. This test report is a design rule check report.

13. The method for inspecting changes in semiconductor device layout as described in claim 12, characterized in that, The Boolean operation is either an AND operation, an OR operation, or a mutually exclusive OR operation.

14. The method for inspecting changes in semiconductor device layout as described in claim 12, characterized in that, Also includes: A second dummy pattern is formed in a second dummy layer; Using the Boolean operation, the first layout pattern and the second dummy pattern are calculated to generate a second calculated value; Compare the second calculated value with a second preset value; When the first calculated value is the same as the first preset value and the second calculated value is different from the second preset value, it indicates that the first layout pattern has been changed.

15. The method for inspecting changes in semiconductor device layout as described in claim 14, characterized in that, The first dummy pattern is different from the second dummy pattern.

16. The method for inspecting changes in semiconductor device layout as described in claim 12, characterized in that, Also includes: A second layout pattern is formed in a second semiconductor layer; Using the Boolean operation, the second layout pattern and the first dummy pattern are calculated to generate a third calculated value; The third calculated value is compared with a third preset value to determine whether the second layout pattern has been changed.

17. The method for inspecting changes in semiconductor device layout as described in claim 12, characterized in that, Also includes: The first layout pattern is compared with a second layout pattern to determine whether the first layout pattern is the same as the second layout pattern; The second layout pattern is located in a second semiconductor layer, which is different from the first semiconductor layer.

18. The method for inspecting changes in semiconductor device layout as described in claim 17, characterized in that, Also includes: When there is a difference between the first layout pattern and the second layout pattern, the position of the difference is recorded.

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