A compact three-port low parasitic capacitance scr device for electrostatic discharge protection

Abstract

This invention belongs to the field of electrostatic discharge (ESD) protection device design for integrated circuits, particularly silicon controlled rectifier (SCR) devices. Specifically, it provides a compact SCR device with low parasitic capacitance for ESD protection. The device described in this invention is a three-port device that can be used for ESD protection between the input / output (I / O) ports, the power rail (VDD), and the ground rail (VSS). The device contains five SCR structures and features low trigger voltage, high current discharging capability, high stability, low parasitic capacitance, and a smaller device area. After optimized layout, the device has a smaller area, further optimizing device performance, and is particularly suitable for on-chip ESD protection using nanometer-scale processes.

Description

Technical Field

[0001] This invention belongs to the field of electrostatic discharge (ESD) protection device design for integrated circuits (ICs), and relates to an ESD protection structure device, particularly a compact novel silicon controlled rectifier (SCR) device with three ports, specifically providing a compact three-port low parasitic capacitance SCR device for ESD protection. Background Technology

[0002] ESD refers to the phenomenon of charge transfer occurring when two objects with different electrostatic potentials come into contact. This common phenomenon can damage submicron-sized ICs, causing immediate or potential failures. Therefore, ESD protection for ICs is necessary. This protection in IC products is generally provided by ESD protection devices and ESD protection circuits composed of these devices. As semiconductor technology advances into the nanometer range and IC operating frequencies further increase, signal loss due to parasitic capacitance between signal ports and power / ground rails in ESD protection devices becomes increasingly significant. The rising cost of wafer manufacturing with advanced processes necessitates implementing ESD protection in smaller areas to save production costs. Therefore, finding ESD protection devices with strong discharge current capability, small footprint, and low parasitic capacitance is of great importance.

[0003] ESD can occur between any port combinations. To provide full-chip ESD protection for IC chips with multiple I / Os, it is necessary to implement protection for seven different discharge combinations, including: DS combination from VDD to VSS, SD combination from VSS to VDD, PS mode from I / O to VSS, NS combination from VSS to I / O, PD combination from I / O to VDD, ND combination from VDD to I / O, and I / O combination between different I / Os. Generally, I / O combinations can be protected by using the aforementioned six protection paths.

[0004] DCSCR is an SCR device that modifies the lead connection method based on traditional SCR devices. In the forward direction, DCSCR utilizes an internal diode string to trigger the internal SCR structure for electrostatic discharge. It boasts advantages such as simple structure, strong discharge capability, low trigger voltage, high robustness, and small parasitic capacitance, making it particularly advantageous for ESD protection in advanced low-voltage CMOS processes. However, in the reverse direction, DCSCR requires the internal diode string to undergo avalanche breakdown under high voltage to release static electricity. Low-voltage IC chips cannot withstand such high voltages, thus DCSCR devices cannot effectively protect low-voltage IC chips in the reverse direction.

[0005] A typical port-based full-chip ESD protection scheme using DCSCR requires connecting four DCSCR devices to the I / O ports for ESD protection of PS, NS, ND, and PD combinations, and also requires an additional bidirectional power clamping unit. These devices occupy a large amount of chip area and introduce a large amount of parasitic capacitance at the I / O ports.

[0006] To further reduce the parasitic capacitance of DCSCR devices in full-chip ESD protection, and to further save the area of ​​the full-chip ESD protection network without reducing the overall ESD protection capability, this invention proposes a compact three-port low parasitic capacitance SCR device for ESD protection. This device internally contains five SCR structures, providing six SCR current release paths between the three ports, and reduces junction capacitance by sharing a heavily doped region. After optimizing the layout, the device has a smaller area.

[0007] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0008] The purpose of this invention is to propose a compact three-port low parasitic capacitance SCR device for ESD protection. This device features low parasitic capacitance and a small footprint, and can provide high-performance ESD protection in six directions between the three ports. Using this device for ESD protection of the chip eliminates the need for a power clamping unit, thereby reducing the area of ​​the entire chip's ESD protection network.

[0009] To achieve the above objectives, the present invention adopts the following technical solution:

[0010] A compact three-port low parasitic capacitance SCR device includes:

[0011] A P-type silicon substrate, wherein a first P-type well region, a second P-type well region, a first deep N-type well region, a first N-type well region, a second N-type well region, a third N-type well region, and a fourth N-type well region are formed on the P-type silicon substrate; the first P-type well region is completely surrounded by the first N-type well region; the first P-type well region is isolated from the P-type silicon substrate below by the first deep N-type well region; the first N-type well region, the second N-type well region, the third N-type well region, and the fourth N-type well region are all completely surrounded by the second P-type well region; the first N-type well region, the second N-type well region, the third N-type well region, and the fourth N-type well region are arranged sequentially from left to right;

[0012] Within a first N-type well region to the left of the first P-type well region, a first heavily doped N-type region and a first heavily doped P-type region are arranged sequentially from left to right; within the first P-type well region, a second heavily doped N-type region, a second heavily doped P-type region, and a third heavily doped N-type region are arranged sequentially from left to right; within a first N-type well region to the right of the first P-type well region, a third heavily doped P-type region and a fourth heavily doped N-type region are arranged sequentially from left to right; within the second N-type well region, a fourth heavily doped P-type region and a fifth heavily doped N-type region are arranged sequentially from left to right; within the third N-type well region, a fifth heavily doped P-type region, a sixth heavily doped N-type region, and a sixth heavily doped P-type region are arranged sequentially from left to right; within the fourth N-type well region, a seventh heavily doped N-type region and a seventh heavily doped P-type region are arranged sequentially from left to right.

[0013] The second, third, fifth, and sixth heavily doped N-type regions are connected to the first port; the first and fifth heavily doped P-type regions are connected to the second port; the third and seventh heavily doped P-type regions are connected to the third port; the first, second, and third heavily doped N-type regions are directly connected via a first metal interconnect; and the fourth, sixth, and seventh heavily doped P-type regions are directly connected via a second metal interconnect.

[0014] Shallow trench isolation is provided between the first N-type heavily doped region and the first P-type heavily doped region, between the first P-type heavily doped region and the second N-type heavily doped region, between the second N-type heavily doped region and the second P-type heavily doped region, between the second P-type heavily doped region and the third N-type heavily doped region, between the third N-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the fourth N-type heavily doped region, between the fourth N-type heavily doped region and the fourth P-type heavily doped region, between the fourth P-type heavily doped region and the fifth N-type heavily doped region, between the fifth N-type heavily doped region and the fifth P-type heavily doped region, between the fifth P-type heavily doped region and the sixth N-type heavily doped region, between the sixth N-type heavily doped region and the sixth P-type heavily doped region, between the sixth P-type heavily doped region and the seventh N-type heavily doped region, and between the seventh N-type heavily doped region and the seventh P-type heavily doped region.

[0015] A layout-optimized three-port low parasitic capacitance SCR device, comprising:

[0016] A P-type silicon substrate, wherein a first P-type well region, a second P-type well region, a first deep N-type well region, a first N-type well region, a second N-type well region, a third N-type well region, and a fourth N-type well region are formed on the P-type silicon substrate; the first P-type well region is completely surrounded by the first N-type well region; the first P-type well region is isolated from the P-type silicon substrate through the first deep N-type well region; the first N-type well region, the second N-type well region, the third N-type well region, and the fourth N-type well region are all completely surrounded by the second P-type well region; the first N-type well region, the second N-type well region, the third N-type well region, and the fourth N-type well region are arranged sequentially from left to right;

[0017] Within the first N-type well region to the left of the first P-type well region, a first heavily doped N-type region and a first heavily doped P-type region are sequentially arranged from bottom to top; within the first P-type well region, a second heavily doped P-type region and a second heavily doped N-type region are sequentially arranged from bottom to top; within the first N-type well region to the right of the first P-type well region, a third heavily doped N-type region and a third heavily doped P-type region are sequentially arranged from bottom to top; within the second N-type well region, a fourth heavily doped P-type region and a fourth heavily doped N-type region are sequentially arranged from bottom to top; within the third N-type well region, a third heavily doped N-type region and a third heavily doped P-type region are sequentially arranged from bottom to top; within the third N-type well region, a third heavily doped P-type region and a fourth heavily doped N-type region are sequentially arranged from bottom to top; within the third N-type well region, a third heavily doped P-type region and a third heavily doped P-type region are sequentially arranged from bottom to top; There is a fifth N-type heavily doped region and a fifth P-type heavily doped region; the fourth N-type well region has a sixth P-type heavily doped region and a sixth N-type heavily doped region arranged sequentially from bottom to top; the first N-type heavily doped region, the second P-type heavily doped region, the third N-type heavily doped region, the fourth P-type heavily doped region, the fifth N-type heavily doped region, and the sixth P-type heavily doped region are arranged sequentially from left to right; the first P-type heavily doped region, the second N-type heavily doped region, the third P-type heavily doped region, the fourth N-type heavily doped region, the fifth P-type heavily doped region, and the sixth N-type heavily doped region are arranged sequentially from left to right;

[0018] The second N-type heavily doped region and the fifth P-type heavily doped region are connected to the first port; the first P-type heavily doped region and the fourth N-type heavily doped region are connected to the second port; the third P-type heavily doped region and the sixth N-type heavily doped region are connected to the third port; the first N-type heavily doped region, the second P-type heavily doped region, and the third N-type heavily doped region are directly connected by a first metal interconnect; the fourth P-type heavily doped region, the fifth N-type heavily doped region, and the sixth P-type heavily doped region are directly connected by a second metal interconnect.

[0019] Shallow trench isolation is provided between the first N-type heavily doped region and the first P-type heavily doped region, between the second P-type heavily doped region and the second N-type heavily doped region, between the third N-type heavily doped region and the third P-type heavily doped region, between the fourth P-type heavily doped region and the fourth N-type heavily doped region, between the fifth N-type heavily doped region and the fifth P-type heavily doped region, and between the sixth P-type heavily doped region and the sixth N-type heavily doped region; shallow trench isolation is provided between the first P-type heavily doped region and the second N-type heavily doped region, between the second N-type heavily doped region and the third P-type heavily doped region, and between the third Shallow trench isolation is provided between the P-type heavily doped region and the fourth N-type heavily doped region, between the fourth N-type heavily doped region and the fifth P-type heavily doped region, and between the fifth P-type heavily doped region and the sixth N-type heavily doped region; shallow trench isolation is also provided between the first N-type heavily doped region and the second P-type heavily doped region, between the second P-type heavily doped region and the third N-type heavily doped region, between the third N-type heavily doped region and the fourth P-type heavily doped region, between the fourth P-type heavily doped region and the fifth P-type heavily doped region, and between the fifth P-type heavily doped region and the sixth N-type heavily doped region.

[0020] This invention is a novel technical solution proposed by the inventor in this technical field through original improvements to the shortcomings of existing technologies, and after complex theoretical and practical verification. It is not easily obtained by those skilled in the art. The device described in this invention is a novel three-port DCSCR device obtained by structural adjustment based on a traditional unidirectional DCSCR device, and it has significant substantial differences from the traditional unidirectional DCSCR. It provides ESD protection for the ports using a combination of PS, PD, NS, and ND. The device described in this invention has lower parasitic capacitance and a smaller device area, further solving the technical problems of low chip area utilization, large footprint, and large parasitic capacitance of existing DCSCR-type ESD protection devices under advanced processes, showing significant progress. The device described in this invention can perform ESD protection using a combination of SD and DS, avoiding the use of power clamping units, further saving the area of ​​the entire chip ESD protection network, demonstrating significant progress.

[0021] The device described in this invention can be manufactured using general integrated circuit manufacturing processes and applied to the protection of a port or the entire chip of a low-voltage integrated circuit chip. Using this invention for full chip protection can save chip area, reduce parasitic capacitance, and lower chip production costs. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0023] Figure 1 Cross-sectional view of a DCSCR device

[0024] Figure 2 Top view of the device according to claim 1

[0025] Figure 3 A cross-sectional view of the device according to claim 1.

[0026] Figure 4 Top view of Example 1

[0027] Figure 5 This is a cross-sectional schematic diagram of the current discharge path under ND mode ESD in Example 1.

[0028] Figure 6 This is a cross-sectional schematic diagram of Example 1 operating in NS mode ESD.

[0029] Figure 7 This is a cross-sectional schematic diagram of Example 1 operating in PD mode ESD.

[0030] Figure 8 This is a cross-sectional schematic diagram of Example 1 operating in PS mode under ESD.

[0031] Figure 9 This is a cross-sectional schematic diagram of Example 1 operating in SD mode ESD.

[0032] Figure 10 This is a cross-sectional schematic diagram of Example 1 operating in DS mode ESD.

[0033] Figure 11 Top view of Example 2

[0034] Figure 12 Top view of the device according to claim 2

[0035] Figure 13 Top view of Example 3

[0036] Figure 14 Top view of Example 4 Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings and references. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0038] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0039] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0040] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0041] Figure 1 Cross-sectional views of traditional DC-DCR devices are shown, including:

[0042] A P-type silicon substrate 110, wherein a first P-type well region 121, a second P-type well region 120, a first N-type deep well region 130, and a first N-type well region 140 are formed on the P-type silicon substrate 110; the first P-type well region 121 is surrounded by the first N-type well region 140 in all directions; the first P-type well region 121 is isolated from the P-type silicon substrate 110 below by the first N-type deep well region 130; the first N-type well region 140 is surrounded by the second P-type well region 120 in all directions.

[0043] A first N-type heavily doped region 160 and a first P-type heavily doped region 150 are arranged sequentially from left to right in the first N-type well region 140 to the left of the first P-type well region 121; a second N-type heavily doped region 161 and a second P-type heavily doped region 151 are arranged sequentially from left to right in the first P-type well region 121; the first P-type heavily doped region 150 is connected to the anode port; the second N-type heavily doped region 161 is connected to the cathode port; the first N-type heavily doped region 160 and the second P-type heavily doped region 151 are directly connected by a metal wire.

[0044] A DCSCR device includes two diode paths: path 1, consisting of a P-type heavily doped region 150, an N-well 140, and an N-type heavily doped region 160, running from the anode port to the metal interconnect; and path 2, consisting of a P-type heavily doped region 151, a P-well 121, and an N-type heavily doped region 161, running from the metal interconnect to the cathode port. The DCSCR device also includes an SCR path 1, consisting of the P-type heavily doped region 150, an N-well 140, a P-well 121, and an N-type heavily doped region 161, running from the anode port to the cathode port. Clearly, traditional DCSCR devices can only provide current discharge paths for the anode-to-cathode diode path and the SCR path, resulting in low area utilization.

[0045] A cross-sectional view of the device according to claim 1 is shown below. Figure 2 As shown, a cross-sectional view of the device according to claim 1 is shown below. Figure 3 As shown, it includes:

[0046] A P-type silicon substrate 110 is formed thereon, comprising a first P-type well region 121, a second P-type well region 120, a first N-type deep well region 130, a first N-type well region 140, a second N-type well region 141, a third N-type well region 142, and a fourth N-type well region 143. The first P-type well region 121 is completely surrounded by the first N-type well region 140. The first P-type well region 121 is isolated from the P-type silicon substrate 110 by the first N-type deep well region 130. The first N-type well region 140, the second N-type well region 141, the third N-type well region 142, and the fourth N-type well region 143 are all completely surrounded by the second P-type well region 120. The first N-type well region 140, the second N-type well region 141, the third N-type well region 142, and the fourth N-type well region 143 are arranged sequentially from left to right.

[0047] Within the first N-type well region 140 to the left of the first P-type well region 121, a first heavily doped N-type region 160 and a first heavily doped P-type region 150 are sequentially arranged from left to right; within the first P-type well region 121, a second heavily doped N-type region 161, a second heavily doped P-type region 151, and a third heavily doped N-type region 162 are sequentially arranged from left to right; within the first N-type well region 140 to the right of the first P-type well region 121, a third heavily doped P-type region 151 is sequentially arranged from left to right. 2. A fourth N-type heavily doped region 163 is provided; a fourth P-type heavily doped region 153 and a fifth N-type heavily doped region 164 are arranged sequentially from left to right in the second N-type well region 141; a fifth P-type heavily doped region 154, a sixth N-type heavily doped region 165 and a sixth P-type heavily doped region 155 are arranged sequentially from left to right in the third N-type well region 142; a seventh N-type heavily doped region 166 and a seventh P-type heavily doped region 156 are arranged sequentially from left to right in the fourth N-type well region 143.

[0048] The second N-type heavily doped region 161, the third N-type heavily doped region 162, the fifth P-type heavily doped region 154, and the sixth P-type heavily doped region 155 are connected to the first port; the first P-type heavily doped region 150 and the fifth N-type heavily doped region 164 are connected to the second port; the third P-type heavily doped region 152 and the seventh N-type heavily doped region 166 are connected to the third port; the first N-type heavily doped region 160, the second P-type heavily doped region 151, and the third N-type heavily doped region 162 are directly connected through the first metal interconnect; the fourth P-type heavily doped region 153, the sixth N-type heavily doped region 165, and the seventh P-type heavily doped region 156 are directly connected through the second metal interconnect.

[0049] Between the first N-type heavily doped region 160 and the first P-type heavily doped region 150, between the first P-type heavily doped region 150 and the second N-type heavily doped region 161, between the second N-type heavily doped region 161 and the second P-type heavily doped region 151, between the second P-type heavily doped region 151 and the third N-type heavily doped region 162, between the third N-type heavily doped region 162 and the third P-type heavily doped region 152, between the third P-type heavily doped region 152 and the fourth N-type heavily doped region 163, and between the fourth N-type heavily doped region 163 and the fourth P-type heavily doped region 150... Shallow trench isolation is provided between doped regions 153, between the fourth P-type heavily doped region 153 and the fifth N-type heavily doped region 164, between the fifth N-type heavily doped region 164 and the fifth P-type heavily doped region 154, between the fifth P-type heavily doped region 154 and the sixth N-type heavily doped region 165, between the sixth N-type heavily doped region 165 and the sixth P-type heavily doped region 155, between the sixth P-type heavily doped region 155 and the seventh N-type heavily doped region 166, and between the seventh N-type heavily doped region 166 and the seventh P-type heavily doped region 156.

[0050] From the perspective of device structure:

[0051] The device of claim 1 comprises six diode paths, namely: diode path 1, consisting of a P-type heavily doped region 150, an N-well 140, and an N-type heavily doped region 160, extending from the third port to the first metal interconnect; diode path 2, consisting of a P-type heavily doped region 151, a P-well 121, an N-type heavily doped region 161, and an N-type heavily doped region 162, extending from the first metal interconnect to the second port; and diode path 3, consisting of a P-type heavily doped region 152, an N-well 140, and an N-type heavily doped region 163, extending from the first port to the third metal interconnect. A diode path 3 consisting of a metal interconnect; a diode path 4 consisting of a P-type heavily doped region 153, an N-well 141, and an N-type heavily doped region 164, extending from the second metal interconnect to the third port; a diode path 5 consisting of a P-type heavily doped region 154, a P-type heavily doped region 155, an N-well 142, and an N-type heavily doped region 165, extending from the second port to the second metal interconnect; and a diode path 6 consisting of a P-type heavily doped region 156, an N-well 143, and an N-type heavily doped region 166, extending from the second metal interconnect to the first port.

[0052] The device of claim 1 comprises five SCR paths, namely: SCR path 1, consisting of P-type heavily doped region 150, N-well 140, P-well 121, N-type heavily doped region 161, and N-type heavily doped region 162, from the third port to the second port; SCR path 2, consisting of P-type heavily doped region 152, N-well 140, P-well 121, N-type heavily doped region 161, and N-type heavily doped region 162, from the first port to the second port; and SCR path 3, consisting of P-type heavily doped region 154, P-type heavily doped region 155, N-well 162, and P-type heavily doped region 162. 42. The SCR path 3, consisting of P-well 120, N-well 141, and N-type heavily doped region 164, runs from the second port to the third port; 4. The SCR path 4, consisting of P-type heavily doped region 154, P-type heavily doped region 155, N-well 142, P-well 120, N-well 143, and N-type heavily doped region 166, runs from the second port to the first port; 5. The SCR path 5, consisting of P-type heavily doped region 152, N-well 140, P-well 120, N-well 141, and N-type heavily doped region 164, runs from the first port to the third port.

[0053] By sharing a heavily doped region, the main parasitic capacitance introduced on the I / O of the device described in claim 1 is the PN junction capacitance corresponding to diode path 2 and diode path 5 at the second port. The capacitance value is limited, and the capacitance is significantly reduced compared to using four DCSCRs for ESD protection of the I / O.

[0054] Example 1: This example provides a method for ESD protection of I / O ports, VDD, and VSS using the three-port compact low-capacitance DCSCR device described in claim 1. In this example, the device described in claim 1 is connected to the actual I / O ports, VSS, and VDD ports as follows: Terminal 1 is connected to the IC's VSS, Terminal 2 is connected to the IC's I / O, and Terminal 3 is connected to the IC's VDD. Figure 4 As shown.

[0055] In terms of working principle:

[0056] When a combined ND and ESD event occurs, the VDD terminal potential rises, causing diode path 1 and diode path 2 to turn on first. Electrostatic current flows from the VDD terminal through diode path 1, through the first metal interconnect, and then is discharged to the I / O terminal via diode path 2. Subsequently, the current in the diode paths further increases, triggering SCR path 1 to turn on. The SCR structure then performs large-current discharge and voltage clamping. Figure 5 As shown in the cross-sectional view;

[0057] When a combined NS ESD occurs, the VSS terminal potential rises, causing diode path 3 and diode path 2 to turn on first. Electrostatic current flows from the VSS terminal through diode path 3, through the first metal interconnect, and then is discharged to the I / O terminal via diode path 2. Subsequently, the current in the diode path further increases, triggering SCR path 2 to turn on. The SCR structure then performs large-current discharge and voltage clamping. Figure 6 As shown in the cross-sectional view;

[0058] When a combined PD ESD occurs, the I / O terminal potential rises, causing diode paths 5 and 4 to turn on first. Electrostatic current flows from the I / O terminal through diode path 5, through the second metal interconnect, and then discharges to the VDD terminal via diode path 4. Subsequently, the current in the diode paths further increases, triggering the SCR path 3 to turn on. The SCR structure then performs large-current discharge and voltage clamping. Figure 7 As shown in the cross-sectional view;

[0059] When a combined PS-based ESD occurs, the I / O terminal potential rises, causing diode paths 5 and 6 to turn on first. Electrostatic current flows from the VSS terminal through diode path 5, through the second metal interconnect, and then is discharged back to the VSS terminal via diode path 6. Subsequently, the current in the diode paths further increases, triggering the SCR path 4 to turn on. The SCR structure then performs large-current discharge and voltage clamping. Figure 8 As shown in the cross-sectional view;

[0060] When a combined SD (stable surface discharge) ESD event occurs, the VSS terminal potential rises, causing diode paths 3, 2, 5, and 4 to turn on. The electrostatic current first flows from the VSS terminal through diode path 3, then through the first metal interconnect, and finally through diode path 2 to the I / O terminal. From the I / O terminal, it flows through diode path 5, then through the second metal interconnect, and finally through diode path 4 to the VDD terminal. Subsequently, the current in the diode paths further increases, triggering SCR path 5 to turn on. The SCR structure then performs high-current discharge and voltage clamping. Figure 9 As shown in the cross-sectional view;

[0061] When a combined DS discharge occurs, since there is no single SCR path from VDD to VSS, after the VDD potential rises, diode paths 1 and 2 turn on first, triggering SCR path 1 to turn on. The electrostatic current is discharged from VDD to the I / O terminal. The rise in I / O potential causes diode paths 5 and 6 to turn on, further triggering SCR path 4 to turn on. The electrostatic current is finally discharged from the I / O terminal to VSS. In other words, under a combined DS discharge, the device actually utilizes a combination of discharge paths from both ND and PS modes to release static electricity. Figure 10 As shown in the cross-sectional view.

[0062] Example 2 provides another example of using the three-port compact low-capacitance DCSCR device described in claim 1 to provide ESD protection for I / O ports and VDD and VSS. In this example, the device described in claim 1 is connected to the actual I / O ports, VSS, and VDD ports as follows: Terminal 1 is connected to the IC's VDD, Terminal 2 is connected to the IC's I / O, and Terminal 3 is connected to the IC's VSS. Figure 11 As shown.

[0063] In terms of working principle: The obvious difference between Example 2 and Example 1 is that the way the device is connected to the IC has been changed.

[0064] Compared to Example 1, the main difference in the working principle of this example is:

[0065] When a combined ND ESD occurs, the device uses diode path 3, diode path 2, and SCR path 2 for ESD protection; when a combined NS ESD occurs, the device uses diode path 1, diode path 2, and SCR path 1 for ESD protection; when a combined PD ESD occurs, the device uses diode path 5, diode path 6, and SCR path 4 for ESD protection; when a combined PS ESD occurs, the device uses diode path 5, diode path 4, and SCR path 3 for ESD protection; when a combined DS ESD occurs, the device uses diode path 3, diode path 2, diode path 5, diode path 4, and SCR path 5 for ESD protection; when a combined SD ESD occurs, the device uses the protection paths in both ND and PS modes for ESD protection.

[0066] Example 2 adopts a protection method with one SCR path as the main path in the protection path of DS combined ESD, which improves the protection capability of DS mode.

[0067] In IC products, each I / O port can be protected by a device as described in claim 1. The device as described in claim 1 corresponding to the relevant I / O port between each VDD power rail and each VSS ground rail can participate in the ESD protection of the SD combination and DS combination that occur between VSS and VDD. At this time, it is not necessary to connect a power clamping unit between VSS and VDD. Therefore, ESD protection can be performed on these different I / O ports using Embodiment 1 and Embodiment 2 respectively.

[0068] Considering that the diode path of the device described in claim 1 is mainly used to trigger the SCR structure, and the diode only plays an auxiliary role in discharging static electricity after the SCR is turned on, the actual current flowing through the diode is small, the device described in claim 2 shifts the diode path to be perpendicular to the SCR path, and at the same time reduces the area of ​​the heavily doped region on the diode path, thereby further saving device area and parasitic capacitance. Compared with the device described in claim 1, the device described in claim 2 is more compact. A top view of the device described in claim 2 is shown below. Figure 12 As shown, it includes:

[0069] A P-type silicon substrate 110 has a first P-type well region 121, a second P-type well region 120, a first deep N-type well region 130, a first N-type well region 140, a second N-type well region 141, a third N-type well region 142, and a fourth N-type well region 143 formed on it. The first P-type well region 121 is completely surrounded by the first N-type well region 140. The first P-type well region 121 is isolated from the P-type silicon substrate 110 below by the first deep N-type well region 130. The first N-type well region 140, the second N-type well region 141, the third N-type well region 142, and the fourth N-type well region 143 are all completely surrounded by the second P-type well region 120. The first N-type well region 140, the second N-type well region 141, the third N-type well region 142, and the fourth N-type well region 143 are arranged sequentially from left to right.

[0070] Within the first N-type well region 140 to the left of the first P-type well region 121, a first heavily doped N-type region 160 and a first heavily doped P-type region 150 are sequentially arranged from bottom to top; within the first P-type well region 121, a second heavily doped P-type region 151 and a second heavily doped N-type region 161 are sequentially arranged from bottom to top; within the first N-type well region 140 to the right of the first P-type well region 121, a third heavily doped N-type region 162 and a third heavily doped P-type region 152 are sequentially arranged from bottom to top; within the second N-type well region 141, a fourth heavily doped P-type region 153 and a fourth heavily doped N-type region 163 are sequentially arranged from bottom to top; within the third N-type well region 142, a fifth heavily doped P-type region 160 and a third heavily doped P-type region 152 are sequentially arranged from bottom to top. The fourth N-type well region 143 contains an N-type heavily doped region 164 and a fifth P-type heavily doped region 154; a sixth P-type heavily doped region 155 and a sixth N-type heavily doped region 165 are arranged sequentially from bottom to top within the fourth N-type well region 143; the first N-type heavily doped region 160, the second P-type heavily doped region 151, the third N-type heavily doped region 162, the fourth P-type heavily doped region 153, the fifth N-type heavily doped region 164, and the sixth P-type heavily doped region 155 are arranged sequentially from left to right; the first P-type heavily doped region 150, the second N-type heavily doped region 161, the third P-type heavily doped region 152, the fourth N-type heavily doped region 163, the fifth P-type heavily doped region 154, and the sixth N-type heavily doped region 165 are arranged sequentially from left to right;

[0071] The second N-type heavily doped region 161 and the fifth P-type heavily doped region 154 are connected to the first port; the first P-type heavily doped region 150 and the fourth N-type heavily doped region 163 are connected to the second port; the third P-type heavily doped region 152 and the sixth N-type heavily doped region 165 are connected to the third port; the first N-type heavily doped region 160, the second P-type heavily doped region 151, and the third N-type heavily doped region 162 are directly connected through a first metal connection; the fourth P-type heavily doped region 153, the fifth N-type heavily doped region 164, and the sixth P-type heavily doped region 155 are directly connected through a second metal connection.

[0072] Shallow trench isolation is provided between the first N-type heavily doped region 160 and the first P-type heavily doped region 150, between the second P-type heavily doped region 151 and the second N-type heavily doped region 161, between the third N-type heavily doped region 162 and the third P-type heavily doped region 152, between the fourth P-type heavily doped region 153 and the fourth N-type heavily doped region 163, between the fifth N-type heavily doped region 164 and the fifth P-type heavily doped region 154, and between the sixth P-type heavily doped region 155 and the sixth N-type heavily doped region 165; shallow trench isolation is provided between the first P-type heavily doped region 150 and the second N-type heavily doped region 161, between the second N-type heavily doped region 161 and the third P-type heavily doped region 152, and between the third Shallow trench isolation is provided between the P-type heavily doped region 152 and the fourth N-type heavily doped region 163, between the fourth N-type heavily doped region 163 and the fifth P-type heavily doped region 154, and between the fifth P-type heavily doped region 154 and the sixth N-type heavily doped region 165; shallow trench isolation is provided between the first N-type heavily doped region 160 and the second P-type heavily doped region 151, between the second P-type heavily doped region 151 and the third N-type heavily doped region 162, between the third N-type heavily doped region 162 and the fourth P-type heavily doped region 153, between the fourth P-type heavily doped region 153 and the fifth P-type heavily doped region 154, and between the fifth P-type heavily doped region 154 and the sixth N-type heavily doped region 165.

[0073] From the perspective of device structure:

[0074] The device of claim 2 includes six diode paths, namely: diode path 1, which is formed by P-type heavily doped region 150, N-well 140, and N-type heavily doped region 160, from the third port to the first metal interconnect; diode path 2, which is formed by P-type heavily doped region 151, P-well 121, and N-type heavily doped region 161, from the first metal interconnect to the second port; diode path 3, which is formed by P-type heavily doped region 152, N-well 140, and N-type heavily doped region 162, from the first port to the first metal interconnect; diode path 4, which is formed by P-type heavily doped region 153, N-well 141, and N-type heavily doped region 163, from the second metal interconnect to the third port; diode path 5, which is formed by P-type heavily doped region 154, N-well 142, and N-type heavily doped region 164, from the second port to the second metal interconnect; and diode path 6, which is formed by P-type heavily doped region 155, N-well 143, and N-type heavily doped region 165, from the second metal interconnect to the first port.

[0075] The device of claim 2 comprises five SCR paths, namely: SCR path 1, consisting of a P-type heavily doped region 150, an N-well 140, a P-well 121, and an N-type heavily doped region 161, from the third port to the second port; SCR path 2, consisting of a P-type heavily doped region 152, an N-well 140, a P-well 121, and an N-type heavily doped region 161, from the first port to the second port; and SCR path 3, consisting of a P-type heavily doped region 154, an N-well 142, a P-well 120, and an N-type heavily doped region 161, from the third port to the second port. SCR path 3, consisting of well 141 and N-type heavily doped region 163, from the second port to the third port; SCR path 4, consisting of P-type heavily doped region 154, N-well 142, P-well 120, N-well 143, and N-type heavily doped region 165, from the second port to the first port; SCR path 5, consisting of P-type heavily doped region 152, N-well 140, P-well 120, N-well 141, and N-type heavily doped region 163, from the first port to the third port.

[0076] Example 3 provides an example of using the three-port compact low-capacitance DCSCR device described in claim 2 to provide ESD protection for I / O ports and VDD and VSS. In this example, the device described in claim 2 is connected to the actual I / O ports and the VSS and VDD terminals as follows: Terminal 1 port of the device is connected to the VSS of the IC, Terminal 2 port is connected to the I / O of the IC, and Terminal 3 port is connected to the VDD of the IC, as shown below. Figure 13 As shown.

[0077] In terms of working principle: When a combined ND and NS ESD occurs, the device uses diode path 1, diode path 2, and SCR path 1 for ESD protection; when a combined NS and NS ESD occurs, the device uses diode path 3, diode path 2, and SCR path 2 for ESD protection; when a combined PD and SD ESD occurs, the device uses diode path 5, diode path 4, and SCR path 3 for ESD protection; when a combined PS and DS ESD occurs, the device uses the protection paths of both ND and PS modes for ESD protection.

[0078] Example 4 provides another example of using the three-port compact low-capacitance DCSCR device described in claim 1 to provide ESD protection for I / O ports and VDD and VSS. In this example, the device described in claim 1 is connected to the actual I / O ports, VSS, and VDD ports as follows: Terminal 1 is connected to the IC's VDD, Terminal 2 is connected to the IC's I / O, and Terminal 3 is connected to the IC's VSS. Figure 14 As shown.

[0079] In terms of working principle: The obvious difference between Example 4 and Example 3 is that the way the device is connected to the IC has been changed.

[0080] Compared to Example 3, the main change in the working principle of this example is:

[0081] When a combined ND ESD occurs, the device uses diode path 3, diode path 2, and SCR path 2 for ESD protection; when a combined NS ESD occurs, the device uses diode path 1, diode path 2, and SCR path 1 for ESD protection; when a combined PD ESD occurs, the device uses diode path 5, diode path 6, and SCR path 4 for ESD protection; when a combined PS ESD occurs, the device uses diode path 5, diode path 4, and SCR path 3 for ESD protection; when a combined DS ESD occurs, the device uses diode path 3, diode path 2, diode path 5, diode path 4, and SCR path 5 for ESD protection; when a combined SD ESD occurs, the device uses the protection paths in both ND and PS modes for ESD protection.

[0082] Similarly, in embodiment 4, a protection method based on a single SCR path is adopted in the protection path of DS combined ESD, which improves the protection capability of DS mode. When using the device described in claim 2 to protect the IC chip, embodiments 3 and 4 can be used on different I / Os respectively.

[0083] The above examples are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described with reference to preferred examples, those skilled in the art should understand that any feature disclosed in this specification, unless specifically stated otherwise, can be replaced by other equivalent or similar alternative features. All features, or steps in all methods or processes disclosed, except for mutually exclusive features and / or steps, can be combined in any way without departing from the spirit and scope of the technical solutions of the present invention, and should all be covered within the scope of the claims of the present invention.

Claims

1. A compact, low-capacitance SCR device, characterized in that: A P-type silicon substrate, wherein a first P-type well region, a second P-type well region, a first deep N-type well region, a first N-type well region, a second N-type well region, a third N-type well region, and a fourth N-type well region are formed on the P-type silicon substrate; the first P-type well region is completely surrounded by the first N-type well region; the first P-type well region is isolated from the P-type silicon substrate below by the first deep N-type well region; the first N-type well region, the second N-type well region, the third N-type well region, and the fourth N-type well region are all completely surrounded by the second P-type well region; the first N-type well region, the second N-type well region, the third N-type well region, and the fourth N-type well region are arranged sequentially from left to right; Within a first N-type well region to the left of the first P-type well region, a first heavily doped N-type region and a first heavily doped P-type region are arranged sequentially from left to right; within the first P-type well region, a second heavily doped N-type region, a second heavily doped P-type region, and a third heavily doped N-type region are arranged sequentially from left to right; within a first N-type well region to the right of the first P-type well region, a third heavily doped P-type region and a fourth heavily doped N-type region are arranged sequentially from left to right; within the second N-type well region, a fourth heavily doped P-type region and a fifth heavily doped N-type region are arranged sequentially from left to right; within the third N-type well region, a fifth heavily doped P-type region, a sixth heavily doped N-type region, and a sixth heavily doped P-type region are arranged sequentially from left to right; within the fourth N-type well region, a seventh heavily doped N-type region and a seventh heavily doped P-type region are arranged sequentially from left to right. The second, third, fifth, and sixth heavily doped N-type regions are connected to the first port; the first and fifth heavily doped P-type regions are connected to the second port; the third and seventh heavily doped P-type regions are connected to the third port; the first, second, and third heavily doped N-type regions are directly connected via a first metal interconnect; and the fourth, sixth, and seventh heavily doped P-type regions are directly connected via a second metal interconnect. Shallow trench isolation is provided between the first N-type heavily doped region and the first P-type heavily doped region, between the first P-type heavily doped region and the second N-type heavily doped region, between the second N-type heavily doped region and the second P-type heavily doped region, between the second P-type heavily doped region and the third N-type heavily doped region, between the third N-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the fourth N-type heavily doped region, between the fourth N-type heavily doped region and the fourth P-type heavily doped region, between the fourth P-type heavily doped region and the fifth N-type heavily doped region, between the fifth N-type heavily doped region and the fifth P-type heavily doped region, between the fifth P-type heavily doped region and the sixth N-type heavily doped region, between the sixth N-type heavily doped region and the sixth P-type heavily doped region, between the sixth P-type heavily doped region and the seventh N-type heavily doped region, and between the seventh N-type heavily doped region and the seventh P-type heavily doped region.

2. An SCR device optimized from the device described in claim 1, characterized in that: A P-type silicon substrate, wherein a first P-type well region, a second P-type well region, a first deep N-type well region, a first N-type well region, a second N-type well region, a third N-type well region, and a fourth N-type well region are formed on the P-type silicon substrate; the first P-type well region is completely surrounded by the first N-type well region; the first P-type well region is isolated from the P-type silicon substrate through the first deep N-type well region; the first N-type well region, the second N-type well region, the third N-type well region, and the fourth N-type well region are all completely surrounded by the second P-type well region; the first N-type well region, the second N-type well region, the third N-type well region, and the fourth N-type well region are arranged sequentially from left to right; Within the first N-type well region to the left of the first P-type well region, a first heavily doped N-type region and a first heavily doped P-type region are sequentially arranged from bottom to top; within the first P-type well region, a second heavily doped P-type region and a second heavily doped N-type region are sequentially arranged from bottom to top; within the first N-type well region to the right of the first P-type well region, a third heavily doped N-type region and a third heavily doped P-type region are sequentially arranged from bottom to top; within the second N-type well region, a fourth heavily doped P-type region and a fourth heavily doped N-type region are sequentially arranged from bottom to top; within the third N-type well region, a third heavily doped N-type region and a third heavily doped P-type region are sequentially arranged from bottom to top; within the third N-type well region, a third heavily doped P-type region and a fourth heavily doped N-type region are sequentially arranged from bottom to top; within the third N-type well region, a third heavily doped P-type region and a third heavily doped P-type region are sequentially arranged from bottom to top; There is a fifth N-type heavily doped region and a fifth P-type heavily doped region; the fourth N-type well region has a sixth P-type heavily doped region and a sixth N-type heavily doped region arranged sequentially from bottom to top; the first N-type heavily doped region, the second P-type heavily doped region, the third N-type heavily doped region, the fourth P-type heavily doped region, the fifth N-type heavily doped region, and the sixth P-type heavily doped region are arranged sequentially from left to right; the first P-type heavily doped region, the second N-type heavily doped region, the third P-type heavily doped region, the fourth N-type heavily doped region, the fifth P-type heavily doped region, and the sixth N-type heavily doped region are arranged sequentially from left to right; The second N-type heavily doped region and the fifth P-type heavily doped region are connected to the first port; the first P-type heavily doped region and the fourth N-type heavily doped region are connected to the second port; the third P-type heavily doped region and the sixth N-type heavily doped region are connected to the third port; the first N-type heavily doped region, the second P-type heavily doped region, and the third N-type heavily doped region are directly connected by a first metal interconnect; the fourth P-type heavily doped region, the fifth N-type heavily doped region, and the sixth P-type heavily doped region are directly connected by a second metal interconnect. Shallow trench isolation is provided between the first N-type heavily doped region and the first P-type heavily doped region, between the second P-type heavily doped region and the second N-type heavily doped region, between the third N-type heavily doped region and the third P-type heavily doped region, between the fourth P-type heavily doped region and the fourth N-type heavily doped region, between the fifth N-type heavily doped region and the fifth P-type heavily doped region, and between the sixth P-type heavily doped region and the sixth N-type heavily doped region; shallow trench isolation is provided between the first P-type heavily doped region and the second N-type heavily doped region, between the second N-type heavily doped region and the third P-type heavily doped region, and between the third Shallow trench isolation is provided between the P-type heavily doped region and the fourth N-type heavily doped region, between the fourth N-type heavily doped region and the fifth P-type heavily doped region, and between the fifth P-type heavily doped region and the sixth N-type heavily doped region; shallow trench isolation is also provided between the first N-type heavily doped region and the second P-type heavily doped region, between the second P-type heavily doped region and the third N-type heavily doped region, between the third N-type heavily doped region and the fourth P-type heavily doped region, between the fourth P-type heavily doped region and the fifth P-type heavily doped region, and between the fifth P-type heavily doped region and the sixth N-type heavily doped region.

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