High electron mobility transistor having a stepped compound layer at the drain

Abstract

This invention discloses a high electron mobility transistor with a stepped compound layer at the drain, comprising a first III-V compound layer, a second III-V compound layer disposed on the first III-V compound layer, the composition of the second III-V compound layer being different from that of the first III-V compound layer, a source electrode, a gate electrode, and a drain electrode disposed on the second III-V compound layer, wherein the gate electrode is disposed between the source electrode and the drain electrode, and a first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer, wherein the first P-type III-V compound layer is stepped.

Description

Technical Field

[0001] This invention relates to a high electron mobility transistor having a ladder-like compound layer. Background Technology

[0002] III-V semiconductor compounds, due to their semiconductor properties, can be used to form many types of integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). In HEMTs, two semiconductor materials with different band gaps are combined at a junction to form a heterojunction, providing a channel for charge carriers. In recent years, gallium nitride (GaN) series materials have become suitable for high-power and high-frequency products due to their wide band gap and high saturation velocity. GaN series HEMTs generate a two-dimensional electron gas (2DEG) through the piezoelectric effect of the material itself. Compared to traditional transistors, HEMTs have higher electron velocity and density, thus increasing switching speed.

[0003] However, trapped electrons are generated during the operation of high electron mobility transistors, which affect the performance of high electron mobility transistors. Summary of the Invention

[0004] In view of this, the present invention provides a high electron mobility transistor with a stepped compound layer at the drain, which can remove trapped electrons without increasing the on-resistance.

[0005] According to a first preferred embodiment of the present invention, a high electron mobility transistor with a stepped compound layer at its drain includes a first III-V compound layer, a second III-V compound layer disposed on the first III-V compound layer, the composition of the second III-V compound layer being different from that of the first III-V compound layer, a source electrode, a gate electrode, and a drain electrode disposed on the second III-V compound layer, wherein the gate electrode is disposed between the source electrode and the drain electrode, and a first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer, wherein the first P-type III-V compound layer is stepped.

[0006] According to a second preferred embodiment of the present invention, a high electron mobility transistor with a stepped compound layer at its drain includes a first III-V compound layer, a second III-V compound layer disposed on the first III-V compound layer, the composition of the second III-V compound layer being different from that of the first III-V compound layer, a source electrode, a gate electrode, and a drain electrode disposed on the second III-V compound layer, wherein the gate electrode is disposed between the source electrode and the drain electrode, the drain electrode includes a first portion and a second portion, the first portion and the second portion being made of different materials, and a first P-type III-V compound layer disposed between the drain electrode and the second III-V compound layer, wherein the first P-type III-V compound layer is stepped, and a Schottky contact is formed between the first portion and the first P-type III-V compound layer.

[0007] According to another preferred embodiment of the present invention, a method for fabricating a high electron mobility transistor with a stepped compound layer at the drain includes providing a III-V compound layer, then forming a P-type III-V compound layer to cover the III-V compound layer, then truncating the P-type III-V compound layer to form a first P-type III-V compound layer and a second P-type III-V compound layer, then patterning the first P-type III-V compound layer such that the first P-type III-V compound layer is stepped, and finally, after patterning the first P-type III-V compound layer, forming a source electrode, a gate electrode and a drain electrode, wherein the gate electrode is located on the second P-type III-V compound layer and the drain electrode is located on the first P-type III-V compound layer.

[0008] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0009] Figures 1 to 6 A schematic diagram illustrating a method for fabricating a high electron mobility transistor with a stepped compound layer at the drain, as shown in the first preferred embodiment of the present invention;

[0010] Figure 7 A schematic diagram illustrating a method for fabricating a high electron mobility transistor with a stepped compound layer at the drain, as shown in the second preferred embodiment of the present invention;

[0011] Figure 8 for Figure 6 A schematic diagram of a variant of a high electron mobility transistor;

[0012] Figure 9 for Figure 7 A schematic diagram of a variant of a high electron mobility transistor;

[0013] Figure 10 This is a schematic diagram of a high electron mobility transistor illustrated as an example of the present invention.

[0014] Explanation of main component symbols

[0015] 10: Base

[0016] 12: First III-V compound layer

[0017] 14: Second III-V compound layer

[0018] 16: Layer of P-type III-V compounds

[0019] 16a: First p-type III-V compound layer

[0020] 16b: Second p-type III-V compound layer

[0021] 16c: Third p-type III-V compound layer

[0022] 16': P-type III-V compound layer

[0023] 18a: First patterned photoresist

[0024] 18b: Second patterned photoresist

[0025] 20a: Depression

[0026] 20b: Depression

[0027] 22: Insulation layer

[0028] 24: Vertical sidewall

[0029] 100a: High electron mobility transistor with a step-like compound layer at the drain.

[0030] 100b: High electron mobility transistor with a stepped compound layer at the drain.

[0031] 200a: High electron mobility transistor with a step-like compound layer at the drain.

[0032] 200b: High electron mobility transistor with a stepped compound layer at the drain.

[0033] 300: High electron mobility transistor

[0034] D: Drain electrode

[0035] D1: Part 1

[0036] D2: Part Two

[0037] G: Gate electrode

[0038] L: Axis of symmetry

[0039] S: Source electrode

[0040] S1: Part One

[0041] S2: Part Two Detailed Implementation

[0042] Figures 1 to 6 A method for fabricating a high electron mobility transistor with a stepped compound layer at the drain electrode, as illustrated in a first preferred embodiment of the present invention.

[0043] like Figure 1 As shown, a substrate 10 is first provided, which may include a silicon substrate and a buffer layer. Then, a first III-V compound layer 12, a second III-V compound layer 14, and a P-type III-V compound layer 16 are sequentially formed to cover the substrate 10. The P-type III-V compound layer 16 covers and contacts the second III-V compound layer 14, the second III-V compound layer 14 covers and contacts the first III-V compound layer 12, and the first III-V compound layer 12 covers and contacts the buffer layer in the substrate 10. The buffer layer can be a III-V compound, such as aluminum gallium nitride (GaN). The P-type III-V compound layer 16 is preferably P-type GaN, the second III-V compound layer 14 is preferably aluminum gallium nitride, and the first III-V compound layer 12 is preferably GaN. However, this is not the only option. Depending on the specific product requirements, the buffer layer, the P-type III-V compound layer 16, the second III-V compound layer 14, and the first III-V compound layer 12 can each be independently selected from III-V compounds such as aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or aluminum nitride.

[0044] like Figure 2 As shown, the P-type III-V compound layer 16 is truncated to form a first P-type III-V compound layer 16a and a second P-type III-V compound layer 16b. According to a preferred embodiment of the present invention, the P-type III-V compound layer 16 can be truncated using an etching process.

[0045] Next, the first P-type III-V compound layer 16a is patterned so that it becomes stair-like, as detailed below. Figure 3As shown, a first patterned photoresist 18a is formed to cover the second P-type III-V compound layer 16b, the second III-V compound layer 14, and a portion of the first P-type III-V compound layer 16a, with the first P-type III-V compound layer 16a, which is farther from the second P-type III-V compound layer 16b, exposed by the first patterned photoresist 18a. The exposed first P-type III-V compound layer 16a is then etched to form a recess 20a on the surface of the first P-type III-V compound layer 16a. As... Figure 4 As shown, after removing the first patterned photoresist 18a, a second patterned photoresist 18b is formed, covering the second P-type III-V compound layer 16b, the second III-V compound layer 14, and a portion of the first P-type III-V compound layer 16a. Only a portion of the recess 20a is exposed by the second patterned photoresist 18b. The exposed recess 20a is then etched to form another recess 20b. The vertical distance between the recess 20b and the second III-V compound layer 14 is smaller than the vertical distance between the recess 20a and the second III-V compound layer 14. The above steps of forming recesses 20a / 20b by etching can be repeated multiple times as needed, ultimately resulting in a stepped shape for the first P-type III-V compound layer 16a. Notably, the stepped shape descends in a direction away from the second P-type III-V compound layer 16b.

[0046] like Figure 5 As shown, after removing the second patterned photoresist 18a, a gate electrode G contact is formed and covered with a second P-type III-V compound layer 16b. The gate electrode G and the second P-type III-V compound layer 16b form a Schottky contact; for example, the gate electrode G may contain nickel or gold. Figure 6As shown, a drain electrode D and a source electrode S are simultaneously formed. The drain electrode D covers and contacts a first P-type III-V compound layer 16a and a second III-V compound layer 14. The source electrode S covers and contacts the second III-V compound layer 14. The drain electrode D is located on one side of the gate electrode G, and the source electrode S is located on the other side of the gate electrode G opposite to the drain electrode D. Furthermore, the drain electrode D and the first P-type III-V compound layer 16a, as well as the drain electrode D and the second III-V compound layer 14, are ohmic contacts, and the source electrode S and the second III-V compound layer 14 are also ohmic contacts. The drain electrode D and the source electrode S may comprise titanium, aluminum, nickel, gold, or titanium nitride. For example, the drain electrode D and the source electrode S may be a composite material sequentially stacked from titanium, aluminum, nickel, and gold, or a composite material sequentially stacked from titanium, aluminum, titanium, and titanium nitride. After forming the drain electrode D and the source electrode S, an insulating layer 22, such as silicon oxide, is formed to cover and contact the drain electrode D, the source electrode S, the gate electrode G, and fill the space between the drain electrode D, the source electrode S, and the gate electrode G. Thus, the high electron mobility transistor 100a with a stepped compound layer at its drain according to the present invention is completed.

[0047] Figure 7 This illustration depicts a method for fabricating a high electron mobility transistor with a stepped compound layer at the drain, according to a second preferred embodiment of the present invention. Components having the same location and function will use the component designations from the first preferred embodiment. The difference between the second preferred embodiment and the first preferred embodiment is that the drain electrode D and the first P-type III-V compound layer 16a in the second preferred embodiment simultaneously have a Schottky contact and an ohmic contact; all other parts are the same as in the first preferred embodiment. Specifically, upon completion... Figures 1 to 4 After the steps, such as Figure 7 As shown, the second patterned photoresist 18b is first removed, and then a first portion D1 of the drain electrode D and a gate electrode G are simultaneously formed. The first portion D1 of the drain electrode D covers and contacts the upper surface of the first P-type III-V compound layer 16a, and a Schottky contact is formed between the first portion D1 of the drain electrode D and the first P-type III-V compound layer 16a. Similarly, a Schottky contact is formed between the gate electrode G and the second P-type III-V compound layer 16b.

[0048] Then, a second portion D2 of the drain electrode D and a source electrode S are formed. The second portion D2 of the drain electrode D covers and contacts the first portion D1 of the drain electrode D, contacts the end of the second III-V compound layer 14 and the first P-type III-V compound layer 16a, and an ohmic contact is formed between the second portion D2 of the drain electrode D and the first P-type III-V compound layer 16a. Next, an insulating layer 22, such as silicon oxide, is formed, covering and contacting the drain electrode D, the source electrode S, the gate electrode G, and filling the space between the drain electrode D, the source electrode S, and the gate electrode G. Thus, the high electron mobility transistor 200a with a stepped compound layer in the drain of the present invention is completed.

[0049] Figure 6 A high electron mobility transistor with a stepped compound layer at the drain, fabricated according to the steps of the first preferred embodiment of the present invention, wherein components having the same location and function will use the component designations in the first preferred embodiment, such as... Figure 6 As shown, a high electron mobility transistor 100a with a stepped compound layer at the drain includes a first III-V compound layer 12, a second III-V compound layer 14 disposed on the first III-V compound layer 12, the composition of the second III-V compound layer 14 being different from that of the first III-V compound layer 12, a source electrode S, a gate electrode G, and a drain electrode D disposed on the second III-V compound layer 14, wherein the gate electrode G is disposed between the source electrode S and the drain electrode D, and a first P-type III-V compound layer 16a is disposed between the drain electrode D and the second III-V compound layer 14, wherein the first P-type III-V compound layer 16a is stepped, the steps descending in a direction away from the gate electrode G. Additionally, the drain electrode D contacts the first P-type III-V compound layer 16a and the second III-V compound layer 14. Specifically, the first P-type III-V compound layer 16a is a stepped structure composed of multiple steps, with the lowest step including a vertical sidewall 24. The drain electrode D contacts the vertical sidewall 24, and the drain electrode D and the first P-type III-V compound layer 16a form an ohmic contact. Furthermore, a second P-type III-V compound layer 16b is disposed between the gate electrode G and the second III-V compound layer 14. In this embodiment, the drain electrode D is farther from the gate electrode G, and the source electrode S is closer to the gate electrode G. However, this is not a limitation; depending on different requirements, the distance between the drain electrode D and the gate electrode G can be the same as the distance between the source electrode S and the gate electrode G.

[0050] Figure 8 for Figure 6 Variations of high electron mobility transistors, in which components with the same location and function will use Figure 6 The component labels in the text. Figure 8 The high electron mobility transistor 100b with a stepped compound layer at its drain also includes a third P-type III-V compound layer 16c disposed between the source electrode S and the second III-V compound layer 14. The gate electrode G has a symmetry axis L perpendicular to the upper surface of the second III-V compound layer 14. Based on the symmetry axis L, the source electrode S and the drain electrode D are mirror-symmetric, and the third P-type III-V compound layer 16c and the first P-type III-V compound layer 16b are mirror-symmetric. That is, both the third P-type III-V compound layer 16c and the first P-type III-V compound layer 16a are stepped. The source electrode S covers and contacts the third P-type III-V compound layer 16c. Since the distance between the source electrode S and the gate electrode G is the same as the distance between the drain electrode D and the gate electrode G, the drain electrode D and the source electrode S of the high electron mobility transistor 100b in this embodiment can be interchanged during operation.

[0051] Figure 7 A high electron mobility transistor with a stepped compound layer at its drain, fabricated according to the steps of the second preferred embodiment of the present invention, wherein components having the same location and function will use the component designations in the second preferred embodiment. For example... Figure 7As shown, a high electron mobility transistor 200a with a stepped compound layer at the drain includes a first III-V compound layer 12, a second III-V compound layer 14 disposed on the first III-V compound layer 12, the composition of the second III-V compound layer 14 being different from that of the first III-V compound layer 12, a source electrode S, a gate electrode G, and a drain electrode D disposed on the second III-V compound layer 14, wherein the gate electrode G is disposed between the source electrode S and the drain electrode D, and the drain electrode D includes a first portion The first part D1 and the second part D2 are made of different materials. A first P-type III-V compound layer 16a is disposed between the drain electrode D and the second III-V compound layer 14, and a second P-type III-V compound layer 16b is disposed between the gate electrode G and the second III-V compound layer 14. The first P-type III-V compound layer 16a is stepped, descending away from the gate electrode G. A Schottky contact is formed between the first part D1 and the first P-type III-V compound layer 14. The first part D1 is located between the second part D2 and the first P-type III-V compound layer 16a. Furthermore, the stepped shape of the first P-type III-V compound layer 16a is composed of multiple steps, the lowest step of which includes a vertical sidewall 24. The second part D2 contacts the vertical sidewall 24 and the second III-V compound layer 14, and an ohmic contact is formed between the second part D2 and the vertical sidewall 24. In this embodiment, the drain electrode D is farther from the gate electrode G, and the source electrode S is closer to the gate electrode G. However, this is not the only option. Depending on the requirements, the distance between the drain electrode D and the gate electrode G can be the same as the distance between the source electrode S and the gate electrode G.

[0052] Figure 9 for Figure 7 Variations of high electron mobility transistors, in which components with the same location and function will use Figure 7 The component labels in the text. Figure 9The high electron mobility transistor 200b with a stepped compound layer at its drain further includes a third P-type III-V compound layer 16c disposed between the source electrode S and the second III-V compound layer 14. The gate electrode G has a symmetry axis L perpendicular to the upper surface of the second III-V compound layer 14. Based on the symmetry axis L, the source electrode S and the drain electrode D are mirror symmetric. Therefore, the source electrode S also has a first portion S1 and a second portion S2. The third P-type III-V compound layer 16c and the first P-type III-V compound layer 16a are mirror symmetric, that is, both the third P-type III-V compound layer 16c and the first P-type III-V compound layer 16a are stepped. Because they are mirror symmetric, the drain electrode D and the source electrode S of the high electron mobility transistor 200b in this embodiment can be interchanged during operation.

[0053] Figure 10 The high electron mobility transistor illustrated in an exemplary embodiment of the present invention, wherein components having the same location and function will use the component designations in the first preferred embodiment.

[0054] Compared to Figures 6-9 High electron mobility transistors in Figure 10 The difference in the high electron mobility transistor 300 is that the first p-type III-V compound layer 16' does not have a stepped profile. The first p-type III-V compound layer 16' is used to remove trapped electrons in the first III-V compound layer 12 and the second III-V compound layer 14. However, the first p-type III-V compound layer 16' reduces the density of the two-dimensional electron gas (2DEG) below the first p-type III-V compound layer 16', thus increasing the on-resistance of the high electron mobility transistor 300.

[0055] Will Figures 6-9 The first p-type III-V compound layer 16a and the ladder-like first p-type III-V compound layer were used. Figure 10 Compared to using a non-stepped first P-type III-V compound layer 16', the density of the two-dimensional electron gas below the stepped first P-type III-V compound layer 16a is higher than that below the non-stepped first P-type III-V compound layer 16'. Therefore, using the stepped first P-type III-V compound layer 16a can not only remove trapped electrons, but also reduce the on-resistance.

[0056] also, Figure 7 and Figure 9 The high electron mobility transistor with a drain having a stepped compound layer additionally uses a Schottky contact, compared to... Figure 6 and Figure 8The drain electrode D only uses an ohmic contact; the additional use of a Schottky contact can improve the breakdown voltage of a high electron mobility transistor.

[0057] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A high electron mobility transistor with a step-like compound layer at its drain, comprising: First III-V compound layer; A second III-V compound layer is disposed on the first III-V compound layer, and the composition of the second III-V compound layer is different from that of the first III-V compound layer. A source electrode, a gate electrode, and a drain electrode are disposed on the second III-V compound layer, wherein the gate electrode is disposed between the source electrode and the drain electrode; and A first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer, wherein the first P-type III-V compound layer is stair-like, and the stair shape descends in a direction away from the gate electrode.

2. The high electron mobility transistor with a stepped compound layer as claimed in claim 1, wherein the drain electrode contacts the first P-type III-V compound layer and the drain electrode contacts the second III-V compound layer.

3. The high electron mobility transistor with a drain having a stepped compound layer as claimed in claim 2, wherein the first P-type III-V compound layer is stepped by a plurality of steps, the lowest step of which includes a vertical sidewall, and the drain electrode contacts the vertical sidewall.

4. The high electron mobility transistor with a stepped compound layer as claimed in claim 1, wherein the drain electrode and the first P-type III-V compound layer are in an ohmic contact.

5. The high electron mobility transistor with a stepped compound layer at the drain as claimed in claim 1, further comprising a second P-type III-V compound layer disposed between the gate electrode and the second III-V compound layer.

6. The high electron mobility transistor with a stepped compound layer at the drain as claimed in claim 1, further comprising a third P-type III-V compound layer disposed between the source electrode and the second III-V compound layer, wherein the gate electrode has an axis of symmetry perpendicular to the upper surface of the second III-V compound layer, and based on the axis of symmetry, the source electrode and the drain electrode are mirror-symmetric, and the third P-type III-V compound layer and the first P-type III-V compound layer are mirror-symmetric.

7. A high electron mobility transistor with a drain having a ladder-like compound layer, comprising: First III-V compound layer; A second III-V compound layer is disposed on the first III-V compound layer, and the composition of the second III-V compound layer is different from that of the first III-V compound layer. A source electrode, a gate electrode, and a drain electrode are disposed on the second III-V compound layer, wherein the gate electrode is disposed between the source electrode and the drain electrode, and the drain electrode includes a first portion and a second portion, the first portion and the second portion being made of different materials; and A first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer, wherein the first P-type III-V compound layer is stair-like, the first portion and the first P-type III-V compound layer are in a Schottky contact, and the second portion and the first P-type III-V compound layer are in an ohmic contact.

8. The high electron mobility transistor with a stepped compound layer at the drain as claimed in claim 7, wherein the first portion is located between the second portion and the first P-type III-V compound layer.

9. The high electron mobility transistor with a drain having a stepped compound layer as claimed in claim 7, wherein the first P-type III-V compound layer is stepped by a plurality of steps, the lowest step of the plurality of steps includes a vertical sidewall, the second portion contacts the vertical sidewall and the second portion contacts the second III-V compound layer.

10. The high electron mobility transistor with a stepped compound layer at the drain as claimed in claim 9, wherein the second portion and the vertical sidewall are in an ohmic contact.

11. The high electron mobility transistor with a stepped compound layer at the drain as claimed in claim 7, further comprising a second P-type III-V compound layer disposed between the gate electrode and the second III-V compound layer.

12. The high electron mobility transistor with a stepped compound layer at the drain as claimed in claim 7, further comprising a third P-type III-V compound layer disposed between the source electrode and the second III-V compound layer, wherein the gate electrode has an axis of symmetry perpendicular to the upper surface of the second III-V compound layer, and based on the axis of symmetry, the source electrode and the drain electrode are mirror-symmetric, and the third P-type III-V compound layer and the first P-type III-V compound layer are mirror-symmetric.

13. The high electron mobility transistor of claim 8, wherein the drain has a stepped compound layer, wherein the stepped layer descends in a direction away from the gate electrode.

14. A method for fabricating a high electron mobility transistor with a step-like compound layer at the drain, comprising: Provide a layer of III-V compound; A layer of P-type III-V compound is formed to cover the III-V compound layer; The P-type III-V compound layer is truncated to form a first P-type III-V compound layer and a second P-type III-V compound layer; Patterning the first P-type III-V compound layer to make it stair-like; and After patterning the first P-type III-V compound layer, a source electrode, a gate electrode, and a drain electrode are formed, wherein the gate electrode is located on the second P-type III-V compound layer, and the drain electrode is located on the first P-type III-V compound layer, wherein the method for fabricating the drain electrode includes: The first portion forming the drain electrode covers and contacts the first P-type III-V compound layer; The second portion forming the drain electrode covers and contacts the first portion and the first P-type III-V compound layer, wherein the first portion and the first P-type III-V compound layer are in a Schottky contact, and the second portion and the first P-type III-V compound layer are in an ohmic contact.

15. The method for fabricating a high electron mobility crystal with a step-like compound layer at the drain electrode as described in claim 14, wherein the second portion of the drain electrode contacts the III-V compound layer.

16. The method for fabricating a high electron mobility crystal with a drain electrode having a stepped compound layer as described in claim 14, wherein the first p-type III-V compound layer is stepped by a plurality of steps, the lowest step of the plurality of steps includes a vertical sidewall, and the second portion of the drain electrode contacts the vertical sidewall.

17. The method for fabricating a high electron mobility crystal with a step-like compound layer at the drain electrode as described in claim 14, further comprising: The gate electrode is formed simultaneously with the first portion, wherein the gate electrode and the first portion are made of the same material.

18. The method for fabricating a high electron mobility crystal with a stepped compound layer at the drain as described in claim 14, wherein the stepped shape descends in a direction away from the gate electrode.

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