Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate; forming a gate dielectric material layer, a first barrier material layer on the gate dielectric material layer, the first barrier material layer being doped with first barrier ions; forming a gate material layer on the surface of the first barrier material layer using the first barrier material layer as a seed, the gate material layer being doped with dopant ions; etching the gate material layer, the first barrier material layer and the gate dielectric material layer to form a gate structure, the gate structure comprising a gate layer, a first barrier layer and a gate dielectric layer, the gate dielectric layer being formed by the gate dielectric material layer, the first barrier layer being formed by the first barrier material layer, and the gate layer being formed by the gate material layer, so as to obtain a gate structure with a higher target dopant ion concentration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Semiconductor devices based on polysilicon gates are currently the mainstream and are widely manufactured and used. As the critical dimensions of devices continue to shrink, it is necessary to perform a certain amount of ion doping on the polysilicon gate to reduce resistance, thereby reducing the parasitic depletion region of polysilicon and improving the overall performance of the device.

[0003] However, the potential drawbacks of high doping concentrations in polysilicon gates include:

[0004] 1) In the subsequent annealing process, dopant ions gradually diffuse to the gate surface, forming surface particles and causing gate morphology failure. To avoid gate morphology failure, the gate surface is cleaned to remove dopant ions. However, the concentration of dopant ions inside the gate decreases, making it impossible to obtain the desired highly doped gate.

[0005] 2) Dopant ions can diffuse to the gate oxide interface and form unstable bonds, which can lead to gate structure failure.

[0006] Therefore, under the existing process conditions, it is difficult to achieve the target concentration of dopant ions in the polysilicon gate. Summary of the Invention

[0007] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0008] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, including: a substrate; a gate structure located on the surface of the substrate, the gate structure including a gate dielectric layer, a first barrier layer located on the gate dielectric layer and a gate layer located on the first barrier layer, the first barrier layer being doped with first barrier ions and the gate layer being doped with dopant ions.

[0009] Optionally, the gate layer material may include polysilicon.

[0010] Optionally, the gate structure may further include a second barrier layer located on the surface of the gate layer, wherein the second barrier layer is doped with second barrier ions.

[0011] Optionally, the thickness of the first barrier layer ranges from 5 nm to 40 nm; the thickness of the second barrier layer ranges from 5 nm to 40 nm.

[0012] Optionally, the material of the first barrier layer includes polycrystalline silicon; the first barrier ion includes carbon ions; the material of the second barrier layer includes polycrystalline silicon; and the second barrier ion includes carbon ions.

[0013] Optionally, the concentration of carbon ions within the first barrier layer is less than or equal to 1E22 atom / cm³. 3 The carbon ion concentration within the second barrier layer is less than or equal to 1E22 atom / cm³. 3 .

[0014] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a gate dielectric material layer and a first barrier material layer on the substrate, wherein the first barrier material layer is doped with first barrier ions; using the first barrier material layer as a seed crystal, forming a gate material layer on the surface of the first barrier material layer, wherein the gate material layer is doped with dopant ions; etching the gate material layer, the first barrier material layer and the gate dielectric material layer to form a gate structure, wherein the gate structure includes a gate layer, a first barrier layer and a gate dielectric layer.

[0015] Optionally, the method for forming the first barrier material layer includes: forming an initial first barrier material layer having an amorphous structure on a substrate, wherein the initial first barrier material layer is doped with first barrier ions; and performing heat treatment on the initial first barrier material layer to form a polycrystalline structure, thereby forming the first barrier material layer.

[0016] Optionally, the initial first barrier material layer can be formed using a low-pressure chemical vapor deposition process.

[0017] Optionally, the first barrier ion includes carbon ions; the process parameters of the low-pressure chemical vapor deposition process include: the reaction gas includes C2H4 and SiH4, the reaction temperature range is 500℃ to 550℃, and the pressure range is 300mTorr to 1000mTorr.

[0018] Optional process parameters for heat treatment include a temperature range of 600°C to 800°C.

[0019] Optionally, the formation process of the first barrier material layer includes a low-pressure chemical vapor deposition process.

[0020] Optionally, the material of the first barrier layer includes polycrystalline silicon; the first barrier ions include carbon ions; the process parameters of the low-pressure chemical vapor deposition process include: the reaction gases include C2H4 and SiH4, the reaction temperature range is 580°C to 630°C, and the pressure range is 100 mTorr to 500 mTorr.

[0021] Optionally, the formation process of the gate material layer includes a low-pressure chemical vapor deposition process; the process parameters of the low-pressure chemical vapor deposition process include: the reaction gas includes SiHH4 and the dopant gas, and the dopant gas includes PH3 or BCl3.

[0022] Optionally, the gate structure further includes a second barrier layer, which is doped with second barrier ions and is located on the surface of the gate layer.

[0023] Optionally, the method for forming the second barrier layer further includes: after forming the gate material layer and before etching the gate material layer, the first barrier material layer and the gate dielectric material layer, forming a second barrier material layer on the gate material layer, the second barrier material layer having second barrier ions; the second barrier material layer being etched to form the second barrier layer.

[0024] Optionally, the process for forming the second barrier material layer includes low-pressure chemical vapor deposition.

[0025] Optionally, the material of the second barrier layer includes polycrystalline silicon; the second barrier ions include carbon ions.

[0026] Optionally, the method for forming the second barrier material layer includes: forming an initial second barrier material layer with an amorphous structure on a gate material layer, the initial second barrier material layer containing second barrier ions; and heat-treating the initial second barrier material layer to form a polycrystalline structure, thereby forming the second barrier material layer.

[0027] Optionally, the concentration of dopant ions within the gate material layer is less than or equal to 1E25 atom / cm³. 3 .

[0028] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0029] In the semiconductor structure formation method provided by the present invention, on the one hand, a first barrier layer is formed between the gate dielectric layer and the gate layer. The first barrier layer can block the diffusion of dopant ions in the gate layer to the gate dielectric layer, reducing the formation of interface states of dopant ions at the interface between the gate dielectric layer and the substrate, thus affecting device performance. At the same time, it can increase the concentration of dopant ions in the gate layer, avoiding the reduction of dopant ion concentration caused by the diffusion of dopant ions to the interface, which is beneficial to obtaining a gate structure with a higher target dopant ion concentration. On the other hand, using the first barrier material layer as a seed crystal, a gate material layer is formed on the surface of the first barrier material layer. The first barrier ions in the first barrier material layer can promote the initial nucleation of the gate material layer, which is beneficial to forming a gate material layer with small and uniform grain size, thereby improving the ability of the gate layer to withstand external voltage, increasing the number of device switching cycles, and extending the device lifetime.

[0030] Furthermore, the first blocking ion is a carbon ion, which can prevent the diffusion of dopant ions into the gate oxide layer. At the same time, the presence of carbon is conducive to the formation of polycrystalline silicon materials with small grain size and uniform particle size.

[0031] Furthermore, the formation of the first barrier material layer by forming an initial first barrier material layer with an amorphous structure and then heat-treating the initial first barrier material layer to form a polycrystalline structure can reduce the accumulation of first barrier ions near the polycrystalline grain boundaries of the first barrier material layer and improve the uniformity of the distribution of first barrier ions within the first barrier material layer.

[0032] Furthermore, the gate structure also includes a second barrier layer, which is doped with second barrier ions. The second barrier layer is located on the surface of the gate layer and is used to block the diffusion of dopant ions in the gate layer to the surface of the gate layer. This can increase the concentration of dopant ions in the gate layer and facilitate obtaining a gate structure with a higher target dopant ion concentration. Attached Figure Description

[0033] Figures 1 to 5 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0034] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial relationship and are not limited to whether there is direct contact.

[0035] As described in the background section, under existing process conditions, it is difficult to achieve the target dopant ion concentration in polysilicon gates.

[0036] To address the aforementioned problems, the present invention provides a semiconductor structure and its formation method. On one hand, a first barrier layer is formed between the gate dielectric layer and the gate layer. This first barrier layer can prevent the diffusion of dopant ions from the gate layer into the gate dielectric layer, reducing the formation of interface states at the gate dielectric layer-substrate interface and thus minimizing the impact on device performance. Simultaneously, it can increase the concentration of dopant ions within the gate layer, preventing a decrease in dopant ion concentration due to diffusion to the interface, thereby facilitating the acquisition of a gate structure with a higher target dopant ion concentration. On the other hand, using the first barrier material layer as a seed crystal, a gate material layer is formed on the surface of the first barrier material layer. The first barrier ions within the first barrier material layer can promote the initial nucleation of the gate material layer, facilitating the formation of a gate material layer with small and uniform grain size. This improves the gate layer's ability to withstand external voltages, increases the device's switching cycles, and extends its lifespan.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 1 to 5 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 1 Substrate 100 is provided.

[0040] In this embodiment, the substrate 100 is made of monocrystalline silicon; in other embodiments, the substrate may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanide, gallium arsenide, silicon-on-insulator, or germanium-on-insulator.

[0041] In this embodiment, the substrate 100 is a planar substrate. In other embodiments, the substrate may have a fin structure.

[0042] Please refer to Figure 2 A gate dielectric material layer 101 and a first barrier material layer 102 are formed on the substrate 100. The first barrier material layer 102 is doped with a first barrier ion A.

[0043] In this embodiment, the gate dielectric material layer 101 is used to form the gate dielectric layer, and the first barrier material layer 102 is used to form the first barrier layer.

[0044] In this embodiment, the material of the gate dielectric material layer 101 includes silicon oxide.

[0045] In this embodiment, the method for forming the first barrier material layer 102 includes: forming an initial first barrier material layer (not shown in the figure) with an amorphous structure on a substrate 100, wherein the initial first barrier material layer is doped with a first barrier ion A; and performing heat treatment on the initial first barrier material layer to form a polycrystalline structure, thereby forming the first barrier material layer 102.

[0046] In this embodiment, the formation process of the initial first barrier material layer includes a low-pressure chemical vapor deposition process.

[0047] In this embodiment, the process parameters for low-pressure chemical vapor deposition include: the reactant gases are C2H4 and SiH4, the reaction temperature range is 500°C to 550°C, and the pressure range is 300 mTorr to 1000 mTorr. The significance of selecting the reaction temperature range is that, under the reaction temperature conditions, the initial first barrier material layer formed is an amorphous structure.

[0048] The initial first barrier material layer is made of polycrystalline silicon. In this embodiment, the initial first barrier material layer is made of polycrystalline silicon.

[0049] In this embodiment, the heat treatment process parameters include a temperature range of 600°C to 800°C. Under these heat treatment conditions, amorphous silicon material can be transformed into polycrystalline silicon material.

[0050] In this embodiment, the first blocking ion A includes carbon ions. Specifically, carbon ions can prevent the diffusion of dopant ions into the gate oxide layer, and the presence of carbon ions is beneficial for forming polycrystalline silicon materials with small and uniform grain size.

[0051] In this embodiment, the thickness of the first barrier material layer 102 ranges from 5 nm to 40 nm.

[0052] In this embodiment, the concentration of carbon ions within the first barrier material layer 102 is less than or equal to 1E22 atom / cm³. 3 .

[0053] In this embodiment, the first barrier material layer 102 is formed by forming an initial first barrier material layer with an amorphous structure, and then heat-treating the initial first barrier material layer to form a polycrystalline structure. This reduces the accumulation of first barrier ions A near the polycrystalline grain boundaries of the first barrier material layer 102 and improves the uniformity of the distribution of first barrier ions A within the first barrier material layer 102.

[0054] In this embodiment, amorphous silicon doped with carbon ions is first formed, and then the amorphous silicon is heat-treated to crystallize the amorphous silicon material into polycrystalline silicon material. This can make the distribution of the first barrier ions in the first barrier material layer more uniform and improve the barrier effect of the first barrier ions.

[0055] In another embodiment, the first barrier material layer with a polycrystalline structure can be directly formed by changing the process temperature during the reaction.

[0056] In another embodiment, the formation process of the first barrier material layer includes a low-pressure chemical vapor deposition process. The material of the first barrier layer includes polycrystalline silicon.

[0057] In another embodiment, the first blocking ion includes a carbon ion.

[0058] In another embodiment, the process parameters of the low-pressure chemical vapor deposition process include: the reaction gases include C2H4 and SiH4, the reaction temperature range is 580°C to 630°C, and the pressure range is 100 mTorr to 500 mTorr.

[0059] The difference between this embodiment and the other embodiment is that the first barrier material layer, which directly forms a polycrystalline structure, allows the first barrier ions to accumulate more easily at the polycrystalline grain boundaries compared to this embodiment. In other words, the distribution uniformity of the first barrier ions within the first barrier material layer is slightly worse in the other embodiment.

[0060] Please refer to Figure 3Using the first barrier material layer 102 as a seed crystal, a gate material layer 103 is formed on the surface of the first barrier material layer 102, and the gate material layer 103 is doped with dopant ions B.

[0061] The gate material layer 103 is used to form the gate layer, and the dopant ions B are used to adjust the electrical performance of the formed gate structure. On one hand, the subsequently formed first barrier layer is located between the gate dielectric layer and the gate layer. The first barrier layer can prevent the diffusion of dopant ions in the gate layer to the gate dielectric layer, reduce the formation of interface states of dopant ions at the interface between the gate dielectric layer and the substrate, and thus reduce the impact on device performance. At the same time, it can increase the concentration of dopant ions in the gate layer, avoiding the reduction of dopant ion concentration caused by the diffusion of dopant ions to the interface, which is beneficial to obtaining a gate structure with a higher target dopant ion concentration. On the other hand, using the first barrier material layer 102 as a seed, the gate material layer 103 is formed on the surface of the first barrier material layer 102. The first barrier ions A in the first barrier material layer 102 can promote the initial nucleation of the gate material layer 103, which is beneficial to forming a gate material layer 103 with small and uniform grain size, thereby improving the ability of the gate layer to withstand external voltage, increasing the number of device switching cycles, and extending the device lifetime.

[0062] In this embodiment, the concentration of dopant ions B within the gate material layer 103 is less than or equal to 1E25 atom / cm³. 3 .

[0063] The dopant ion B includes either an N-type or a P-type conductive ion. In this embodiment, the dopant ion B is a phosphorus ion.

[0064] In this embodiment, the formation process of the gate material layer 103 includes a low-pressure chemical vapor deposition process.

[0065] Specifically, the material of the gate material layer 103 includes polysilicon.

[0066] In this embodiment, the process parameters for low-pressure chemical vapor deposition include: the reaction gas includes SiH4 and the dopant gas, which includes PH3 or BCl3. Specifically, in this embodiment, the dopant gas is PH3.

[0067] In another embodiment, the reactant gas also includes C2H4 to incorporate a small amount of carbon ions into the gate material layer 103.

[0068] Subsequently, the gate material layer 103, the first barrier material layer 102, and the gate dielectric material layer 101 are etched to form a gate structure. The gate structure includes a gate layer, a first barrier layer, and a gate dielectric layer. The gate dielectric layer is formed by the gate dielectric material layer 101, the first barrier layer is formed by the first barrier material layer 102, and the gate layer is formed by the gate material layer 103.

[0069] In this embodiment, the gate structure further includes a second barrier layer, which is doped with second barrier ions and is located on the surface of the gate layer. For a method of forming the second barrier layer, please refer to [reference needed]. Figures 4 to 5 .

[0070] Please refer to Figure 4 After the gate material layer 103 is formed, and before the gate material layer 103, the first barrier material layer 102 and the gate dielectric material layer 101 are etched, a second barrier material layer 104 is formed on the gate material layer 103, and the second barrier material layer 104 contains second barrier ions C.

[0071] Subsequently, the second barrier material layer 104 is etched to form a second barrier layer.

[0072] The material of the second barrier material layer 104 includes polycrystalline silicon. In this embodiment, the material of the second barrier material layer 104 is polycrystalline silicon.

[0073] The second blocking ion C includes carbon ions. In this embodiment, the second blocking ion C is a carbon ion.

[0074] In this embodiment, the concentration of carbon ions within the second barrier material layer 104 is less than or equal to 1E22 atom / cm³. 3 .

[0075] In this embodiment, the formation process of the second barrier material layer 104 includes a low-pressure chemical vapor deposition process.

[0076] In this embodiment, the process parameters for forming the second barrier material layer 104 include: the reaction gas includes C2H4 and SiH4, the reaction temperature range is 500°C to 550°C, and the pressure range is 300 mTorr to 1000 mTorr.

[0077] In another embodiment, the method for forming the second barrier material layer 104 includes: forming an initial second barrier material layer with an amorphous structure on a gate material layer, the initial second barrier material layer containing second barrier ions; heat-treating the initial second barrier material layer to form a polycrystalline structure, thereby forming the second barrier material layer; the process parameters for forming the initial second barrier layer include: the reaction gas includes C2H4 and SiH4, the reaction temperature range is 580°C to 630°C, and the pressure range is 100 mTorr to 500 mTorr.

[0078] In this embodiment, the thickness of the second barrier material layer 104 ranges from 5 nm to 40 nm.

[0079] Please refer to Figure 5The gate material layer 103, the first barrier material layer 102 and the gate dielectric material layer 101 are etched to form a gate structure. The gate structure includes a gate layer 105, a first barrier layer 106 and a gate dielectric layer 107. The gate dielectric layer 107 is formed with the gate dielectric material layer 101, the first barrier layer 106 is formed with the first barrier material layer 102 and the gate layer 105 is formed with the gate material layer 103.

[0080] In this embodiment, the second barrier material layer 104 is etched to form the second barrier layer 108.

[0081] The second barrier layer 108 is located on the surface of the gate layer 105. The second barrier layer 108 is used to block the diffusion of dopant ions B in the gate layer 105 to the surface of the gate layer 105, which can increase the concentration of dopant ions in the gate layer 105 and facilitate obtaining a gate structure with a higher target dopant ion concentration.

[0082] The material of the second barrier layer 108 includes polycrystalline silicon. In this embodiment, the material of the second barrier layer 108 is polycrystalline silicon.

[0083] In this embodiment, the thickness of the first barrier layer 106 ranges from 5 nm to 40 nm; the thickness of the second barrier layer 108 ranges from 5 nm to 40 nm.

[0084] In this embodiment, the concentration of carbon ions within the first barrier layer 106 is less than or equal to 1E22 atom / cm³. 3 The carbon ion concentration within the second barrier layer 108 is less than or equal to 1E22 atom / cm³. 3 .

[0085] Accordingly, embodiments of the present invention also provide a semiconductor structure formed using the above method. Please refer to [the documentation for further details]. Figure 5 The present invention includes: a substrate 100; a gate structure located on the surface of the substrate, the gate structure including a gate dielectric layer 107, a first barrier layer 106 located on the gate dielectric layer 107 and a gate layer 105 located on the first barrier layer 106, the first barrier layer 106 being doped with a first barrier ion A and the gate layer 105 being doped with a dopant ion B.

[0086] The first barrier layer 106 can block the diffusion of dopant ions B in the gate layer 105 to the gate dielectric layer 107, reduce the formation of interface states of dopant ions B at the interface between the gate dielectric layer 107 and the substrate 100, and affect device performance. At the same time, it can increase the concentration of dopant ions in the gate layer 105, avoid the reduction of dopant ion concentration caused by the diffusion of dopant ions to the interface, and facilitate obtaining a gate structure with a higher target dopant ion concentration.

[0087] In this embodiment, the material of the gate layer 105 includes polysilicon.

[0088] In this embodiment, the gate structure further includes a second barrier layer 108 located on the surface of the gate layer 105, and the second barrier layer 108 is doped with a second barrier ion C.

[0089] In this embodiment, the thickness of the first barrier layer 106 ranges from 5 nm to 40 nm; the thickness of the second barrier layer 108 ranges from 5 nm to 40 nm.

[0090] In this embodiment, the material of the first barrier layer 106 includes polycrystalline silicon; the first barrier ion A includes carbon ions; the material of the second barrier layer 108 includes polycrystalline silicon; and the second barrier ion C includes carbon ions.

[0091] In this embodiment, the concentration of carbon ions within the first barrier layer 106 is less than or equal to 1E22 atom / cm³. 3 The carbon ion concentration within the second barrier layer 108 is less than or equal to 1E22 atom / cm³. 3 .

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A gate structure located on the surface of the substrate, the gate structure including a gate dielectric layer, a first barrier layer located on the gate dielectric layer and a gate layer located on the first barrier layer, the first barrier layer being doped with first barrier ions, the gate layer being doped with dopant ions, and the first barrier layer serving as a seed for forming the gate layer.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the gate layer includes polycrystalline silicon.

3. The semiconductor structure as described in claim 1, characterized in that, The gate structure further includes a second barrier layer located on the surface of the gate layer, the second barrier layer being doped with second barrier ions.

4. The semiconductor structure as described in claim 3, characterized in that, The thickness of the first barrier layer ranges from 5 nm to 40 nm; the thickness of the second barrier layer ranges from 5 nm to 40 nm.

5. The semiconductor structure as described in claim 3, characterized in that, The material of the first barrier layer includes polycrystalline silicon; the first barrier ion includes carbon ions; the material of the second barrier layer includes polycrystalline silicon; the second barrier ion includes carbon ions.

6. The semiconductor structure as described in claim 5, characterized in that, The concentration of carbon ions within the first barrier layer is less than or equal to 1E22 atom / cm³. 3 The carbon ion concentration within the second barrier layer is less than or equal to 1E22atom / cm³. 3 .

7. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A gate dielectric material layer and a first barrier material layer are formed on the substrate, wherein the first barrier material layer is doped with first barrier ions. Using the first barrier material layer as a seed crystal, a gate material layer is formed on the surface of the first barrier material layer, and the gate material layer is doped with dopant ions. The gate material layer, the first barrier material layer, and the gate dielectric material layer are etched to form a gate structure, the gate structure including a gate layer, a first barrier layer, and a gate dielectric layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the first barrier material layer includes: forming an initial first barrier material layer having an amorphous structure on the substrate, wherein the initial first barrier material layer is doped with the first barrier ions; and performing heat treatment on the initial first barrier material layer to form a polycrystalline structure, thereby forming the first barrier material layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The formation process of the initial first barrier material layer includes a low-pressure chemical vapor deposition process.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first blocking ion includes carbon ions; the process parameters of the low-pressure chemical vapor deposition process include: the reaction gases include C2H4 and SiH4, the reaction temperature range is 500 ℃ to 550 ℃, and the pressure range is 300 mTorr to 1000 mTorr.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process parameters for the heat treatment include a temperature range of 600 ℃ to 800 ℃.

12. The method for forming a semiconductor structure as described in claim 7, characterized in that, The formation process of the first barrier material layer includes low-pressure chemical vapor deposition.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the first barrier layer includes polycrystalline silicon; the first barrier ions include carbon ions; the process parameters of the low-pressure chemical vapor deposition process include: the reaction gases include C2H4 and SiH4, the reaction temperature range is 580 ℃ to 630 ℃, and the pressure range is 100 mTorr to 500 mTorr.

14. The method for forming a semiconductor structure as described in claim 7, characterized in that, The formation process of the gate material layer includes a low-pressure chemical vapor deposition process; the process parameters of the low-pressure chemical vapor deposition process include: the reaction gas includes SiH4 and the dopant gas, wherein the dopant gas includes PH3 or BCl3.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The gate structure further includes a second barrier layer, which is doped with second barrier ions and is located on the surface of the gate layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming the second barrier layer further includes: after forming the gate material layer and before etching the gate material layer, the first barrier material layer and the gate dielectric material layer, forming a second barrier material layer on the gate material layer, wherein the second barrier material layer contains the second barrier ions; and the second barrier material layer is etched to form the second barrier layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The process for forming the second barrier material layer includes low-pressure chemical vapor deposition.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The material of the second barrier layer includes polycrystalline silicon; the second barrier ions include carbon ions.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The method for forming the second barrier material layer includes: forming an initial second barrier material layer with an amorphous structure on the gate material layer, wherein the initial second barrier material layer contains the second barrier ions; and performing heat treatment on the initial second barrier material layer to form a polycrystalline structure, thereby forming the second barrier material layer.

20. The method for forming a semiconductor structure as described in claim 7, characterized in that, The concentration of dopant ions within the gate material layer is less than or equal to 1E25 atom / cm³. 3 .

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