Power supply protection system

Abstract

A power protection system includes a hot plug controller, a processing chip unit, a transistor switch unit, and a delay circuit unit. The hot plug controller includes a detection terminal and a control terminal. The transistor switch unit includes a first terminal connected to the processing chip unit, a second terminal, and a third terminal controlled by the control terminal of the hot plug controller. When the processing chip unit operates in a peak power mode, a signal input to the second terminal of the transistor switch unit is a limit power signal. The delay circuit unit includes a delay terminal connected to the detection terminal of the hot plug controller, and a transmission terminal connected to the second terminal of the transistor switch unit. The limit power signal is detected by the transmission terminal of the delay circuit unit, and the limit power signal is transmitted to the detection terminal of the hot plug controller after a default time by the delay terminal, effectively ensuring that the processing chip unit can operate in the limit current for the preset time.

Description

Technical Field This invention relates to a protection system, and more particularly to a power supply protection system. Background Technology Servers often require high-efficiency processing chips to achieve high-speed operation and improve overall performance. For example, graphics processing units (GPUs) are used for high-performance graphics processing. With increasing processing speeds and performance requirements, more power is needed to operate the processing chips in maximum performance mode (peak mode). Generally, power supplies have a rated output power and are equipped with overcurrent protection (OCP) mechanisms to cut off the output current when the power supply current is too high, ensuring system safety and preventing damage to the processing chips or other components. However, it often happens that when the GPU is operating in maximum performance mode (peak mode), a sudden surge in power can trigger the overcurrent protection circuit, causing a power outage or restart. This inconvenience and inconvenience to users necessitates careful investigation and research into improvement solutions. Summary of the Invention The technical problem to be solved by the present invention is to provide a power supply protection system with high efficiency.

[0001] To solve the above-mentioned technical problems, the present invention provides a power supply protection system for receiving an input voltage from a power supply unit. The power supply protection system includes a hot-swappable controller capable of receiving the input voltage, a processing chip unit, a sensing resistor, a controlled transistor switch unit, and a delay circuit unit capable of receiving the input voltage.

[0002] The hot-swap controller includes a sensing terminal and a control terminal. The processing chip unit can operate in a peak power mode. The sensing resistor includes a first terminal for receiving the input voltage and a second terminal.

[0003] The transistor switching unit includes a first terminal connected to the processing chip unit, a second terminal, and a third terminal controlled by a control terminal of the hot-swap controller. The second terminal of a sensing resistor is connected to the second terminal of the transistor switching unit and can transmit a power supply signal to the second terminal of the transistor switching unit. The hot-swap controller controls the third terminal of the transistor switching unit via the control terminal, thereby controlling the switching on and off of the transistor switching unit. When the transistor switching unit receives a first control signal transmitted by the control terminal according to the third terminal, the transistor switching unit is in a conducting state, and the power supply signal received at the second terminal of the transistor switching unit is output to the processing chip unit via the first terminal, thus putting the processing chip unit into an operational state. When the processing chip unit operates in the peak power mode, the signal input to the second terminal of the transistor switching unit is a limit power supply signal.

[0004] The delay circuit unit includes a delay terminal connected to the detection terminal of the hot-swap controller and a transmission terminal connected to the second terminal of the transistor switching unit. When the processing chip unit is operating in the peak power mode, the delay circuit unit detects the limit power signal through the transmission terminal and after a default time, the delay terminal of the delay circuit unit transmits the limit power signal to the detection terminal of the hot-swap controller. When the hot-swap controller determines that the detection terminal has detected the limit power signal, the control terminal of the hot-swap controller transmits a second control signal to the third terminal of the transistor switching unit and makes the transistor switching unit non-conducting, and puts the processing chip unit in a non-operating state.

[0005] Compared to existing technologies, this invention utilizes a delay circuit unit to delay the signal received by the transmission end by a default time before transmitting it from the delay end to the detection end of the hot-swap controller. When the second terminal of the transistor switching unit receives the extreme power supply signal, the processing chip unit operates in the peak power mode. The transmission end of the delay circuit unit detects the extreme power supply signal, and after the default time, the delay end transmits the extreme power supply signal to the detection end of the hot-swap controller. This causes the control end of the hot-swap controller to control the transistor switching unit to be in a non-conducting state and the processing chip unit to be in a non-operating state, effectively ensuring that the processing chip unit can operate under the extreme power supply signal and maintain the default time. Attached Figure Description Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: Figure 1 This is a block diagram illustrating an embodiment of the power supply protection system of the present invention; and Figure 2This is a block diagram illustrating the connection relationship between a hot-swap controller, a transistor switching unit, and a protection circuit unit in this embodiment. Detailed Implementation Before the invention is described in detail, it should be noted that similar components are represented by the same numbers in the following description.

[0006] See Figure 1 and Figure 2 The present invention provides a power supply protection system 1 for receiving an input voltage from a power supply unit 80. The power supply protection system 1 includes a hot-swap controller 2 capable of receiving the input voltage, a processing chip unit 3, a sensing resistor 4, a transistor switch unit 5 that is controlled to be turned on and off, and a delay circuit unit 6 capable of receiving the input voltage.

[0007] The hot-swap controller 2 includes a detection terminal 21 and a control terminal 22. The processing chip unit 3 can operate in a peak power mode. The sensing resistor 4 includes a first terminal 41 that can receive the input voltage and a second terminal 42.

[0008] The transistor switching unit 5 includes a first terminal 51 connected to the processing chip unit 3, a second terminal 52, and a third terminal 53 controlled by the control terminal 22 of the hot-swap controller 2. The second terminal 42 of the sensing resistor 4 is connected to the second terminal 52 of the transistor switching unit 5, and the second terminal 42 of the sensing resistor 4 can transmit a power supply signal to the second terminal 52 of the transistor switching unit 5. The hot-swap controller 2 controls the third terminal 53 of the transistor switching unit 5 via the control terminal 22, thereby controlling the on / off state of the transistor switching unit 5. When the transistor switching unit 5 receives a first control signal transmitted by the control terminal 22 according to the third terminal 53, the transistor switching unit 5 is in a conducting state, and the power supply signal received by the second terminal 52 of the transistor switching unit 5 is output to the processing chip unit 3 via the first terminal 51, thus putting the processing chip unit 3 into an operational state. When the processing chip unit 3 operates in the peak power mode, the input to the second terminal 52 of the transistor switching unit 5 is a limit power supply signal.

[0009] The delay circuit unit 6 includes a delay terminal 61 connected to the detection terminal 21 of the hot-swap controller 2, and a transmission terminal 62 connected to the second terminal 52 of the transistor switching unit 5. When the processing chip unit 3 is operating in the peak power mode, after the delay circuit unit 6 detects the limit power supply signal through the transmission terminal 62 and a default time is reached, the delay terminal 61 of the delay circuit unit 6 transmits the limit power supply signal to the detection terminal 21 of the hot-swap controller 2. When the hot-swap controller 2 determines that the detection terminal 21 has detected the limit power supply signal, the control terminal 22 of the hot-swap controller 2 transmits a second control signal to the third terminal 53 of the transistor switching unit 5, making the transistor switching unit 5 non-conducting and putting the processing chip unit 3 in a non-operating state.

[0010] In use, after the power supply protection system 1 is powered on, the hot-swap controller 2 transmits the first control signal to the third terminal 53 of the transistor switching unit 5 via the control terminal 22 to control the transistor switching unit 5 to be in the conducting state (On). The first terminal 41 of the sensing resistor 4 receives the input voltage of the power supply unit 80 and generates the power supply signal, which is input to the second terminal 52 of the transistor switching unit 5 via the second terminal 42 of the sensing resistor 4, and output to the processing chip unit 3 via the first terminal 51 of the transistor switching unit 5, thus putting the processing chip unit 3 into operation. When the input to the second terminal 52 of the transistor switching unit 5 is the extreme power supply signal, the processing chip unit 3 operates in the peak power mode. At this time, the transmission terminal 62 of the delay circuit unit 6 detects the extreme power supply signal input to the second terminal 52 of the transistor switching unit 5, and the delay circuit unit 6 transmits the extreme power supply signal to the detection terminal 21 of the hot-swap controller 2 only after the default time. When the hot-swap controller 2 determines that the detection terminal 21 detects the power limit signal, the control terminal 22 of the hot-swap controller 2 sends the second control signal to the third terminal 53 of the transistor switching unit 5, causing the transistor switching unit 5 to be in a non-conducting state (Off), and putting the processing chip unit 3 into a non-operating state, thereby protecting the processing chip unit 3. In simpler terms, the hot-swap controller 2 will only control the transistor switching unit 5 to be in a non-conducting state (Off) and put the processing chip unit 3 into a non-operating state after the processing chip unit 3 can maintain operation in the peak power mode for the default time.

[0011] In this embodiment, the processing chip unit 3 is in the form of a Graphics Processing Unit (GPU), but is not limited thereto; it can also be in the form of a CPU, MCU, or other related electronic devices such as Digital Integrated Circuits (ICs). In this embodiment, the transistor switching unit 5 is in the form of an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS). The first terminal 51 of the transistor switching unit 5 is the source (S), the second terminal 52 is the drain (D), and the third terminal 53 is the gate (G), but is not limited thereto. In this embodiment, the power supply signal is a current signal, and the limiting power supply signal is a limiting current signal. That is, the current signal is output from the first terminal 51 of the transistor switching unit 5 to the processing chip unit 3, thereby putting the processing chip unit 3 into an operating state. When the current signal value input to the processing chip unit 3 reaches the limit current signal, the processing chip unit 3 starts to operate in the peak power mode. At this time, the transmission terminal 62 of the delay circuit unit 6 will detect that the current input to the second terminal 52 of the transistor switching unit 5 has reached or exceeded the limit current signal, and the delay circuit unit 6 will transmit the limit current signal to the detection terminal 21 of the hot-swap controller 2 after the default time. Furthermore, in this embodiment, the limiting condition of the peak power mode is that the processing chip unit 3 can operate at the limiting current within a peak time range. The preset time is equal to the peak time. That is, when the current signal flowing into the second terminal 52 of the transistor switching unit 5 reaches or exceeds the limiting current signal, it is output to the processing chip unit 3 through the first terminal 51 of the transistor switching unit 5, causing the processing chip unit 3 to operate at the limiting current signal. The maximum performance that the processing chip unit 3 can perform is to maintain the peak time while operating at the limiting current. Thus, this invention achieves the effect of delaying the detection terminal 21 of the hot-swap controller 2 to detect the limiting current signal after the preset time through the circuit design of the delay circuit unit 6, effectively ensuring that the processing chip unit 3 can operate at the limiting current and maintain the preset time without exceeding the limitation of the peak power mode, thereby enabling the processing chip unit 3 to execute the peak power mode when it needs to perform maximum performance. When the processing chip unit 3 operates with the limit current signal exceeding the peak time, the hot-swap controller 2 will control the transistor switching unit 5 to be in a non-conducting state (Off), and put the processing chip unit 3 into a non-operating state, thereby protecting the system and avoiding the risk of damage to the processing unit. In this embodiment, the preset time is equal to the peak time, but it is not limited to this. The preset time can be designed to be less than the peak time according to actual needs, so as to perform the protection action earlier.

[0012] It should be noted that, in this embodiment, the delay circuit unit 6 further includes a first resistor 63 and a first capacitor 64. The first resistor 63 has a first terminal 631 connected to the transmission terminal 62 and a second terminal 632. The first capacitor 64 has a first terminal 641 connected to the first terminal 631 of the sensing resistor 4 and a second terminal 642 connected to the second terminal 632 of the first resistor 63. The delay terminal 61 connects the second terminal 632 of the first resistor 63 and the second terminal 642 of the first capacitor 64. In short, the delay circuit unit 6 is designed as an RC delay circuit, but it is not limited to this. As long as the delay circuit unit 6 can delay the preset time before the detection terminal 21 of the hot-swap controller 2 detects the limit power supply signal, it is acceptable. In addition, in this embodiment, by utilizing the ingenuity of the delay circuit unit 6 as an RC delay circuit, the required preset time can be adjusted by adjusting the values ​​of the first resistor 63 and the first capacitor 64. This ensures that the operating limit current can be maintained within the required peak time range and the peak power mode can be maintained for the default time, effectively meeting the usage requirements of supporting multiple different peak power modes and providing excellent overall applicability.

[0013] By using the delay circuit unit 6, the signal received by the transmission terminal 62 is delayed by the default time before being transmitted from the delay terminal 61 to the detection terminal 21 of the hot-swap controller 2. When the second terminal 52 of the transistor switching unit 5 receives the extreme power supply signal, the processing chip unit 3 operates in the peak power mode. The transmission terminal 62 of the delay circuit unit 6 will detect the extreme power supply signal, and after the default time, the delay terminal 61 will transmit the extreme power supply signal to the detection terminal 21 of the hot-swap controller 2. This causes the control terminal 22 of the hot-swap controller 2 to control the transistor switching unit 5 to be in a non-conducting state and the processing chip unit 3 to be in a non-operating state, effectively ensuring that the processing chip unit 3 can operate under the extreme power supply signal and maintain the default time.

[0014] Please also see Figure 2It should be noted that this embodiment also includes a protection circuit unit 7. This protection circuit unit 7 has a signal terminal 71 connected to the detection terminal 21 of the hot-swap controller 2, a protection terminal 72 connected to the second terminal 42 of the sensing resistor 4 and the second terminal 52 of the transistor switching unit 5, a P-type metal-oxide-semiconductor field-effect transistor 73 connected to the signal terminal 71 and the protection terminal 72, and a startup circuit 74 controlling the opening and closing of the P-type metal-oxide-semiconductor field-effect transistor 73. The source (S) of the P-type metal-oxide-semiconductor field-effect transistor 73 is connected to the protection terminal 72, the drain (D) of the P-type metal-oxide-semiconductor field-effect transistor 73 is connected to the signal terminal 71, and the gate (G) of the P-type metal-oxide-semiconductor field-effect transistor 73 is connected to the startup circuit 74. This protection circuit unit 7 is used to protect the transistor switching unit 5. When the power supply protection system 1 is initially powered on, the startup circuit 74 controls the P-type metal-oxide-semiconductor field-effect transistor 73 to be in the conducting state within a protection time. At this time, the power supply signal transmitted by the second terminal 42 of the sensing resistor 4 will be input to the protection terminal 72 of the protection circuit unit 7 and through the P-type metal-oxide-semiconductor field-effect transistor 73 to the signal terminal 71 of the protection circuit unit 7, and then to the detection terminal 21 of the hot-swap controller 2. When the power supply protection system 1 is powered on and the protection time has elapsed, the startup circuit 74 controls the P-type metal-oxide-semiconductor field-effect transistor 73 to be in the non-conducting state. At this time, the power supply signal transmitted by the second terminal 42 of the sensing resistor 4 will be input to the second terminal 52 of the transistor switching unit 5. In detail, during the power-on process, as soon as the power supply protection system 1 is powered on, the startup circuit 74 immediately controls the P-type metal-oxide-semiconductor field-effect transistor 73 to be in the conducting state and maintains it in the conducting state for the protection time. At this time, because the P-type metal-oxide-semiconductor field-effect transistor 73 is conducting, the power supply signal transmitted by the second terminal 42 of the sensing resistor 4 will directly flow into the protection terminal 72 of the protection circuit unit 7 and through the P-type metal-oxide-semiconductor field-effect transistor 73 to the signal terminal 71 of the protection circuit unit 7. Furthermore, when the power supply protection system 1 is initially powered on, the hot-swap controller 2 has not yet completed its startup and cannot control the transistor switching unit 5 to turn on. Therefore, the transistor switching unit 5 is temporarily in a non-conducting state. During this protection period, the power supply signal output from the second terminal 42 of the sensing resistor 4 will flow directly into the P-type metal-oxide-semiconductor field-effect transistor 73 and will not be input to the transistor switching unit 5. This effectively avoids the problem of excessive current being input to the transistor switching unit 5 due to a short circuit in the processing chip unit 3 connected to the transistor switching unit 5 when the power supply protection system 1 is initially powered on, which could lead to the transistor switching unit 5 being broken down or damaged. This achieves the system power supply short circuit protection measure.When the power supply protection system 1 is powered on and the protection time has elapsed, the startup circuit 74 controls the P-type metal-oxide-semiconductor field-effect transistor 73 to be in a non-conducting state. At this time, the hot-swap controller 2 has completed the power-on startup and controls the transistor switching unit 5 to be in a conducting state. The power supply signal transmitted by the second terminal 42 of the sensing resistor 4 will be input to the second terminal 52 of the transistor switching unit 5. Additionally, the design connects the signal terminal 71 of the protection circuit unit 7 to the detection terminal 21 of the hot-swap controller 2. Upon power-up, the detection terminal 21 of the hot-swap controller 2 can detect the current at the signal terminal 71 of the protection circuit unit 7 in real time. If a short circuit occurs upon power-up, generating an overcurrent, the detection terminal 21 of the hot-swap controller 2 will detect the overcurrent in real time. However, since the overcurrent generated by a short circuit is usually much greater than the limit current, when the drain (D) of the P-type metal-oxide-semiconductor field-effect transistor 73 outputs an overcurrent to the signal terminal 71, the detection terminal 21 of the hot-swap controller 2 will detect the overcurrent at the signal terminal 71. If the current exceeds the limit current value, the hot-swap controller 2 will initially control the transistor switching unit 5 to be in a non-conducting state, effectively ensuring that after the protection time is exceeded, the overcurrent generated by the short circuit will not pass through the transistor switching unit 5, so as to avoid the risk of damaging the transistor switching unit 5.

[0015] In addition, in this embodiment, the startup circuit 74 of the protection circuit unit 7 includes a second resistor 75, a second capacitor 76, and a diode 77. The second resistor 75 has a first terminal 751 that can receive the input voltage and a second terminal 752. The second capacitor 76 has a first terminal 761 connected to the second terminal 752 of the second resistor 75 and a ground terminal 762. The gate of the P-type metal-oxide-semiconductor field-effect transistor 73 is connected to the first terminal 761 of the second capacitor 76 and the second terminal 752 of the second resistor 75. The anode of the diode 77 is connected to the gate of the P-type metal-oxide-semiconductor field-effect transistor 73, and the cathode of the diode 77 is connected to the first terminal 751 of the second resistor 75.

[0016] In summary, the power supply protection system 1 of the present invention, through the design of the delay circuit unit 6, can delay the extreme power supply signal by the default time. Only then will the detection terminal 21 of the hot-swap controller 2 detect the extreme power supply signal and control the transistor switching unit 5 to be in a non-conducting state, and put the processing chip unit 3 in a non-operating state. This effectively ensures that the processing chip unit 3 can operate at the extreme current for the preset time without exceeding the peak power mode limit, thereby achieving the requirement of the processing chip unit 3 to perform at maximum efficiency. Furthermore, in conjunction with the application of the protection circuit unit 7, when the power supply protection system 1 is initially powered on, the power supply signal output from the second terminal 42 of the sensing resistor 4 will directly flow into the P-type metal-oxide-semiconductor field-effect transistor 73 of the protection circuit unit 7 during the protection period, and will not be input to the transistor switching unit 5. This effectively avoids the problem of overcurrent being generated when the processing chip unit 3 connected to the transistor switching unit 5 is short-circuited when the power supply protection system 1 is initially powered on, which could lead to the transistor switching unit 5 being damaged or broken down.

[0017] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A power supply protection system for receiving an input voltage from a power supply unit, characterized in that, This power supply protection system includes: A hot-swappable controller capable of receiving the input voltage includes a detection terminal and a control terminal; A processing chip unit that can operate in a peak power mode; A sensing resistor includes a first terminal for receiving the input voltage and a second terminal; A controllably switched transistor unit includes a first terminal connected to the processing chip unit, a second terminal, and a third terminal controlled by a control terminal of a hot-swap controller. The second terminal of a sensing resistor is connected to the second terminal of the transistor switch unit and can transmit a power supply signal to the second terminal of the transistor switch unit. The hot-swap controller controls the third terminal of the transistor switch unit via the control terminal, thereby controlling the switching of the transistor switch unit. When the transistor switch unit receives a first control signal transmitted by the control terminal according to the third terminal, the transistor switch unit is in a conducting state, and the power supply signal received at the second terminal of the transistor switch unit is output to the processing chip unit via the first terminal, thus putting the processing chip unit into an operational state. When the processing chip unit operates in the peak power mode, the signal input to the second terminal of the transistor switch unit is a limit power supply signal. A delay circuit unit capable of receiving the input voltage includes a delay terminal connected to the detection terminal of the hot-swap controller and a transmission terminal connected to the second terminal of the transistor switching unit. When the processing chip unit operates in the peak power mode, the delay circuit unit detects the limit power supply signal through the transmission terminal and after a default time, the delay terminal of the delay circuit unit transmits the limit power supply signal to the detection terminal of the hot-swap controller. When the hot-swap controller determines that the detection terminal has detected the limit power supply signal, the control terminal of the hot-swap controller transmits a second control signal to the third terminal of the transistor switching unit and makes the transistor switching unit non-conducting, and puts the processing chip unit in a non-operating state.

2. The power supply protection system as described in claim 1, characterized in that, The delay circuit unit further includes a first resistor and a first capacitor. The first resistor has a first end connected to the transmission end and a second end. The first capacitor has a first end connected to the first end of the sensing resistor and a second end connected to the second end of the first resistor. The delay end is connected to the second end of the first resistor and the second end of the first capacitor.

3. The power supply protection system as described in claim 1, characterized in that, The transistor switching unit is an N-type metal-oxide-semiconductor field-effect transistor. The first terminal of the transistor switching unit is the source, the second terminal is the drain, and the third terminal is the gate.

4. The power supply protection system as described in claim 3, characterized in that, It also includes a protection circuit unit, which has a signal terminal connected to the detection terminal of the hot-swap controller, a protection terminal connected to the second terminal of the sensing resistor and the second terminal of the transistor switching unit, a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) connected to the signal terminal and the protection terminal, and a startup circuit for controlling the switching of the P-type MOSFET. The source of the P-type MOSFET is connected to the protection terminal, the drain of the P-type MOSFET is connected to the signal terminal, and the gate of the P-type MOSFET is connected to the startup circuit. The protection circuit unit is used to protect the transistor switching unit when... When the power supply protection system is initially powered on, the startup circuit controls the P-type metal-oxide-semiconductor field-effect transistor to be in the conducting state within a protection period. At this time, the power supply signal transmitted from the second terminal of the sensing resistor is input to the protection terminal of the protection circuit unit and then through the P-type metal-oxide-semiconductor field-effect transistor to the signal terminal of the protection circuit unit, and finally to the detection terminal of the hot-swap controller. After the power supply protection system is powered on and the protection period has elapsed, the startup circuit controls the P-type metal-oxide-semiconductor field-effect transistor to be in the non-conducting state. At this time, the power supply signal transmitted from the second terminal of the sensing resistor is input to the second terminal of the transistor switching unit.

5. The power supply protection system as described in claim 4, characterized in that, The startup circuit of the protection circuit unit has a second resistor and a second capacitor. The second resistor has a first terminal that can receive the input voltage and a second terminal. The second capacitor has a first terminal that is connected to the second terminal of the second resistor and a ground terminal. The gate of the P-type metal-oxide-semiconductor field-effect transistor is connected to the first terminal of the second capacitor and the second terminal of the second resistor.

6. The power supply protection system as described in claim 5, characterized in that, The startup circuit of the protection circuit unit also has a diode that connects the second resistor and the P-type metal-oxide-semiconductor field-effect transistor. The anode of the diode is connected to the gate of the P-type metal-oxide-semiconductor field-effect transistor, and the cathode of the diode is connected to the first terminal of the second resistor.

7. The power supply protection system as described in claim 1, characterized in that, The power limit signal is a current limit signal, and the peak power mode allows the processing chip unit to operate at the current limit within a peak time range, where the default time is less than or equal to the peak time.

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