A potential conversion circuit and chip

Abstract

This application discloses a potential conversion circuit and chip, applied in the field of power electronics technology, to solve the problem of uncertain operating state and output signal of the potential conversion circuit when the low-voltage domain power supply is powered off in the prior art. Specifically, a power-on state detection circuit detects the voltage value of the first power supply and generates a power-on state signal. The first potential conversion circuit converts this signal to a power-on state signal with the second power supply as the voltage domain. When the power-on state signal with the second power supply as the voltage domain is a power-off state signal, the internal nodes of the second potential conversion circuit have fixed states, controlling the target digital signal output to the second circuit to be a fixed value. In this way, when the first power supply is in a power-off state, the second potential conversion circuit has no leakage risk, and the external second circuit does not have an unexpected operating state.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a potential conversion circuit and chip. Background Technology

[0002] With the development of integrated circuit products, the requirements for functional integration are becoming increasingly stringent. More and more functional modules are being designed into complex power systems. Due to considerations such as power consumption, radiation, area, and compatibility, multiple power domains are typically set up simultaneously in an integrated circuit system. Signal transmission across different voltage domains has become commonplace, leading to the widespread use of potential conversion circuits. Potential conversion can be divided into two types: conversion from a high voltage domain to a low voltage domain and conversion from a low voltage domain to a high voltage domain. Conversion from a high voltage domain to a low voltage domain is usually achieved directly using two stages of inverters. Conversion from a low voltage domain to a high voltage domain is relatively complex, requiring consideration of factors such as the voltage difference between the high and low voltage domains and the operating frequency of the digital signal being converted.

[0003] Currently, existing low-voltage domain to high-voltage domain potential conversion circuits, such as Figure 1 As shown, this circuit mainly consists of an inverter, a positive feedback circuit, and a switching transistor module. While it can meet the requirements of reducing circuit area and increasing input signal speed, when the low-voltage power supply VDDL is de-energized, the voltages at nodes Vb and Vc become uncertain. The potential conversion circuit operates in an uncertain state, posing a risk of leakage. Simultaneously, the output signal Voh also exhibits an uncertain potential, meaning devices using Voh as input signals also face leakage risks and unexpected operating conditions. Summary of the Invention

[0004] This application provides a potential conversion circuit and chip to solve the problem in the prior art where the operating state and output signal of the potential conversion circuit are uncertain when the low-voltage domain power supply is lost.

[0005] The technical solutions provided in this application are as follows:

[0006] On one hand, embodiments of this application provide a potential conversion circuit, including: a power-on state detection circuit, a first potential conversion circuit, a second potential conversion circuit, a first power supply, and a second power supply; wherein the voltage of the first power supply is lower than the voltage of the second power supply;

[0007] The first terminal of the power-on status detection circuit is connected to the first power supply, the second terminal of the power-on status detection circuit is connected to the first terminal of the first potential conversion circuit, and the third terminal of the power-on status detection circuit is connected to ground. The power-on status detection circuit is used to detect the voltage value of the first power supply and generate a power-on status signal based on the voltage value of the first power supply.

[0008] The second terminal of the first potential conversion circuit is connected to the first power supply, the third terminal of the first potential conversion circuit is connected to the second power supply, the fourth terminal of the first potential conversion circuit is connected to the first terminal of the second potential conversion circuit, and the fifth terminal of the first potential conversion circuit is connected to ground; the first potential conversion circuit is used to convert the power-on status signal into a power-on status signal with the second power supply as the voltage domain.

[0009] The second terminal of the second potential conversion circuit is connected to the external first circuit, the third terminal of the second potential conversion circuit is connected to the first power supply, the fourth terminal of the second potential conversion circuit is connected to the second power supply, the fifth terminal of the second potential conversion circuit is connected to the external second circuit, and the sixth terminal of the second potential conversion circuit is connected to ground. The second potential conversion circuit is used to determine the target digital signal to be output to the external second circuit based on the power-on state signal of the second power supply as the voltage domain and the digital signal input to the external first circuit, and when the power-on state signal of the second power supply as the voltage domain is the power-off state signal, it controls the target digital signal output to the second circuit to be a fixed value.

[0010] In one possible implementation, the first potential conversion circuit includes: a first inverter module, a first positive feedback module, a charge / discharge module, a first inverter, a second inverter, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a first resistor;

[0011] The gate of the first NMOS transistor is connected to the second terminal of the power-on state detection circuit. The drain of the first NMOS transistor is connected to the source, gate, and third gate of the second NMOS transistor and the first terminal of the charge / discharge module. The source of the first NMOS transistor is connected to ground. The drain of the second NMOS transistor is connected to the second terminal of the charge / discharge module via a first resistor. The second terminal of the charge / discharge module is also connected to the second power supply. The base of the second NMOS transistor is connected to ground. The drain of the third NMOS transistor is connected to the second terminal of the first positive feedback module. The source of the third NMOS transistor is connected to the source of the first NMOS transistor and ground. The gate of the fourth NMOS transistor is connected to the output terminal of the first inverter. The drain of the fourth NMOS transistor is connected to the second terminal of the first positive feedback module. The source of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor and ground. The gate of the fifth NMOS transistor is connected to the output terminal of the second inverter. The drain of the fifth NMOS transistor is connected to the first terminal of the first positive feedback module. The source and drain of the fifth NMOS transistor are connected to ground.

[0012] The first terminal of the first positive feedback module is connected to the first terminal of the first inverter module, and the third and fourth terminals of the first positive feedback module are both connected to the second power supply.

[0013] The second terminal of the first inverter module is connected to the second power supply, the third terminal of the first inverter module is connected to ground, and the fourth terminal of the first inverter module is connected to the first terminal of the second potential conversion circuit.

[0014] The input terminal of the first inverter is connected to the second terminal of the power-on state detection circuit, and the output terminal of the first inverter is connected to the input terminal of the second inverter. The first power supply terminals of the first inverter and the second inverter are connected to the first power supply, and the second power supply terminals of the first inverter and the second inverter are connected to ground.

[0015] In one possible implementation, the charging and discharging module includes: a first PMOS transistor or a capacitor;

[0016] The gate of the first PMOS transistor is connected to the drain of the first NMOS transistor, the source of the first PMOS transistor is connected to the drain of the second NMOS transistor via the first resistor, and the drain of the first PMOS transistor is connected to the first power supply.

[0017] The first terminal of the capacitor is connected to the drain of the first NMOS transistor, the second terminal of the capacitor is connected to the first power supply, and the second terminal of the capacitor is also connected to the drain of the second NMOS transistor via the first resistor.

[0018] In one possible implementation, the first positive feedback module includes: a second PMOS transistor and a third PMOS transistor;

[0019] The source of the second PMOS transistor serves as the first terminal of the first positive feedback module, the source of the third PMOS transistor serves as the second terminal of the first positive feedback module, the drain of the second PMOS transistor serves as the third terminal of the first positive feedback module, the drain of the third PMOS transistor serves as the fourth terminal of the first positive feedback module, the gate of the second PMOS transistor is connected to the source of the third PMOS transistor, and the gate of the third PMOS transistor is connected to the source of the second PMOS transistor.

[0020] In one possible implementation, the first inverter module includes: a fourth PMOS transistor and a sixth NMOS transistor;

[0021] The gate of the fourth PMOS transistor serves as the first terminal of the first inverter module, the drain of the fourth PMOS transistor serves as the second terminal of the first inverter module, and the source of the fourth PMOS transistor serves as the fourth terminal of the first inverter module.

[0022] The gate of the sixth NMOS transistor is connected to the gate of the fourth PMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the fourth PMOS transistor, and the source of the sixth NMOS transistor serves as the third terminal of the first inverter module.

[0023] In one possible implementation, the second potential conversion circuit includes: a second inverter module, a second positive feedback module, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a fifth PMOS transistor;

[0024] The input terminal of the third inverter is connected to the external first circuit. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the gate of the seventh NMOS transistor, respectively. The output terminal of the fourth inverter is connected to the gate of the eighth NMOS transistor. The input terminal of the fifth inverter is connected to the fourth terminal of the first potential conversion circuit. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the gate of the ninth NMOS transistor. The first power supply terminals of the third and fourth inverters are connected to the first power supply. The first power supply terminals of the fifth and sixth inverters are connected to the second power supply. The second power supply terminals of the third, fourth, fifth, and sixth inverters are all connected to ground.

[0025] The drain of the seventh NMOS transistor is connected to the first terminal of the second positive feedback module, the drain of the eighth NMOS transistor is connected to the second terminal of the second positive feedback module, and the sources of both the seventh and eighth NMOS transistors are connected to the drain of the ninth NMOS transistor; the third and fourth terminals of the second positive feedback module are both connected to the second power supply.

[0026] The first terminal of the second inverter module is connected to the second terminal of the second positive feedback module, the second terminal of the second inverter module is connected to the second power supply, the third terminal of the second inverter module is connected to ground, and the fourth terminal of the second inverter module is connected to the external second circuit.

[0027] The gate of the fifth PMOS transistor is connected to the output of the sixth inverter, the source of the fifth PMOS transistor is connected to the first terminal of the second inverter module, and the drain of the fifth PMOS transistor is connected to the second power supply.

[0028] In one possible implementation, the second potential conversion circuit includes: a second inverter module, a second positive feedback module, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;

[0029] The input terminal of the third inverter is connected to the external first circuit. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the gate of the seventh NMOS transistor, respectively. The output terminal of the fourth inverter is connected to the gate of the eighth NMOS transistor. The input terminal of the fifth inverter is connected to the fourth terminal of the first potential conversion circuit. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the gate of the ninth NMOS transistor. The first power supply terminals of the third and fourth inverters are connected to the first power supply. The first power supply terminals of the fifth and sixth inverters are connected to the second power supply. The second power supply terminals of the third, fourth, fifth, and sixth inverters are all connected to ground.

[0030] The drain of the seventh NMOS transistor is connected to the first terminal of the second positive feedback module, the drain of the eighth NMOS transistor is connected to the second terminal of the second positive feedback module, and the sources of both the seventh and eighth NMOS transistors are connected to the drain of the ninth NMOS transistor; the third and fourth terminals of the second positive feedback module are both connected to the second power supply.

[0031] The first terminal of the second inverter module is connected to the second terminal of the second positive feedback module, the second terminal of the second inverter module is connected to the second power supply, the third terminal of the second inverter module is connected to ground, and the fourth terminal of the second inverter module is connected to the external second circuit.

[0032] The gate of the tenth NMOS transistor is connected to the output of the fifth inverter, the source of the tenth NMOS transistor is connected to ground, and the drain of the tenth NMOS transistor is connected to the first terminal of the second inverter module.

[0033] In one possible implementation, the second potential conversion circuit includes: a second inverter module, a second positive feedback module, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and a fifth PMOS transistor;

[0034] The input terminal of the third inverter is connected to the external first circuit. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the gate of the seventh NMOS transistor, respectively. The output terminal of the fourth inverter is connected to the gate of the eighth NMOS transistor. The input terminal of the fifth inverter is connected to the fourth terminal of the first potential conversion circuit. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor, respectively. The first power supply terminals of the third and fourth inverters are connected to the first power supply. The first power supply terminals of the fifth and sixth inverters are connected to the second power supply. The second power supply terminals of the third, fourth, fifth, and sixth inverters are all connected to ground.

[0035] The drain of the ninth NMOS transistor is connected to the first terminal of the second positive feedback module, the source of the ninth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the base of the ninth NMOS transistor is connected to ground; the drain of the tenth NMOS transistor is connected to the second terminal of the second positive feedback module, the source of the tenth NMOS transistor is connected to the drain of the eighth NMOS transistor, and the base of the tenth NMOS transistor is connected to ground; the sources of both the seventh and eighth NMOS transistors are connected to ground; the third and fourth terminals of the second positive feedback module are both connected to the second power supply.

[0036] The first terminal of the second inverter module is connected to the second terminal of the second positive feedback module, the second terminal of the second inverter module is connected to the second power supply, the third terminal of the second inverter module is connected to ground, and the fourth terminal of the second inverter module is connected to the external second circuit.

[0037] The gate of the fifth PMOS transistor is connected to the output of the sixth inverter, the source of the fifth PMOS transistor is connected to the first terminal of the second inverter module, and the drain of the fifth PMOS transistor is connected to the second power supply.

[0038] In one possible implementation, the second potential conversion circuit includes: a second inverter module, a second positive feedback module, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor;

[0039] The input terminal of the third inverter is connected to the external first circuit. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the gate of the seventh NMOS transistor, respectively. The output terminal of the fourth inverter is connected to the gate of the eighth NMOS transistor. The input terminal of the fifth inverter is connected to the fourth terminal of the first potential conversion circuit. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor, respectively. The first power supply terminals of the third and fourth inverters are connected to the first power supply. The first power supply terminals of the fifth and sixth inverters are connected to the second power supply. The second power supply terminals of the third, fourth, fifth, and sixth inverters are all connected to ground.

[0040] The drain of the ninth NMOS transistor is connected to the first terminal of the second positive feedback module, the source of the ninth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the base of the ninth NMOS transistor is connected to ground; the drain of the tenth NMOS transistor is connected to the second terminal of the second positive feedback module, the source of the tenth NMOS transistor is connected to the drain of the eighth NMOS transistor, and the base of the tenth NMOS transistor is connected to ground; the sources of both the seventh and eighth NMOS transistors are connected to ground; the third and fourth terminals of the second positive feedback module are both connected to the second power supply.

[0041] The first terminal of the second inverter module is connected to the second terminal of the second positive feedback module, the second terminal of the second inverter module is connected to the second power supply, the third terminal of the second inverter module is connected to ground, and the fourth terminal of the second inverter module is connected to the external second circuit.

[0042] The gate of the eleventh NMOS transistor is connected to the output of the fifth inverter, the source of the eleventh NMOS transistor is connected to ground, and the drain of the eleventh NMOS transistor is connected to the first terminal of the second inverter module.

[0043] On the other hand, embodiments of this application provide a chip, including: a first circuit, a second circuit, and a potential conversion circuit provided in embodiments of this application;

[0044] The input terminal of the potential conversion circuit is connected to the first circuit, and the output terminal of the potential conversion circuit is connected to the second circuit.

[0045] The beneficial effects of the embodiments of this application are as follows:

[0046] In this embodiment, a power-on state detection circuit detects the voltage value of a first power supply and generates a power-on state signal based on that voltage. A first potential conversion circuit converts the power-on state signal into a power-on state signal with a second power supply as its voltage domain. A second potential conversion circuit determines the target digital signal to be output to an external second circuit based on the power-on state signal with the second power supply as its voltage domain and the digital signal input from the external first circuit. When the power-on state signal with the second power supply as its voltage domain is a power-off state signal, the target digital signal output to the second circuit is controlled to be a fixed value. This ensures that each node within the potential conversion circuit also has a fixed state when the first power supply is in a power-off state, thereby enabling the output of a target digital signal with a fixed state and eliminating the risk of leakage current in the circuit. Simultaneously, the target digital signal transmitted to the external second circuit has a fixed state, and the second circuit using the target digital signal has a fixed input state, eliminating the risk of leakage current and unexpected operating states.

[0047] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0048] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0049] Figure 1 This is a schematic diagram of the circuit structure of a conventional potential conversion circuit in an embodiment of this application;

[0050] Figure 2 This is a schematic diagram of a potential conversion circuit in one embodiment of this application;

[0051] Figure 3a This is a schematic diagram of a circuit structure for a power-on state detection circuit in an embodiment of this application;

[0052] Figure 3b This is a waveform diagram of the power-on state detection circuit in the embodiments of this application;

[0053] Figure 4 This is a schematic diagram of a first circuit structure of the first potential conversion circuit in the embodiments of this application;

[0054] Figure 5 This is a schematic diagram of a second circuit structure for the first potential conversion circuit in the embodiments of this application;

[0055] Figure 6This is a schematic diagram of a third circuit structure for the first potential conversion circuit in the embodiments of this application;

[0056] Figure 7 This is a schematic diagram of the fourth circuit structure of the first potential conversion circuit in the embodiments of this application;

[0057] Figure 8 This is a schematic diagram of the first circuit structure of the second potential conversion circuit in the embodiments of this application;

[0058] Figure 9 This is a schematic diagram of a second circuit structure for the second potential conversion circuit in the embodiments of this application;

[0059] Figure 10 This is a schematic diagram of a third circuit structure for the second potential conversion circuit in the embodiments of this application;

[0060] Figure 11 This is a schematic diagram of the fourth circuit structure of the second potential conversion circuit in the embodiments of this application;

[0061] Figure 12 This is a schematic diagram of a circuit structure of the chip in an embodiment of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and beneficial effects of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0063] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein.

[0064] This application provides a potential conversion circuit, see below. Figure 2 As shown, the potential conversion circuit 100 provided in this application embodiment includes at least: a power-on state detection circuit 110, a first potential conversion circuit 120, a second potential conversion circuit 130, a first power supply 140, and a second power supply 150; wherein, the voltage of the first power supply 140 is lower than the voltage of the second power supply 150.

[0065] The first terminal of the power-on state detection circuit 110 is connected to the first power supply 140, the second terminal of the power-on state detection circuit 110 is connected to the first terminal of the first potential conversion circuit 120, and the third terminal of the power-on state detection circuit 110 is connected to ground; the power-on state detection circuit 110 is used to detect the voltage value of the first power supply 140 and generate a power-on state signal based on the voltage value of the first power supply 140.

[0066] The second terminal of the first potential conversion circuit 120 is connected to the first power supply 140, the third terminal of the first potential conversion circuit 120 is connected to the second power supply 150, the fourth terminal of the first potential conversion circuit 120 is connected to the first terminal of the second potential conversion circuit 130, and the fifth terminal of the first potential conversion circuit 120 is connected to ground; the first potential conversion circuit 120 is used to convert the power-on status signal into a power-on status signal with the second power supply 150 as the voltage domain.

[0067] The second terminal of the second potential conversion circuit 130 is connected to the external first circuit, the third terminal of the second potential conversion circuit 130 is connected to the first power supply 140, the fourth terminal of the second potential conversion circuit 130 is connected to the second power supply 150, the fifth terminal of the second potential conversion circuit 130 is connected to the external second circuit, and the sixth terminal of the second potential conversion circuit 130 is connected to ground. The second potential conversion circuit 130 is used to determine the target digital signal to be output to the external second circuit based on the power-on state signal of the second power supply 150 as the voltage domain and the digital signal input to the external first circuit. When the power-on state signal of the second power supply 150 as the voltage domain is a power-off state signal, it controls the target digital signal to be output to the second circuit to a fixed value.

[0068] In practical applications, the voltage VDDL of the first power supply 140 is lower than the voltage VDDH of the second power supply 150. The first power supply 140 is generally a low-voltage domain power supply, and the second power supply 150 is generally a high-voltage domain power supply. The power-on state detection circuit 110 detects the voltage value of the first power supply 140. When the voltage value of the first power supply 140 is higher than a preset power-on threshold, the generated power-on state signal is the low-voltage domain voltage VDDL, indicating that the first power supply 140 is in a power-on state; when the voltage value of the first power supply 140 is lower than the preset power-on threshold, the generated power-on state signal is the ground potential GND, indicating that the first power supply 140 is in a power-off state. The first potential conversion circuit 120 is used to convert the power-on state signal into a power-on state signal with the second power supply 150 as the voltage domain. When the power-on state signal is the low-voltage domain voltage VDDL, it is converted into the high-voltage domain voltage VDDH and output to the second potential conversion circuit 130; when the power-on state signal is the ground potential GND, the ground potential GND is output to the second potential conversion circuit 130. The second potential conversion circuit 130, when the second power supply 150 serves as the power-on state signal in the voltage domain and is ground potential GND (i.e., the power-off state signal), disregards the level of the digital signal input from the external first circuit and controls the target digital signal output to the second circuit to a fixed value, typically ground potential GND. When the second power supply 150 serves as the power-on state signal in the voltage domain and is a high voltage domain voltage VDDH, the second potential conversion circuit 130 converts the digital signal input from the external first circuit to obtain the target digital signal, which is then transmitted to the second circuit. Specifically, if the digital signal input from the external first circuit is a low voltage domain voltage VDDL, it is converted to a low voltage domain voltage VDDH and transmitted to the second circuit; if the digital signal input from the external first circuit is a ground potential GND, it is transmitted to the second circuit.

[0069] In specific implementations, the power-on state detection circuit 110 in the potential conversion circuit provided in this embodiment of the invention can have various specific structures to realize its function. For example... Figure 3a As shown, the power-on state detection circuit can be composed of a comparator. The positive input terminal of the comparator is connected to the first power supply 140, the negative input terminal of the comparator is input with the voltage threshold vth, and the output terminal of the comparator is connected to the first terminal of the first potential conversion circuit 120. Figure 3b The diagram shows the operating waveforms of the power-on state detection circuit composed of a comparator. When the voltage VDDL of the first power supply is higher than the voltage threshold vth, the comparator outputs a high level to the first potential conversion circuit 120; when the voltage VDDL of the first power supply is lower than the voltage threshold vth, the comparator outputs a low level to the first potential conversion circuit 120.

[0070] In this way, when the first power supply is off, each node inside the potential conversion circuit also has a fixed state, thus enabling the output of a target digital signal with a fixed state, and eliminating the risk of leakage in the potential conversion circuit. Simultaneously, the target digital signal transmitted to the second circuit has a fixed state, and the second circuit using the target digital signal has a fixed input state, eliminating the risk of leakage and unexpected operating states.

[0071] In specific implementations, the first potential conversion circuit 120 in the potential conversion circuit provided in this embodiment of the invention can have various specific structures to realize its function. For example... Figure 4 As shown, the first potential conversion circuit 120 includes at least: a first inverter module 121, a first positive feedback module 122, a charge / discharge module 123, a first inverter inv1, a second inverter inv2, a first NMOS transistor Qn1, a second NMOS transistor Qn2, a third NMOS transistor Qn3, a fourth NMOS transistor Qn4, a fifth NMOS transistor Qn5, and a first resistor R1;

[0072] The gate of the first NMOS transistor Qn1 is connected to the second terminal of the power-on state detection circuit 110. The drain of the first NMOS transistor Qn1 is connected to the source, gate, and third NMOS transistor Qn3 of the second NMOS transistor Qn2 and the first terminal of the charge / discharge module 123, respectively. The source of the first NMOS transistor Qn1 is connected to ground. The drain of the second NMOS transistor Qn2 is connected to the second terminal of the charge / discharge module 123 via the first resistor R1. The second terminal of the charge / discharge module 123 is also connected to the second power supply. The base of the second NMOS transistor Qn2 is connected to ground. The drain of the third NMOS transistor Qn3 is connected to the second terminal of the first positive feedback module 122. The source of the third NMOS transistor Qn3 is connected to the source of the first NMOS transistor Qn1 and ground, respectively; the gate of the fourth NMOS transistor Qn4 is connected to the output terminal of the first inverter inv1, the drain of the fourth NMOS transistor Qn4 is connected to the second terminal of the first positive feedback module 122, and the source of the fourth NMOS transistor Qn4 is connected to the source of the fifth NMOS transistor Qn5 and ground, respectively; the gate of the fifth NMOS transistor Qn5 is connected to the output terminal of the second inverter inv2, the drain of the fifth NMOS transistor Qn5 is connected to the first terminal of the first positive feedback module 122, and the source and drain of the fifth NMOS transistor Qn5 are connected to ground;

[0073] The first terminal of the first positive feedback module 122 is connected to the first terminal of the first inverter module 121, and the third and fourth terminals of the first positive feedback module 122 are both connected to the second power supply 150.

[0074] The second terminal of the first inverter module 121 is connected to the second power supply 150, the third terminal of the first inverter module 121 is connected to ground, and the fourth terminal of the first inverter module 121 is connected to the first terminal of the second potential conversion circuit 130.

[0075] The input terminal of the first inverter inv1 is connected to the second terminal of the power-on state detection circuit 110, and the output terminal of the first inverter inv1 is connected to the input terminal of the second inverter inv2. The first power supply terminal of the first inverter inv1 and the first power supply terminal of the second inverter inv2 are connected to the first power supply 140, and the second power supply terminal of the first inverter inv1 and the second power supply terminal of the second inverter inv2 are connected to ground.

[0076] In practical applications, the first resistor is used to limit the current in its branch after the second power supply is powered on. The first inverter module 121 is used to invert the phase of the input signal by 180°. The first positive feedback module 122 is used to pull down the voltage of the first target terminal to GND and pull up the voltage of the second target terminal to the voltage of the power supply connected to the third and fourth terminals of the first positive feedback module 122 when the voltage of the first target terminal is pulled down; the first positive feedback module 122 is also used to pull up the voltage of the first target terminal to the voltage of the power supply connected to the third and fourth terminals of the first positive feedback module 122 and pull down the voltage of the second target terminal to GND when the voltage of the first target terminal is pulled up. Here, the first target terminal is either the first or second terminal of the first positive feedback module 122, and the second target terminal is one of the first and second terminals of the first positive feedback module 122 other than the first target terminal. The charge / discharge module 123 is used to charge through the second power supply 150, pulling up the voltage of the VF node to the VDDH potential. After the second power supply 150 is initially powered on, the charging and discharging module 123 charges the Vf node to the VDDH potential. Based on the voltage condition of the first power supply 140, the operating states of the first potential conversion circuit 120 are divided into the following three types:

[0077] The first operating state is when the first power supply 140 is not powered on. At this time, the power-on state signal POL output by the power-on state detection circuit 110 is GND, the first NMOS transistor Qn1 is off, the voltage at node Vf is VDDH, the third NMOS transistor Qn3 is on, and the voltage at node Vd is pulled low by the third NMOS transistor. The first positive feedback module 122 further pulls the voltage at node Vd down to GND and further pulls the voltage at node Ve up to VDDH. The voltage at node Ve, after being inverted by the first inverter module 121, outputs a power-on state signal POH with the second power supply 150 as the voltage domain, which is GND. In this way, a definite state of each component and circuit output in the first potential conversion circuit 120 can be achieved when the first power supply 140 is not powered on, and the first potential conversion circuit 120 has no leakage current problem at this time.

[0078] The second operating state is the state after the first power supply 140 is not powered on. At this time, the power-on state detection circuit 110 outputs a power-on state signal POL of VDDL, the first NMOS transistor Qn1 is turned on, and the voltage of node Vf is pulled down to GND. The gate and source of the second NMOS transistor Qn2 are both connected to node Vf, and Qn2 is in the off state. The equivalent resistance of Qn2 is greater than 1 GΩ, and the leakage current is less than 1 nA. The voltage of node Vf is GND, the third NMOS transistor Qn3 is turned off, the voltage of node Vc is GND, the fourth NMOS transistor Qn4 is turned off, the voltage of node Vb is VDDL, and the fifth NMOS transistor Qn5 is turned on, pulling the voltage of node Ve low. The first positive feedback module 122 further pulls the voltage of node Ve down to GND and further pulls the voltage of node Vd up to VDDH. The voltage at node Ve, after being inverted by the first inverter module 121, outputs a power-on status signal POH with the second power supply 150 as the voltage domain, which is VDDH. Thus, after the first power supply 140 is powered on, the leakage current of the first potential conversion circuit 120 is less than 1nA, indicating a very small leakage current.

[0079] The third operating state is the state where the first power supply 140 is powered on and then powered off. In this state, because the power-on state detection circuit 110 outputs a low level to the first potential conversion circuit 120 when the voltage VDDL of the first power supply is lower than the voltage threshold vth, the change in the power-on state signal POL output by the power-on state detection circuit 110 precedes the change in VDDL. The voltages of nodes Vc and Vb can be converted to fixed VDDL and GND states respectively within a certain time, causing the fourth NMOS transistor Qn4 to conduct and the fifth NMOS transistor Qn5 to turn off. Similarly, under the action of the first positive feedback module 122, the voltage of node Vd is further pulled down to GND, and the voltage of node Ve is further pulled up to VDDH. The voltage of node Ve, after being inverted by the first inverter module 121, outputs a power-on state signal POH with the second power supply 150 as the voltage domain, which is GND. In this way, the output states of each component and circuit in the first potential conversion circuit 120 can be determined when the first power supply 140 is powered on and then powered off, and the first potential conversion circuit 120 has no leakage problem at this time.

[0080] In specific implementations, the charging and discharging module 123 in the first potential conversion circuit 120 of the embodiment of the present invention can have various specific structures to realize its function. The charging and discharging module 123 includes at least: a first PMOS transistor Qp1 or a capacitor C;

[0081] The gate of the first PMOS transistor Qp1 is connected to the drain of the first NMOS transistor Qn1, the source of the first PMOS transistor Qp1 is connected to the drain of the second NMOS transistor Qn2 through the first resistor R1, and the drain of the first PMOS transistor Qp1 is connected to the first power supply 140.

[0082] The first end of capacitor C is connected to the drain of the first NMOS transistor Qn1, the second end of capacitor C is connected to the first power supply 140, and the second end of capacitor C is also connected to the drain of the second NMOS transistor Qn2 through the first resistor R1.

[0083] In practical applications, refer to Figure 5 As shown, the charge / discharge module 123 can be a capacitor C. The capacitor C is charged after the second power supply 150 is initially powered on, charging the Vf node to the VDDH potential. (See reference...) Figure 6 As shown, the charging / discharging module 123 can also be a first NMOS transistor Qn1, with its drain and source connected to the base. After the second power supply 150 is initially powered on, the parasitic capacitance C of the first NMOS transistor Qn1 is charged, and the Vf node can also be charged to the VDDH potential.

[0084] In specific implementations, the first positive feedback module 122 in the potential conversion circuit provided in this embodiment of the invention can have various specific structures to realize its function. For example... Figure 7 As shown, the first positive feedback module 122 includes at least: a second PMOS transistor Qp2 and a third PMOS transistor Qp3;

[0085] The source of the second PMOS transistor Qp2 serves as the first terminal of the first positive feedback module 122, the source of the third PMOS transistor Qp3 serves as the second terminal of the first positive feedback module 122, the drain of the second PMOS transistor Qp2 serves as the third terminal of the first positive feedback module 122, the drain of the third PMOS transistor Qp3 serves as the fourth terminal of the first positive feedback module 122, the gate of the second PMOS transistor Qp2 is connected to the source of the third PMOS transistor Qp3, and the gate of the third PMOS transistor Qp3 is connected to the source of the second PMOS transistor Qp2.

[0086] In practical applications, the first positive feedback module 122 mainly pulls down the source voltage of the second PMOS transistor Qp2 to GND when the source voltage of the second PMOS transistor Qp2 is pulled low, and pulls up the source voltage of the third PMOS transistor Qp3 to the voltage of the power supply connected to the third and fourth terminals of the first positive feedback module 122. Similarly, when the source voltage of the third PMOS transistor Qp3 is pulled low, it pulls down the source voltage of the third PMOS transistor Qp3 to GND, and pulls up the source voltage of the second PMOS transistor Qp2 to the voltage of the power supply connected to the third and fourth terminals of the first positive feedback module 122. Conversely, when the source voltage of the second PMOS transistor Qp2 is pulled up, the source voltage of the second PMOS transistor Qp2 is pulled up to the voltage of the power supply connected to the third and fourth terminals of the first positive feedback module 122, and the source voltage of the third PMOS transistor Qp3 is pulled down to GND; similarly, when the source voltage of the third PMOS transistor Qp3 is pulled up, the source voltage of the third PMOS transistor Qp3 is pulled up to the voltage of the power supply connected to the third and fourth terminals of the first positive feedback module 122, and the source voltage of the second PMOS transistor Qp2 is pulled down to GND.

[0087] In specific implementations, the first inverter module 121 in the potential conversion circuit provided in this embodiment of the invention can have various specific structures to realize its function. For example... Figure 7 As shown, the first inverter module 121 includes: a fourth PMOS transistor Qp4 and a sixth NMOS transistor Qn6;

[0088] The gate of the fourth PMOS transistor Qp4 serves as the first terminal of the first inverter module 121, the drain of the fourth PMOS transistor Qp4 serves as the second terminal of the first inverter module 121, and the source of the fourth PMOS transistor Qp4 serves as the fourth terminal of the first inverter module 121.

[0089] The gate of the sixth NMOS transistor Qn6 is connected to the gate of the fourth PMOS transistor Qp4, the drain of the sixth NMOS transistor Qn6 is connected to the source of the fourth PMOS transistor Qp4, and the source of the sixth NMOS transistor Qn6 serves as the third terminal of the first inverter module 121.

[0090] In practical applications, when the first input of the first inverter module 121 is VDDH, the fourth PMOS transistor Qp4 is turned off, the sixth NMOS transistor Qn6 is turned on, and the fourth output of the first inverter module 121 is GND; when the first input of the first inverter module 121 is GND, the fourth PMOS transistor Qp4 is turned on, the sixth NMOS transistor Qn6 is turned off, and the fourth output of the first inverter module 121 is VDDH.

[0091] In specific implementations, the second potential conversion circuit 130 in the potential conversion circuit provided in this embodiment of the invention can have various specific structures to realize its function. For example... Figure 8 As shown, the first type of second potential conversion circuit 130 in this application embodiment includes at least: a second inverter module 131, a second positive feedback module 132, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, a seventh NMOS transistor Qn7, an eighth NMOS transistor Qn8, a ninth NMOS transistor Qn9, and a fifth PMOS transistor Qp5;

[0092] The input terminal of the third inverter inv3 is connected to the external first circuit. The output terminal of the third inverter inv3 is connected to the input terminal of the fourth inverter inv4 and the gate of the seventh NMOS transistor Qn7. The output terminal of the fourth inverter inv4 is connected to the gate of the eighth NMOS transistor Qn8. The input terminal of the fifth inverter inv5 is connected to the fourth terminal of the first potential conversion circuit 120. The output terminal of the fifth inverter inv5 is connected to the input terminal of the sixth inverter inv6. The output terminal of the sixth inverter inv6 is connected to the gate of the ninth NMOS transistor Qn9. The first power supply terminals of the third inverter inv3 and the fourth inverter inv4 are connected to the first power supply 140. The first power supply terminals of the fifth inverter inv5 and the sixth inverter inv6 are connected to the second power supply 150. The second power supply terminals of the third inverter inv3, the fourth inverter inv4, the fifth inverter inv5, and the sixth inverter inv6 are all connected to ground.

[0093] The drain of the seventh NMOS transistor Qn7 is connected to the first terminal of the second positive feedback module 132, the drain of the eighth NMOS transistor Qn8 is connected to the second terminal of the second positive feedback module 132, and the sources of both the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 are connected to the drain of the ninth NMOS transistor Qn9; the third and fourth terminals of the second positive feedback module 132 are both connected to the second power supply 150.

[0094] The first terminal of the second inverter module 131 is connected to the second terminal of the second positive feedback module 132, the second terminal of the second inverter module 131 is connected to the second power supply 150, the third terminal of the second inverter module 131 is connected to ground, and the fourth terminal of the second inverter module 131 is connected to the external second circuit.

[0095] The gate of the fifth PMOS transistor Qp5 is connected to the output terminal of the sixth inverter inv6, the source of the fifth PMOS transistor Qp5 is connected to the first terminal of the second inverter module 131, and the drain of the fifth PMOS transistor Qp5 is connected to the second power supply 150.

[0096] In practical applications, the specific configuration of the second inverter module 131 and the second positive feedback module 132 in the second potential conversion circuit 130 can be the same as that of the first inverter module 121 composed of the fifth PMOS transistor Qp5 and the sixth NMOS transistor Qn6, and the first positive feedback module 122 composed of the second PMOS transistor Qp2 and the third PMOS transistor Qp3 in the first potential conversion circuit 120. Alternatively, other circuits capable of achieving the corresponding functions can be used. The working principle of the first type of second potential conversion circuit 130 is as follows:

[0097] After the first power supply 140 is powered on, the voltage of the power-on status signal POH, with the second power supply 150 as the voltage domain, is VDDH. The voltage of node Vg is VDDH, the ninth NMOS transistor Qn9 is turned on, and the fifth PMOS transistor Qp5 is turned off. When the digital signal Vil input from the external first circuit is VDDL, the voltage of node Vc is VDDL, the voltage of node Vb is GND, the seventh NMOS transistor Qn7 is turned on, the eighth NMOS transistor Qn8 is turned off, and the voltage of node Vd is pulled low. The second positive feedback module 132, composed of PMOS transistors Q1 and Q2, further pulls the voltage of node Vd down to GND and further pulls the voltage of node Ve up to VDDH. The voltage of node Vd is output as VDDH through the second inverter module 131, composed of PMOS transistors Q3 and Q4, which is the target digital signal Voh output to the external second circuit. When the digital signal Vil input to the external first circuit is GND, the voltage of node Vc is GND, the voltage of node Vb is VDDL, the seventh NMOS transistor Qn7 is turned off, the eighth NMOS transistor Qn8 is turned on, the voltage of node Ve is pulled low, and the second positive feedback module 132 composed of PMOS transistors Q1 and Q2 further pulls the voltage of node Ve down to GND and pulls the voltage of node Vd up to VDDH. The voltage of node Vd is output as GND through the second inverter module 131 composed of PMOS transistors Q3 and Q4, which is the target digital signal Voh output to the external second circuit.

[0098] When the first power supply 140 is de-energized, the power-on status signal POH of the second power supply 150 is set to GND, the voltage at node Vg is GND, the ninth NMOS transistor Qn9 is turned off, and the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 have no path to GND. With the voltage at node Vg at GND, the fifth PMOS transistor Qp5 is turned on, pulling the voltage at node Vd up to VDDH. The second positive feedback module 132, composed of PMOS transistors Q1 and Q2, further pulls the voltage at node Ve down to GND and further pulls the voltage at node Vd up to VDDH. The voltage at node Vd is output to GND via the second inverter module 131, composed of PMOS transistors Q3 and Q4, which is the target digital signal Voh output to the external second circuit.

[0099] In this way, by setting the ninth NMOS transistor Qn9 to disconnect when the first power supply 140 is powered off, the path from the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 to GND is cut off, so that the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 have a definite cut-off state. This avoids the problem of uncertain switching states of the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 when the first power supply 140 is powered off, and the circuit has no leakage problem. In addition, the fifth PMOS transistor Qp5 is set to give the voltage of the Vd node a definite potential VDDH when the first power supply 140 is powered off, so that the second positive feedback module 132 operates in a definite state, so that the target digital signal Voh output to the external second circuit is a definite state GND, and the external second circuit can also operate in a definite state.

[0100] In specific implementations, the second potential conversion circuit 130 in the potential conversion circuit provided in this embodiment of the invention can have various specific structures to realize its function. For example... Figure 9 As shown, the second type of second potential conversion circuit 130 in this embodiment of the application includes at least: a second inverter module 131, a second positive feedback module 132, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, a seventh NMOS transistor Qn7, an eighth NMOS transistor Qn8, a ninth NMOS transistor Qn9, and a tenth NMOS transistor Qn10;

[0101] The input terminal of the third inverter inv3 is connected to the external first circuit. The output terminal of the third inverter inv3 is connected to the input terminal of the fourth inverter inv4 and the gate of the seventh NMOS transistor Qn7. The output terminal of the fourth inverter inv4 is connected to the gate of the eighth NMOS transistor Qn8. The input terminal of the fifth inverter inv5 is connected to the fourth terminal of the first potential conversion circuit 120. The output terminal of the fifth inverter inv5 is connected to the input terminal of the sixth inverter inv6. The output terminal of the sixth inverter inv6 is connected to the gate of the ninth NMOS transistor Qn9. The first power supply terminals of the third inverter inv3 and the fourth inverter inv4 are connected to the first power supply 140. The first power supply terminals of the fifth inverter inv5 and the sixth inverter inv6 are connected to the second power supply 150. The second power supply terminals of the third inverter inv3, the fourth inverter inv4, the fifth inverter inv5, and the sixth inverter inv6 are all connected to ground.

[0102] The drain of the seventh NMOS transistor Qn7 is connected to the first terminal of the second positive feedback module 132, the drain of the eighth NMOS transistor Qn8 is connected to the second terminal of the second positive feedback module 132, and the sources of both the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 are connected to the drain of the ninth NMOS transistor Qn9; the third and fourth terminals of the second positive feedback module 132 are both connected to the second power supply 150.

[0103] The first terminal of the second inverter module 131 is connected to the second terminal of the second positive feedback module 132, the second terminal of the second inverter module 131 is connected to the second power supply 150, the third terminal of the second inverter module 131 is connected to ground, and the fourth terminal of the second inverter module 131 is connected to the external second circuit.

[0104] The gate of the tenth NMOS transistor Qn10 is connected to the output terminal of the fifth inverter inv5, the source of the tenth NMOS transistor Qn10 is connected to ground, and the drain of the tenth NMOS transistor Qn10 is connected to the first terminal of the second inverter module 131.

[0105] In practical applications, the second type of second potential conversion circuit 130 replaces the fifth PMOS transistor Qp5 in the first type of second potential conversion circuit 130 with the tenth NMOS transistor Qn10. The gate of the tenth NMOS transistor Qn10 is connected to the output of the fifth inverter inv5, the source of the tenth NMOS transistor Qn10 is connected to ground, and the drain of the tenth NMOS transistor Qn10 is connected to the first terminal of the second inverter module 131. The tenth NMOS transistor Qn10 is used to provide a defined GND potential to the voltage at node Vd when the first power supply 140 is de-energized. Specifically, when the first power supply 140 is de-energized, the power-on state signal POH of the second power supply 150 is GND, the voltage at node Vg is GND, the ninth NMOS transistor Qn9 is turned off, and the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 have no path to GND. The voltage at node Vj is VDDH, and the tenth NMOS transistor Qn10 is turned on, pulling the voltage at node Vd down to GND. The second positive feedback module 132, composed of PMOS transistors Q1 and Q2, further pulls up the voltage at the Ve node to VDDH and further pulls down the voltage at the Vd node to GND. The voltage at the Vd node is output as VDDH through the second inverter module 131, composed of PMOS transistors Q3 and Q4, which is the target digital signal Voh output to the external second circuit. After the first power supply 140 is powered on, the tenth NMOS transistor Qn10 is turned off, and the other operating principles are the same as those of the first type of second potential conversion circuit 130.

[0106] In this way, by setting the ninth NMOS transistor Qn9 to disconnect when the first power supply 140 is powered off, the path from the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 to GND is cut off, so that the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 have a definite cut-off state, avoiding the problem of uncertain switching state of the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 when the first power supply 140 is powered off, and the circuit has no leakage problem. In addition, the tenth NMOS transistor Qn10 is set to give the voltage of the Vd node a definite GND potential when the first power supply 140 is powered off, so that the second positive feedback module 132 operates in a definite state, so that the target digital signal Voh output to the external second circuit is a definite state VDDH, and the external second circuit can also operate in a definite state.

[0107] In specific implementations, the second potential conversion circuit 130 in the potential conversion circuit provided in this embodiment of the invention can have various specific structures to realize its function. For example... Figure 10As shown, the third type of second potential conversion circuit 130 in this embodiment includes at least: a second inverter module 131, a second positive feedback module 132, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, a seventh NMOS transistor Qn7, an eighth NMOS transistor Qn8, a ninth NMOS transistor Qn9, a tenth NMOS transistor Qn10, and a fifth PMOS transistor Qp5;

[0108] The input terminal of the third inverter inv3 is connected to the external first circuit. The output terminal of the third inverter inv3 is connected to the input terminal of the fourth inverter inv4 and the gate of the seventh NMOS transistor Qn7. The output terminal of the fourth inverter inv4 is connected to the gate of the eighth NMOS transistor Qn8. The input terminal of the fifth inverter inv5 is connected to the fourth terminal of the first potential conversion circuit 120. The output terminal of the fifth inverter inv5 is connected to the input terminal of the sixth inverter inv6. The output terminal of the sixth inverter inv6 is connected to the gate of the ninth NMOS transistor Qn8. The gate of MOSFET Qn9 is connected to the gate of the tenth NMOS transistor Qn10; the first power supply terminal of the third inverter inv3 and the first power supply terminal of the fourth inverter inv4 are connected to the first power supply 140, the first power supply terminal of the fifth inverter inv5 and the first power supply terminal of the sixth inverter inv6 are connected to the second power supply 150, and the second power supply terminals of the third inverter inv3, the fourth inverter inv4, the fifth inverter inv5 and the sixth inverter inv6 are all connected to ground;

[0109] The drain of the ninth NMOS transistor Qn9 is connected to the first terminal of the second positive feedback module 132, the source of the ninth NMOS transistor Qn9 is connected to the drain of the seventh NMOS transistor Qn7, and the base of the ninth NMOS transistor Qn9 is connected to ground; the drain of the tenth NMOS transistor Qn10 is connected to the second terminal of the second positive feedback module 132, the source of the tenth NMOS transistor Qn10 is connected to the drain of the eighth NMOS transistor Qn8, and the base of the tenth NMOS transistor Qn10 is connected to ground; the sources of the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 are both connected to ground; the third and fourth terminals of the second positive feedback module 132 are both connected to the second power supply 150;

[0110] The first terminal of the second inverter module 131 is connected to the second terminal of the second positive feedback module 132, the second terminal of the second inverter module 131 is connected to the second power supply 150, the third terminal of the second inverter module 131 is connected to ground, and the fourth terminal of the second inverter module 131 is connected to the external second circuit.

[0111] The gate of the fifth PMOS transistor Qp5 is connected to the output terminal of the sixth inverter inv6, the source of the fifth PMOS transistor Qp5 is connected to the first terminal of the second inverter module 131, and the drain of the fifth PMOS transistor Qp5 is connected to the second power supply 150.

[0112] In practical applications, the third type of second potential conversion circuit 130 in this embodiment replaces the ninth NMOS transistor Qn9 between the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 and ground in the first type of second potential conversion circuit 130 by setting a ninth NMOS transistor Qn9 and a tenth NMOS transistor Qn10 between the second positive feedback module 132 and the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8. The ninth NMOS transistor Qn9 is used to disconnect or connect the seventh NMOS transistor Qn7 and the second positive feedback module 132, thereby disconnecting or connecting the path from the seventh NMOS transistor Qn7 to VDDH. The tenth NMOS transistor Qn10 is used to disconnect or connect the eighth NMOS transistor Qn8 and the second positive feedback module 132, thereby disconnecting or connecting the path from the eighth NMOS transistor Qn8 to VDDH. The working principle of the third type of second potential conversion circuit 130 is as follows:

[0113] After the first power supply 140 is powered on, the voltage of the power-on status signal POH, with the second power supply 150 as the voltage domain, is VDDH. The voltage of node Vg is also VDDH. The ninth NMOS transistor Qn9 and the tenth NMOS transistor Qn10 are turned on, while the fifth PMOS transistor Qp5 is turned off. The operating states of other devices and the voltages of the nodes are the same as in the first type of second potential conversion circuit 130.

[0114] When the first power supply 140 is de-energized, the power-on status signal POH of the second power supply 150 is set to GND, the voltage at node Vg is GND, the ninth NMOS transistor Qn9 and the tenth NMOS transistor Qn10 are both turned off, and the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 have no path to VDDH. With the voltage at node Vg at GND, the fifth PMOS transistor Qp5 is turned on, pulling the voltage at node Vd up to VDDH. The second positive feedback module 132, composed of PMOS transistors Q1 and Q2, further pulls the voltage at node Ve down to GND and further pulls the voltage at node Vd up to VDDH. The voltage at node Vd is output as GND through the second inverter module 131, composed of PMOS transistors Q3 and Q4, which is the target digital signal Voh output to the external second circuit.

[0115] In this way, by setting the ninth NMOS transistor Qn9 and the tenth NMOS transistor Qn10 to disconnect when the first power supply 140 is powered off, the path from the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 to GND is cut off, so that the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 have a definite cut-off state, avoiding the problem of uncertain switching state of the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 when the first power supply 140 is powered off, and the circuit has no leakage problem. In addition, the fifth PMOS transistor Qp5 is set to give the voltage of the Vd node a definite potential VDDH when the first power supply 140 is powered off, so that the second positive feedback module 132 operates in a definite state, so that the target digital signal Voh output to the external second circuit is a definite state GND, and the external second circuit can also operate in a definite state.

[0116] In specific implementations, the second potential conversion circuit 130 in the potential conversion circuit provided in this embodiment of the invention can have various specific structures to realize its function. For example... Figure 11 As shown, the fourth type of second potential conversion circuit 130 in this embodiment includes at least: a second inverter module 131, a second positive feedback module 132, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, a seventh NMOS transistor Qn7, an eighth NMOS transistor Qn8, a ninth NMOS transistor Qn9, a tenth NMOS transistor Qn10, and an eleventh NMOS transistor Qn11;

[0117] The input terminal of the third inverter inv3 is connected to the external first circuit. The output terminal of the third inverter inv3 is connected to the input terminal of the fourth inverter inv4 and the gate of the seventh NMOS transistor Qn7. The output terminal of the fourth inverter inv4 is connected to the gate of the eighth NMOS transistor Qn8. The input terminal of the fifth inverter inv5 is connected to the fourth terminal of the first potential conversion circuit 120. The output terminal of the fifth inverter inv5 is connected to the input terminal of the sixth inverter inv6. The output terminal of the sixth inverter inv6 is connected to the gate of the ninth NMOS transistor Qn8. The gate of MOSFET Qn9 is connected to the gate of the tenth NMOS transistor Qn10; the first power supply terminal of the third inverter inv3 and the first power supply terminal of the fourth inverter inv4 are connected to the first power supply 140, the first power supply terminal of the fifth inverter inv5 and the first power supply terminal of the sixth inverter inv6 are connected to the second power supply 150, and the second power supply terminals of the third inverter inv3, the fourth inverter inv4, the fifth inverter inv5 and the sixth inverter inv6 are all connected to ground;

[0118] The drain of the ninth NMOS transistor Qn9 is connected to the first terminal of the second positive feedback module 132, the source of the ninth NMOS transistor Qn9 is connected to the drain of the seventh NMOS transistor Qn7, and the base of the ninth NMOS transistor Qn9 is connected to ground; the drain of the tenth NMOS transistor Qn10 is connected to the second terminal of the second positive feedback module 132, the source of the tenth NMOS transistor Qn10 is connected to the drain of the eighth NMOS transistor Qn8, and the base of the tenth NMOS transistor Qn10 is connected to ground; the sources of the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 are both connected to ground; the third and fourth terminals of the second positive feedback module 132 are both connected to the second power supply 150;

[0119] The first terminal of the second inverter module 131 is connected to the second terminal of the second positive feedback module 132, the second terminal of the second inverter module 131 is connected to the second power supply 150, the third terminal of the second inverter module 131 is connected to ground, and the fourth terminal of the second inverter module 131 is connected to the external second circuit.

[0120] The gate of the eleventh NMOS transistor Qn11 is connected to the output terminal of the fifth inverter inv5, the source of the eleventh NMOS transistor Qn11 is connected to ground, and the drain of the eleventh NMOS transistor Qn11 is connected to the first terminal of the second inverter module 131.

[0121] In practical applications, the fourth type of second potential conversion circuit 130 replaces the fifth PMOS transistor Qp5 in the third type of second potential conversion circuit 130 with the eleventh NMOS transistor Qn11. The gate of the eleventh NMOS transistor Qn11 is connected to the output of the fifth inverter inv5, the source of the eleventh NMOS transistor Qn11 is connected to ground, and the drain of the eleventh NMOS transistor Qn11 is connected to the first terminal of the second inverter module 131. The tenth NMOS transistor Qn10 is used to provide a defined GND potential to the voltage at node Vd when the first power supply 140 is powered off. Specifically, when the first power supply 140 is powered off, the power-on status signal POH of the second power supply 150 is used as GND, the voltage at node Vg is GND, the ninth NMOS transistor Qn9 and the tenth NMOS transistor Qn10 are both turned off, and the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 have no path to VDDH. The voltage at node Vj is VDDH, and the eleventh NMOS transistor Qn11 is turned on, pulling the voltage at node Vd down to GND. The second positive feedback module 132, composed of PMOS transistors Q1 and Q2, further pulls the voltage at node Vd down to GND and further pulls the voltage at node Ve up to VDDH. The voltage at node Vd is then output as VDDH by the second inverter module 131, composed of PMOS transistors Q3 and Q4, which is the target digital signal Voh output to the external second circuit. After the first power supply 140 is powered on, the eleventh NMOS transistor Qn11 is turned off; other operating principles are the same as the third type of second potential conversion circuit 130.

[0122] In this way, by setting the ninth NMOS transistor Qn9 to disconnect when the first power supply 140 is powered off, the path from the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 to GND is cut off, so that the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 have a definite cut-off state, avoiding the problem of uncertain switching state of the seventh NMOS transistor Qn7 and the eighth NMOS transistor Qn8 when the first power supply 140 is powered off, and the circuit has no leakage problem. In addition, the tenth NMOS transistor Qn10 is set to give the voltage of the Vd node a definite GND potential when the first power supply 140 is powered off, so that the second positive feedback module 132 operates in a definite state, so that the target digital signal Voh output to the external second circuit is a definite state VDDH, and the external second circuit can also operate in a definite state.

[0123] In addition, based on the above embodiments, this application also provides a chip 200, see reference. Figure 12 As shown, the chip 200 provided in this application embodiment includes at least: a first circuit 210, a second circuit 220, and the potential conversion circuit 100 provided in this application embodiment;

[0124] The input terminal of the potential conversion circuit 100 is connected to the first circuit 210, and the output terminal of the potential conversion circuit is connected to the second circuit 220. The functionality of the chip provided in this application embodiment is detailed in the above-described voltage regulator circuit embodiment, and will not be repeated here.

[0125] It should be noted that although several units or sub-units of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units.

[0126] Furthermore, although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0127] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0128] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A potential conversion circuit, characterized in that, include: The circuit includes a power-on detection circuit, a first potential conversion circuit, a second potential conversion circuit, a first power supply, and a second power supply; wherein the voltage of the first power supply is lower than the voltage of the second power supply. The first terminal of the power-on state detection circuit is connected to the first power supply, the second terminal of the power-on state detection circuit is connected to the first terminal of the first potential conversion circuit, and the third terminal of the power-on state detection circuit is connected to ground; the power-on state detection circuit is used to detect the voltage value of the first power supply and generate a power-on state signal based on the voltage value of the first power supply. The second terminal of the first potential conversion circuit is connected to the first power supply, the third terminal of the first potential conversion circuit is connected to the second power supply, the fourth terminal of the first potential conversion circuit is connected to the first terminal of the second potential conversion circuit, and the fifth terminal of the first potential conversion circuit is connected to ground; the first potential conversion circuit is used to convert the power-on status signal into a power-on status signal with the second power supply as the voltage domain. The second terminal of the second potential conversion circuit is connected to the external first circuit, the third terminal of the second potential conversion circuit is connected to the first power supply, the fourth terminal of the second potential conversion circuit is connected to the second power supply, the fifth terminal of the second potential conversion circuit is connected to the external second circuit, and the sixth terminal of the second potential conversion circuit is connected to ground. The second potential conversion circuit is used to determine the target digital signal to be output to the external second circuit based on the power-on state signal of the second power supply as the voltage domain and the digital signal input to the external first circuit, and when the power-on state signal of the second power supply as the voltage domain is the power-off state signal, it controls the target digital signal output to the second circuit to be a fixed value.

2. The potential conversion circuit as described in claim 1, characterized in that, The first potential conversion circuit includes: a first inverter module, a first positive feedback module, a charge / discharge module, a first inverter, a second inverter, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a first resistor; The gate of the first NMOS transistor is connected to the second terminal of the power-on state detection circuit. The drain of the first NMOS transistor is connected to the source, gate, and third gate of the second NMOS transistor, and the first terminal of the charge / discharge module. The source of the first NMOS transistor is connected to ground. The drain of the second NMOS transistor is connected to the second terminal of the charge / discharge module via a first resistor. The second terminal of the charge / discharge module is also connected to the second power supply. The base of the second NMOS transistor is connected to ground. The drain of the third NMOS transistor is connected to the first positive feedback module. The third NMOS transistor has two terminals connected. The source of the third NMOS transistor is connected to the source of the first NMOS transistor and ground, respectively. The gate of the fourth NMOS transistor is connected to the output terminal of the first inverter. The drain of the fourth NMOS transistor is connected to the second terminal of the first positive feedback module. The source of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor and ground, respectively. The gate of the fifth NMOS transistor is connected to the output terminal of the second inverter. The drain of the fifth NMOS transistor is connected to the first terminal of the first positive feedback module. The source of the fifth NMOS transistor is connected to ground, and the drain of the fifth NMOS transistor is connected to ground. The first terminal of the first positive feedback module is connected to the first terminal of the first inverter module, and the third and fourth terminals of the first positive feedback module are both connected to the second power supply. The second terminal of the first inverter module is connected to the second power supply, the third terminal of the first inverter module is connected to ground, and the fourth terminal of the first inverter module is connected to the first terminal of the second potential conversion circuit. The input terminal of the first inverter is connected to the second terminal of the power-on state detection circuit, and the output terminal of the first inverter is connected to the input terminal of the second inverter; the first power supply terminal of the first inverter and the first power supply terminal of the second inverter are connected to the first power supply, and the second power supply terminal of the first inverter and the second power supply terminal of the second inverter are connected to ground.

3. The potential conversion circuit as described in claim 2, characterized in that, The charging and discharging module includes: a first PMOS transistor or a capacitor; The gate of the first PMOS transistor is connected to the drain of the first NMOS transistor, the source of the first PMOS transistor is connected to the drain of the second NMOS transistor via a first resistor, and the drain of the first PMOS transistor is connected to the first power supply. The first terminal of the capacitor is connected to the drain of the first NMOS transistor, the second terminal of the capacitor is connected to the first power supply, and the second terminal of the capacitor is also connected to the drain of the second NMOS transistor via a first resistor.

4. The potential conversion circuit as described in claim 3, characterized in that, The first positive feedback module includes: a second PMOS transistor and a third PMOS transistor; The source of the second PMOS transistor serves as the first terminal of the first positive feedback module, the source of the third PMOS transistor serves as the second terminal of the first positive feedback module, the drain of the second PMOS transistor serves as the third terminal of the first positive feedback module, the drain of the third PMOS transistor serves as the fourth terminal of the first positive feedback module, the gate of the second PMOS transistor is connected to the source of the third PMOS transistor, and the gate of the third PMOS transistor is connected to the source of the second PMOS transistor.

5. The potential conversion circuit as described in claim 4, characterized in that, The first inverter module includes: a fourth PMOS transistor and a sixth NMOS transistor; The gate of the fourth PMOS transistor serves as the first terminal of the first inverter module, the drain of the fourth PMOS transistor serves as the second terminal of the first inverter module, and the source of the fourth PMOS transistor serves as the fourth terminal of the first inverter module. The gate of the sixth NMOS transistor is connected to the gate of the fourth PMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the fourth PMOS transistor, and the source of the sixth NMOS transistor serves as the third terminal of the first inverter module.

6. The potential conversion circuit according to any one of claims 3-5, characterized in that, The second potential conversion circuit includes: a second inverter module, a second positive feedback module, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a fifth PMOS transistor; The input terminal of the third inverter is connected to an external first circuit. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the gate of the seventh NMOS transistor, respectively. The output terminal of the fourth inverter is connected to the gate of the eighth NMOS transistor. The input terminal of the fifth inverter is connected to the fourth terminal of the first potential conversion circuit. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the gate of the ninth NMOS transistor. The first power supply terminals of the third and fourth inverters are connected to the first power supply. The first power supply terminals of the fifth and sixth inverters are connected to the second power supply. The second power supply terminals of the third, fourth, fifth, and sixth inverters are all connected to ground. The drain of the seventh NMOS transistor is connected to the first terminal of the second positive feedback module, the drain of the eighth NMOS transistor is connected to the second terminal of the second positive feedback module, and the sources of the seventh and eighth NMOS transistors are both connected to the drain of the ninth NMOS transistor; the third and fourth terminals of the second positive feedback module are both connected to the second power supply. The first terminal of the second inverter module is connected to the second terminal of the second positive feedback module, the second terminal of the second inverter module is connected to the second power supply, the third terminal of the second inverter module is connected to ground, and the fourth terminal of the second inverter module is connected to the external second circuit. The gate of the fifth PMOS transistor is connected to the output terminal of the sixth inverter, the source of the fifth PMOS transistor is connected to the first terminal of the second inverter module, and the drain of the fifth PMOS transistor is connected to the second power supply.

7. The potential conversion circuit according to any one of claims 3-5, characterized in that, The second potential conversion circuit includes: a second inverter module, a second positive feedback module, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; The input terminal of the third inverter is connected to an external first circuit. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the gate of the seventh NMOS transistor, respectively. The output terminal of the fourth inverter is connected to the gate of the eighth NMOS transistor. The input terminal of the fifth inverter is connected to the fourth terminal of the first potential conversion circuit. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the gate of the ninth NMOS transistor. The first power supply terminals of the third and fourth inverters are connected to the first power supply. The first power supply terminals of the fifth and sixth inverters are connected to the second power supply. The second power supply terminals of the third, fourth, fifth, and sixth inverters are all connected to ground. The drain of the seventh NMOS transistor is connected to the first terminal of the second positive feedback module, the drain of the eighth NMOS transistor is connected to the second terminal of the second positive feedback module, and the sources of the seventh and eighth NMOS transistors are both connected to the drain of the ninth NMOS transistor; the third and fourth terminals of the second positive feedback module are both connected to the second power supply. The first terminal of the second inverter module is connected to the second terminal of the second positive feedback module, the second terminal of the second inverter module is connected to the second power supply, the third terminal of the second inverter module is connected to ground, and the fourth terminal of the second inverter module is connected to the external second circuit. The gate of the tenth NMOS transistor is connected to the output terminal of the fifth inverter, the source of the tenth NMOS transistor is connected to ground, and the drain of the tenth NMOS transistor is connected to the first terminal of the second inverter module.

8. The potential conversion circuit according to any one of claims 3-5, characterized in that, The second potential conversion circuit includes: a second inverter module, a second positive feedback module, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and a fifth PMOS transistor; The input terminal of the third inverter is connected to an external first circuit. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the gate of the seventh NMOS transistor, respectively. The output terminal of the fourth inverter is connected to the gate of the eighth NMOS transistor. The input terminal of the fifth inverter is connected to the fourth terminal of the first potential conversion circuit. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor, respectively. The first power supply terminals of the third and fourth inverters are connected to the first power supply. The first power supply terminals of the fifth and sixth inverters are connected to the second power supply. The second power supply terminals of the third, fourth, fifth, and sixth inverters are all connected to ground. The drain of the ninth NMOS transistor is connected to the first terminal of the second positive feedback module, the source of the ninth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the base of the ninth NMOS transistor is connected to ground; the drain of the tenth NMOS transistor is connected to the second terminal of the second positive feedback module, the source of the tenth NMOS transistor is connected to the drain of the eighth NMOS transistor, and the base of the tenth NMOS transistor is connected to ground; the sources of the seventh NMOS transistor and the eighth NMOS transistor are both connected to ground; the third and fourth terminals of the second positive feedback module are both connected to the second power supply. The first terminal of the second inverter module is connected to the second terminal of the second positive feedback module, the second terminal of the second inverter module is connected to the second power supply, the third terminal of the second inverter module is connected to ground, and the fourth terminal of the second inverter module is connected to the external second circuit. The gate of the fifth PMOS transistor is connected to the output terminal of the sixth inverter, the source of the fifth PMOS transistor is connected to the first terminal of the second inverter module, and the drain of the fifth PMOS transistor is connected to the second power supply.

9. The potential conversion circuit according to any one of claims 3-5, characterized in that, The second potential conversion circuit includes: a second inverter module, a second positive feedback module, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor; The input terminal of the third inverter is connected to an external first circuit. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the gate of the seventh NMOS transistor, respectively. The output terminal of the fourth inverter is connected to the gate of the eighth NMOS transistor. The input terminal of the fifth inverter is connected to the fourth terminal of the first potential conversion circuit. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the gate of the ninth NMOS transistor and the gate of the tenth NMOS transistor, respectively. The first power supply terminals of the third and fourth inverters are connected to the first power supply. The first power supply terminals of the fifth and sixth inverters are connected to the second power supply. The second power supply terminals of the third, fourth, fifth, and sixth inverters are all connected to ground. The drain of the ninth NMOS transistor is connected to the first terminal of the second positive feedback module, the source of the ninth NMOS transistor is connected to the drain of the seventh NMOS transistor, and the base of the ninth NMOS transistor is connected to ground; the drain of the tenth NMOS transistor is connected to the second terminal of the second positive feedback module, the source of the tenth NMOS transistor is connected to the drain of the eighth NMOS transistor, and the base of the tenth NMOS transistor is connected to ground; the sources of the seventh NMOS transistor and the eighth NMOS transistor are both connected to ground; the third and fourth terminals of the second positive feedback module are both connected to the second power supply. The first terminal of the second inverter module is connected to the second terminal of the second positive feedback module, the second terminal of the second inverter module is connected to the second power supply, the third terminal of the second inverter module is connected to ground, and the fourth terminal of the second inverter module is connected to the external second circuit. The gate of the eleventh NMOS transistor is connected to the output terminal of the fifth inverter, the source of the eleventh NMOS transistor is connected to ground, and the drain of the eleventh NMOS transistor is connected to the first terminal of the second inverter module.

10. A chip, characterized in that, include: The first circuit, the second circuit, and the potential conversion circuit as described in any one of claims 1 to 9; The input terminal of the potential conversion circuit is connected to the first circuit, and the output terminal of the potential conversion circuit is connected to the second circuit.

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